MC68EZ328.h File Reference

Go to the source code of this file.

Data Structures
struct	__attribute__

Macros
#define	BYTE_REF(addr)   (*((volatile unsigned char*)addr))
#define	WORD_REF(addr)   (*((volatile unsigned short*)addr))
#define	LONG_REF(addr)   (*((volatile unsigned long*)addr))
#define	PUT_FIELD(field, val)   (((val) << field##_SHIFT) & field##_MASK)
#define	GET_FIELD(reg, field)   (((reg) & field##_MASK) >> field##_SHIFT)
#define	SCR_ADDR   0xfffff000
#define	SCR   BYTE_REF(SCR_ADDR)
#define	SCR_WDTH8   0x01 /* 8-Bit Width Select */
#define	SCR_DMAP   0x04 /* Double Map */
#define	SCR_SO   0x08 /* Supervisor Only */
#define	SCR_BETEN   0x10 /* Bus-Error Time-Out Enable */
#define	SCR_PRV   0x20 /* Privilege Violation */
#define	SCR_WPV   0x40 /* Write Protect Violation */
#define	SCR_BETO   0x80 /* Bus-Error TimeOut */
#define	MRR_ADDR   0xfffff004
#define	MRR   LONG_REF(MRR_ADDR)
#define	CSGBA_ADDR   0xfffff100
#define	CSGBB_ADDR   0xfffff102
#define	CSGBC_ADDR   0xfffff104
#define	CSGBD_ADDR   0xfffff106
#define	CSGBA   WORD_REF(CSGBA_ADDR)
#define	CSGBB   WORD_REF(CSGBB_ADDR)
#define	CSGBC   WORD_REF(CSGBC_ADDR)
#define	CSGBD   WORD_REF(CSGBD_ADDR)
#define	CSA_ADDR   0xfffff110
#define	CSB_ADDR   0xfffff112
#define	CSC_ADDR   0xfffff114
#define	CSD_ADDR   0xfffff116
#define	CSA   WORD_REF(CSA_ADDR)
#define	CSB   WORD_REF(CSB_ADDR)
#define	CSC   WORD_REF(CSC_ADDR)
#define	CSD   WORD_REF(CSD_ADDR)
#define	CSA_EN   0x0001 /* Chip-Select Enable */
#define	CSA_SIZ_MASK   0x000e /* Chip-Select Size */
#define	CSA_SIZ_SHIFT   1
#define	CSA_WS_MASK   0x0070 /* Wait State */
#define	CSA_WS_SHIFT   4
#define	CSA_BSW   0x0080 /* Data Bus Width */
#define	CSA_FLASH   0x0100 /* FLASH Memory Support */
#define	CSA_RO   0x8000 /* Read-Only */
#define	CSB_EN   0x0001 /* Chip-Select Enable */
#define	CSB_SIZ_MASK   0x000e /* Chip-Select Size */
#define	CSB_SIZ_SHIFT   1
#define	CSB_WS_MASK   0x0070 /* Wait State */
#define	CSB_WS_SHIFT   4
#define	CSB_BSW   0x0080 /* Data Bus Width */
#define	CSB_FLASH   0x0100 /* FLASH Memory Support */
#define	CSB_UPSIZ_MASK   0x1800 /* Unprotected memory block size */
#define	CSB_UPSIZ_SHIFT   11
#define	CSB_ROP   0x2000 /* Readonly if protected */
#define	CSB_SOP   0x4000 /* Supervisor only if protected */
#define	CSB_RO   0x8000 /* Read-Only */
#define	CSC_EN   0x0001 /* Chip-Select Enable */
#define	CSC_SIZ_MASK   0x000e /* Chip-Select Size */
#define	CSC_SIZ_SHIFT   1
#define	CSC_WS_MASK   0x0070 /* Wait State */
#define	CSC_WS_SHIFT   4
#define	CSC_BSW   0x0080 /* Data Bus Width */
#define	CSC_FLASH   0x0100 /* FLASH Memory Support */
#define	CSC_UPSIZ_MASK   0x1800 /* Unprotected memory block size */
#define	CSC_UPSIZ_SHIFT   11
#define	CSC_ROP   0x2000 /* Readonly if protected */
#define	CSC_SOP   0x4000 /* Supervisor only if protected */
#define	CSC_RO   0x8000 /* Read-Only */
#define	CSD_EN   0x0001 /* Chip-Select Enable */
#define	CSD_SIZ_MASK   0x000e /* Chip-Select Size */
#define	CSD_SIZ_SHIFT   1
#define	CSD_WS_MASK   0x0070 /* Wait State */
#define	CSD_WS_SHIFT   4
#define	CSD_BSW   0x0080 /* Data Bus Width */
#define	CSD_FLASH   0x0100 /* FLASH Memory Support */
#define	CSD_DRAM   0x0200 /* Dram Selection */
#define	CSD_COMB   0x0400 /* Combining */
#define	CSD_UPSIZ_MASK   0x1800 /* Unprotected memory block size */
#define	CSD_UPSIZ_SHIFT   11
#define	CSD_ROP   0x2000 /* Readonly if protected */
#define	CSD_SOP   0x4000 /* Supervisor only if protected */
#define	CSD_RO   0x8000 /* Read-Only */
#define	EMUCS_ADDR   0xfffff118
#define	EMUCS   WORD_REF(EMUCS_ADDR)
#define	EMUCS_WS_MASK   0x0070
#define	EMUCS_WS_SHIFT   4
#define	PLLCR_ADDR   0xfffff200
#define	PLLCR   WORD_REF(PLLCR_ADDR)
#define	PLLCR_DISPLL   0x0008 /* Disable PLL */
#define	PLLCR_CLKEN   0x0010 /* Clock (CLKO pin) enable */
#define	PLLCR_PRESC   0x0020 /* VCO prescaler */
#define	PLLCR_SYSCLK_SEL_MASK   0x0700 /* System Clock Selection */
#define	PLLCR_SYSCLK_SEL_SHIFT   8
#define	PLLCR_LCDCLK_SEL_MASK   0x3800 /* LCD Clock Selection */
#define	PLLCR_LCDCLK_SEL_SHIFT   11
#define	PLLCR_PIXCLK_SEL_MASK   PLLCR_LCDCLK_SEL_MASK
#define	PLLCR_PIXCLK_SEL_SHIFT   PLLCR_LCDCLK_SEL_SHIFT
#define	PLLFSR_ADDR   0xfffff202
#define	PLLFSR   WORD_REF(PLLFSR_ADDR)
#define	PLLFSR_PC_MASK   0x00ff /* P Count */
#define	PLLFSR_PC_SHIFT   0
#define	PLLFSR_QC_MASK   0x0f00 /* Q Count */
#define	PLLFSR_QC_SHIFT   8
#define	PLLFSR_PROT   0x4000 /* Protect P & Q */
#define	PLLFSR_CLK32   0x8000 /* Clock 32 (kHz) */
#define	PCTRL_ADDR   0xfffff207
#define	PCTRL   BYTE_REF(PCTRL_ADDR)
#define	PCTRL_WIDTH_MASK   0x1f /* CPU Clock bursts width */
#define	PCTRL_WIDTH_SHIFT   0
#define	PCTRL_PCEN   0x80 /* Power Control Enable */
#define	IVR_ADDR   0xfffff300
#define	IVR   BYTE_REF(IVR_ADDR)
#define	IVR_VECTOR_MASK   0xF8
#define	ICR_ADDR   0xfffff302
#define	ICR   WORD_REF(ICR_ADDR)
#define	ICR_POL5   0x0080 /* Polarity Control for IRQ5 */
#define	ICR_ET6   0x0100 /* Edge Trigger Select for IRQ6 */
#define	ICR_ET3   0x0200 /* Edge Trigger Select for IRQ3 */
#define	ICR_ET2   0x0400 /* Edge Trigger Select for IRQ2 */
#define	ICR_ET1   0x0800 /* Edge Trigger Select for IRQ1 */
#define	ICR_POL6   0x1000 /* Polarity Control for IRQ6 */
#define	ICR_POL3   0x2000 /* Polarity Control for IRQ3 */
#define	ICR_POL2   0x4000 /* Polarity Control for IRQ2 */
#define	ICR_POL1   0x8000 /* Polarity Control for IRQ1 */
#define	IMR_ADDR   0xfffff304
#define	IMR   LONG_REF(IMR_ADDR)
#define	SPI_IRQ_NUM   0 /* SPI interrupt */
#define	TMR_IRQ_NUM   1 /* Timer interrupt */
#define	UART_IRQ_NUM   2 /* UART interrupt */
#define	WDT_IRQ_NUM   3 /* Watchdog Timer interrupt */
#define	RTC_IRQ_NUM   4 /* RTC interrupt */
#define	KB_IRQ_NUM   6 /* Keyboard Interrupt */
#define	PWM_IRQ_NUM   7 /* Pulse-Width Modulator int. */
#define	INT0_IRQ_NUM   8 /* External INT0 */
#define	INT1_IRQ_NUM   9 /* External INT1 */
#define	INT2_IRQ_NUM   10 /* External INT2 */
#define	INT3_IRQ_NUM   11 /* External INT3 */
#define	IRQ1_IRQ_NUM   16 /* IRQ1 */
#define	IRQ2_IRQ_NUM   17 /* IRQ2 */
#define	IRQ3_IRQ_NUM   18 /* IRQ3 */
#define	IRQ6_IRQ_NUM   19 /* IRQ6 */
#define	IRQ5_IRQ_NUM   20 /* IRQ5 */
#define	SAM_IRQ_NUM   22 /* Sampling Timer for RTC */
#define	EMIQ_IRQ_NUM   23 /* Emulator Interrupt */
#define	SPIM_IRQ_NUM   SPI_IRQ_NUM
#define	TMR1_IRQ_NUM   TMR_IRQ_NUM
#define	IMR_MSPI   (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
#define	IMR_MTMR   (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
#define	IMR_MUART   (1 << UART_IRQ_NUM) /* Mask UART interrupt */
#define	IMR_MWDT   (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
#define	IMR_MRTC   (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
#define	IMR_MKB   (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
#define	IMR_MPWM   (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
#define	IMR_MINT0   (1 << INT0_IRQ_NUM) /* Mask External INT0 */
#define	IMR_MINT1   (1 << INT1_IRQ_NUM) /* Mask External INT1 */
#define	IMR_MINT2   (1 << INT2_IRQ_NUM) /* Mask External INT2 */
#define	IMR_MINT3   (1 << INT3_IRQ_NUM) /* Mask External INT3 */
#define	IMR_MIRQ1   (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
#define	IMR_MIRQ2   (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
#define	IMR_MIRQ3   (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
#define	IMR_MIRQ6   (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
#define	IMR_MIRQ5   (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
#define	IMR_MSAM   (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
#define	IMR_MEMIQ   (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
#define	IMR_MSPIM   IMR_MSPI
#define	IMR_MTMR1   IMR_MTMR
#define	ISR_ADDR   0xfffff30c
#define	ISR   LONG_REF(ISR_ADDR)
#define	ISR_SPI   (1 << SPI_IRQ_NUM) /* SPI interrupt */
#define	ISR_TMR   (1 << TMR_IRQ_NUM) /* Timer interrupt */
#define	ISR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */
#define	ISR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define	ISR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define	ISR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define	ISR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
#define	ISR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */
#define	ISR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */
#define	ISR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */
#define	ISR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */
#define	ISR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define	ISR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define	ISR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define	ISR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define	ISR_IRQ5   (1 << IRQ5_IRQ_NUM) /* IRQ5 */
#define	ISR_SAM   (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
#define	ISR_EMIQ   (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
#define	ISR_SPIM   ISR_SPI
#define	ISR_TMR1   ISR_TMR
#define	IPR_ADDR   0xfffff30c
#define	IPR   LONG_REF(IPR_ADDR)
#define	IPR_SPI   (1 << SPI_IRQ_NUM) /* SPI interrupt */
#define	IPR_TMR   (1 << TMR_IRQ_NUM) /* Timer interrupt */
#define	IPR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */
#define	IPR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define	IPR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define	IPR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define	IPR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
#define	IPR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */
#define	IPR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */
#define	IPR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */
#define	IPR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */
#define	IPR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define	IPR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define	IPR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define	IPR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define	IPR_IRQ5   (1 << IRQ5_IRQ_NUM) /* IRQ5 */
#define	IPR_SAM   (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
#define	IPR_EMIQ   (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
#define	IPR_SPIM   IPR_SPI
#define	IPR_TMR1   IPR_TMR
#define	PADIR_ADDR   0xfffff400 /* Port A direction reg */
#define	PADATA_ADDR   0xfffff401 /* Port A data register */
#define	PAPUEN_ADDR   0xfffff402 /* Port A Pull-Up enable reg */
#define	PADIR   BYTE_REF(PADIR_ADDR)
#define	PADATA   BYTE_REF(PADATA_ADDR)
#define	PAPUEN   BYTE_REF(PAPUEN_ADDR)
#define	PA(x)   (1 << (x))
#define	PBDIR_ADDR   0xfffff408 /* Port B direction reg */
#define	PBDATA_ADDR   0xfffff409 /* Port B data register */
#define	PBPUEN_ADDR   0xfffff40a /* Port B Pull-Up enable reg */
#define	PBSEL_ADDR   0xfffff40b /* Port B Select Register */
#define	PBDIR   BYTE_REF(PBDIR_ADDR)
#define	PBDATA   BYTE_REF(PBDATA_ADDR)
#define	PBPUEN   BYTE_REF(PBPUEN_ADDR)
#define	PBSEL   BYTE_REF(PBSEL_ADDR)
#define	PB(x)   (1 << (x))
#define	PB_CSB0   0x01 /* Use CSB0 as PB[0] */
#define	PB_CSB1   0x02 /* Use CSB1 as PB[1] */
#define	PB_CSC0_RAS0   0x04 /* Use CSC0/RAS0 as PB[2] */
#define	PB_CSC1_RAS1   0x08 /* Use CSC1/RAS1 as PB[3] */
#define	PB_CSD0_CAS0   0x10 /* Use CSD0/CAS0 as PB[4] */
#define	PB_CSD1_CAS1   0x20 /* Use CSD1/CAS1 as PB[5] */
#define	PB_TIN_TOUT   0x40 /* Use TIN/TOUT as PB[6] */
#define	PB_PWMO   0x80 /* Use PWMO as PB[7] */
#define	PCDIR_ADDR   0xfffff410 /* Port C direction reg */
#define	PCDATA_ADDR   0xfffff411 /* Port C data register */
#define	PCPDEN_ADDR   0xfffff412 /* Port C Pull-Down enb. reg */
#define	PCSEL_ADDR   0xfffff413 /* Port C Select Register */
#define	PCDIR   BYTE_REF(PCDIR_ADDR)
#define	PCDATA   BYTE_REF(PCDATA_ADDR)
#define	PCPDEN   BYTE_REF(PCPDEN_ADDR)
#define	PCSEL   BYTE_REF(PCSEL_ADDR)
#define	PC(x)   (1 << (x))
#define	PC_LD0   0x01 /* Use LD0 as PC[0] */
#define	PC_LD1   0x02 /* Use LD1 as PC[1] */
#define	PC_LD2   0x04 /* Use LD2 as PC[2] */
#define	PC_LD3   0x08 /* Use LD3 as PC[3] */
#define	PC_LFLM   0x10 /* Use LFLM as PC[4] */
#define	PC_LLP   0x20 /* Use LLP as PC[5] */
#define	PC_LCLK   0x40 /* Use LCLK as PC[6] */
#define	PC_LACD   0x80 /* Use LACD as PC[7] */
#define	PDDIR_ADDR   0xfffff418 /* Port D direction reg */
#define	PDDATA_ADDR   0xfffff419 /* Port D data register */
#define	PDPUEN_ADDR   0xfffff41a /* Port D Pull-Up enable reg */
#define	PDSEL_ADDR   0xfffff41b /* Port D Select Register */
#define	PDPOL_ADDR   0xfffff41c /* Port D Polarity Register */
#define	PDIRQEN_ADDR   0xfffff41d /* Port D IRQ enable register */
#define	PDKBEN_ADDR   0xfffff41e /* Port D Keyboard Enable reg */
#define	PDIQEG_ADDR   0xfffff41f /* Port D IRQ Edge Register */
#define	PDDIR   BYTE_REF(PDDIR_ADDR)
#define	PDDATA   BYTE_REF(PDDATA_ADDR)
#define	PDPUEN   BYTE_REF(PDPUEN_ADDR)
#define	PDSEL   BYTE_REF(PDSEL_ADDR)
#define	PDPOL   BYTE_REF(PDPOL_ADDR)
#define	PDIRQEN   BYTE_REF(PDIRQEN_ADDR)
#define	PDKBEN   BYTE_REF(PDKBEN_ADDR)
#define	PDIQEG   BYTE_REF(PDIQEG_ADDR)
#define	PD(x)   (1 << (x))
#define	PD_INT0   0x01 /* Use INT0 as PD[0] */
#define	PD_INT1   0x02 /* Use INT1 as PD[1] */
#define	PD_INT2   0x04 /* Use INT2 as PD[2] */
#define	PD_INT3   0x08 /* Use INT3 as PD[3] */
#define	PD_IRQ1   0x10 /* Use IRQ1 as PD[4] */
#define	PD_IRQ2   0x20 /* Use IRQ2 as PD[5] */
#define	PD_IRQ3   0x40 /* Use IRQ3 as PD[6] */
#define	PD_IRQ6   0x80 /* Use IRQ6 as PD[7] */
#define	PEDIR_ADDR   0xfffff420 /* Port E direction reg */
#define	PEDATA_ADDR   0xfffff421 /* Port E data register */
#define	PEPUEN_ADDR   0xfffff422 /* Port E Pull-Up enable reg */
#define	PESEL_ADDR   0xfffff423 /* Port E Select Register */
#define	PEDIR   BYTE_REF(PEDIR_ADDR)
#define	PEDATA   BYTE_REF(PEDATA_ADDR)
#define	PEPUEN   BYTE_REF(PEPUEN_ADDR)
#define	PESEL   BYTE_REF(PESEL_ADDR)
#define	PE(x)   (1 << (x))
#define	PE_SPMTXD   0x01 /* Use SPMTXD as PE[0] */
#define	PE_SPMRXD   0x02 /* Use SPMRXD as PE[1] */
#define	PE_SPMCLK   0x04 /* Use SPMCLK as PE[2] */
#define	PE_DWE   0x08 /* Use DWE as PE[3] */
#define	PE_RXD   0x10 /* Use RXD as PE[4] */
#define	PE_TXD   0x20 /* Use TXD as PE[5] */
#define	PE_RTS   0x40 /* Use RTS as PE[6] */
#define	PE_CTS   0x80 /* Use CTS as PE[7] */
#define	PFDIR_ADDR   0xfffff428 /* Port F direction reg */
#define	PFDATA_ADDR   0xfffff429 /* Port F data register */
#define	PFPUEN_ADDR   0xfffff42a /* Port F Pull-Up enable reg */
#define	PFSEL_ADDR   0xfffff42b /* Port F Select Register */
#define	PFDIR   BYTE_REF(PFDIR_ADDR)
#define	PFDATA   BYTE_REF(PFDATA_ADDR)
#define	PFPUEN   BYTE_REF(PFPUEN_ADDR)
#define	PFSEL   BYTE_REF(PFSEL_ADDR)
#define	PF(x)   (1 << (x))
#define	PF_LCONTRAST   0x01 /* Use LCONTRAST as PF[0] */
#define	PF_IRQ5   0x02 /* Use IRQ5 as PF[1] */
#define	PF_CLKO   0x04 /* Use CLKO as PF[2] */
#define	PF_A20   0x08 /* Use A20 as PF[3] */
#define	PF_A21   0x10 /* Use A21 as PF[4] */
#define	PF_A22   0x20 /* Use A22 as PF[5] */
#define	PF_A23   0x40 /* Use A23 as PF[6] */
#define	PF_CSA1   0x80 /* Use CSA1 as PF[7] */
#define	PGDIR_ADDR   0xfffff430 /* Port G direction reg */
#define	PGDATA_ADDR   0xfffff431 /* Port G data register */
#define	PGPUEN_ADDR   0xfffff432 /* Port G Pull-Up enable reg */
#define	PGSEL_ADDR   0xfffff433 /* Port G Select Register */
#define	PGDIR   BYTE_REF(PGDIR_ADDR)
#define	PGDATA   BYTE_REF(PGDATA_ADDR)
#define	PGPUEN   BYTE_REF(PGPUEN_ADDR)
#define	PGSEL   BYTE_REF(PGSEL_ADDR)
#define	PG(x)   (1 << (x))
#define	PG_BUSW_DTACK   0x01 /* Use BUSW/DTACK as PG[0] */
#define	PG_A0   0x02 /* Use A0 as PG[1] */
#define	PG_EMUIRQ   0x04 /* Use EMUIRQ as PG[2] */
#define	PG_HIZ_P_D   0x08 /* Use HIZ/P/D as PG[3] */
#define	PG_EMUCS   0x10 /* Use EMUCS as PG[4] */
#define	PG_EMUBRK   0x20 /* Use EMUBRK as PG[5] */
#define	PWMC_ADDR   0xfffff500
#define	PWMC   WORD_REF(PWMC_ADDR)
#define	PWMC_CLKSEL_MASK   0x0003 /* Clock Selection */
#define	PWMC_CLKSEL_SHIFT   0
#define	PWMC_REPEAT_MASK   0x000c /* Sample Repeats */
#define	PWMC_REPEAT_SHIFT   2
#define	PWMC_EN   0x0010 /* Enable PWM */
#define	PMNC_FIFOAV   0x0020 /* FIFO Available */
#define	PWMC_IRQEN   0x0040 /* Interrupt Request Enable */
#define	PWMC_IRQ   0x0080 /* Interrupt Request (FIFO empty) */
#define	PWMC_PRESCALER_MASK   0x7f00 /* Incoming Clock prescaler */
#define	PWMC_PRESCALER_SHIFT   8
#define	PWMC_CLKSRC   0x8000 /* Clock Source Select */
#define	PWMC_PWMEN   PWMC_EN
#define	PWMS_ADDR   0xfffff502
#define	PWMS   WORD_REF(PWMS_ADDR)
#define	PWMP_ADDR   0xfffff504
#define	PWMP   BYTE_REF(PWMP_ADDR)
#define	PWMCNT_ADDR   0xfffff505
#define	PWMCNT   BYTE_REF(PWMCNT_ADDR)
#define	TCTL_ADDR   0xfffff600
#define	TCTL   WORD_REF(TCTL_ADDR)
#define	TCTL_TEN   0x0001 /* Timer Enable */
#define	TCTL_CLKSOURCE_MASK   0x000e /* Clock Source: */
#define	TCTL_CLKSOURCE_STOP   0x0000 /* Stop count (disabled) */
#define	TCTL_CLKSOURCE_SYSCLK   0x0002 /* SYSCLK to prescaler */
#define	TCTL_CLKSOURCE_SYSCLK_16   0x0004 /* SYSCLK/16 to prescaler */
#define	TCTL_CLKSOURCE_TIN   0x0006 /* TIN to prescaler */
#define	TCTL_CLKSOURCE_32KHZ   0x0008 /* 32kHz clock to prescaler */
#define	TCTL_IRQEN   0x0010 /* IRQ Enable */
#define	TCTL_OM   0x0020 /* Output Mode */
#define	TCTL_CAP_MASK   0x00c0 /* Capture Edge: */
#define	TCTL_CAP_RE   0x0040 /* Capture on rizing edge */
#define	TCTL_CAP_FE   0x0080 /* Capture on falling edge */
#define	TCTL_FRR   0x0010 /* Free-Run Mode */
#define	TCTL1_ADDR   TCTL_ADDR
#define	TCTL1   TCTL
#define	TPRER_ADDR   0xfffff602
#define	TPRER   WORD_REF(TPRER_ADDR)
#define	TPRER1_ADDR   TPRER_ADDR
#define	TPRER1   TPRER
#define	TCMP_ADDR   0xfffff604
#define	TCMP   WORD_REF(TCMP_ADDR)
#define	TCMP1_ADDR   TCMP_ADDR
#define	TCMP1   TCMP
#define	TCR_ADDR   0xfffff606
#define	TCR   WORD_REF(TCR_ADDR)
#define	TCR1_ADDR   TCR_ADDR
#define	TCR1   TCR
#define	TCN_ADDR   0xfffff608
#define	TCN   WORD_REF(TCN_ADDR)
#define	TCN1_ADDR   TCN_ADDR
#define	TCN1   TCN
#define	TSTAT_ADDR   0xfffff60a
#define	TSTAT   WORD_REF(TSTAT_ADDR)
#define	TSTAT_COMP   0x0001 /* Compare Event occurred */
#define	TSTAT_CAPT   0x0001 /* Capture Event occurred */
#define	TSTAT1_ADDR   TSTAT_ADDR
#define	TSTAT1   TSTAT
#define	SPIMDATA_ADDR   0xfffff800
#define	SPIMDATA   WORD_REF(SPIMDATA_ADDR)
#define	SPIMCONT_ADDR   0xfffff802
#define	SPIMCONT   WORD_REF(SPIMCONT_ADDR)
#define	SPIMCONT_BIT_COUNT_MASK   0x000f /* Transfer Length in Bytes */
#define	SPIMCONT_BIT_COUNT_SHIFT   0
#define	SPIMCONT_POL   0x0010 /* SPMCLK Signel Polarity */
#define	SPIMCONT_PHA   0x0020 /* Clock/Data phase relationship */
#define	SPIMCONT_IRQEN   0x0040 /* IRQ Enable */
#define	SPIMCONT_IRQ   0x0080 /* Interrupt Request */
#define	SPIMCONT_XCH   0x0100 /* Exchange */
#define	SPIMCONT_ENABLE   0x0200 /* Enable SPIM */
#define	SPIMCONT_DATA_RATE_MASK   0xe000 /* SPIM Data Rate */
#define	SPIMCONT_DATA_RATE_SHIFT   13
#define	SPIMCONT_SPIMIRQ   SPIMCONT_IRQ
#define	SPIMCONT_SPIMEN   SPIMCONT_ENABLE
#define	USTCNT_ADDR   0xfffff900
#define	USTCNT   WORD_REF(USTCNT_ADDR)
#define	USTCNT_TXAE   0x0001 /* Transmitter Available Interrupt Enable */
#define	USTCNT_TXHE   0x0002 /* Transmitter Half Empty Enable */
#define	USTCNT_TXEE   0x0004 /* Transmitter Empty Interrupt Enable */
#define	USTCNT_RXRE   0x0008 /* Receiver Ready Interrupt Enable */
#define	USTCNT_RXHE   0x0010 /* Receiver Half-Full Interrupt Enable */
#define	USTCNT_RXFE   0x0020 /* Receiver Full Interrupt Enable */
#define	USTCNT_CTSD   0x0040 /* CTS Delta Interrupt Enable */
#define	USTCNT_ODEN   0x0080 /* Old Data Interrupt Enable */
#define	USTCNT_8_7   0x0100 /* Eight or seven-bit transmission */
#define	USTCNT_STOP   0x0200 /* Stop bit transmission */
#define	USTCNT_ODD   0x0400 /* Odd Parity */
#define	USTCNT_PEN   0x0800 /* Parity Enable */
#define	USTCNT_CLKM   0x1000 /* Clock Mode Select */
#define	USTCNT_TXEN   0x2000 /* Transmitter Enable */
#define	USTCNT_RXEN   0x4000 /* Receiver Enable */
#define	USTCNT_UEN   0x8000 /* UART Enable */
#define	USTCNT_TXAVAILEN   USTCNT_TXAE
#define	USTCNT_TXHALFEN   USTCNT_TXHE
#define	USTCNT_TXEMPTYEN   USTCNT_TXEE
#define	USTCNT_RXREADYEN   USTCNT_RXRE
#define	USTCNT_RXHALFEN   USTCNT_RXHE
#define	USTCNT_RXFULLEN   USTCNT_RXFE
#define	USTCNT_CTSDELTAEN   USTCNT_CTSD
#define	USTCNT_ODD_EVEN   USTCNT_ODD
#define	USTCNT_PARITYEN   USTCNT_PEN
#define	USTCNT_CLKMODE   USTCNT_CLKM
#define	USTCNT_UARTEN   USTCNT_UEN
#define	UBAUD_ADDR   0xfffff902
#define	UBAUD   WORD_REF(UBAUD_ADDR)
#define	UBAUD_PRESCALER_MASK   0x003f /* Actual divisor is 65 - PRESCALER */
#define	UBAUD_PRESCALER_SHIFT   0
#define	UBAUD_DIVIDE_MASK   0x0700 /* Baud Rate freq. divizor */
#define	UBAUD_DIVIDE_SHIFT   8
#define	UBAUD_BAUD_SRC   0x0800 /* Baud Rate Source */
#define	UBAUD_UCLKDIR   0x2000 /* UCLK Direction */
#define	URX_ADDR   0xfffff904
#define	URX   WORD_REF(URX_ADDR)
#define	URX_RXDATA_ADDR   0xfffff905
#define	URX_RXDATA   BYTE_REF(URX_RXDATA_ADDR)
#define	URX_RXDATA_MASK   0x00ff /* Received data */
#define	URX_RXDATA_SHIFT   0
#define	URX_PARITY_ERROR   0x0100 /* Parity Error */
#define	URX_BREAK   0x0200 /* Break Detected */
#define	URX_FRAME_ERROR   0x0400 /* Framing Error */
#define	URX_OVRUN   0x0800 /* Serial Overrun */
#define	URX_OLD_DATA   0x1000 /* Old data in FIFO */
#define	URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */
#define	URX_FIFO_HALF   0x4000 /* FIFO is Half-Full */
#define	URX_FIFO_FULL   0x8000 /* FIFO is Full */
#define	UTX_ADDR   0xfffff906
#define	UTX   WORD_REF(UTX_ADDR)
#define	UTX_TXDATA_ADDR   0xfffff907
#define	UTX_TXDATA   BYTE_REF(UTX_TXDATA_ADDR)
#define	UTX_TXDATA_MASK   0x00ff /* Data to be transmitted */
#define	UTX_TXDATA_SHIFT   0
#define	UTX_CTS_DELTA   0x0100 /* CTS changed */
#define	UTX_CTS_STAT   0x0200 /* CTS State */
#define	UTX_BUSY   0x0400 /* FIFO is busy, sending a character */
#define	UTX_NOCTS   0x0800 /* Ignore CTS */
#define	UTX_SEND_BREAK   0x1000 /* Send a BREAK */
#define	UTX_TX_AVAIL   0x2000 /* Transmit FIFO has a slot available */
#define	UTX_FIFO_HALF   0x4000 /* Transmit FIFO is half empty */
#define	UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */
#define	UTX_CTS_STATUS   UTX_CTS_STAT
#define	UTX_IGNORE_CTS   UTX_NOCTS
#define	UMISC_ADDR   0xfffff908
#define	UMISC   WORD_REF(UMISC_ADDR)
#define	UMISC_TX_POL   0x0004 /* Transmit Polarity */
#define	UMISC_RX_POL   0x0008 /* Receive Polarity */
#define	UMISC_IRDA_LOOP   0x0010 /* IrDA Loopback Enable */
#define	UMISC_IRDA_EN   0x0020 /* Infra-Red Enable */
#define	UMISC_RTS   0x0040 /* Set RTS status */
#define	UMISC_RTSCONT   0x0080 /* Choose RTS control */
#define	UMISC_IR_TEST   0x0400 /* IRDA Test Enable */
#define	UMISC_BAUD_RESET   0x0800 /* Reset Baud Rate Generation Counters */
#define	UMISC_LOOP   0x1000 /* Serial Loopback Enable */
#define	UMISC_FORCE_PERR   0x2000 /* Force Parity Error */
#define	UMISC_CLKSRC   0x4000 /* Clock Source */
#define	UMISC_BAUD_TEST   0x8000 /* Enable Baud Test Mode */
#define	NIPR_ADDR   0xfffff90a
#define	NIPR   WORD_REF(NIPR_ADDR)
#define	NIPR_STEP_VALUE_MASK   0x00ff /* NI prescaler step value */
#define	NIPR_STEP_VALUE_SHIFT   0
#define	NIPR_SELECT_MASK   0x0700 /* Tap Selection */
#define	NIPR_SELECT_SHIFT   8
#define	NIPR_PRE_SEL   0x8000 /* Non-integer prescaler select */
#define	LSSA_ADDR   0xfffffa00
#define	LSSA   LONG_REF(LSSA_ADDR)
#define	LSSA_SSA_MASK   0x1ffffffe /* Bits 0 and 29-31 are reserved */
#define	LVPW_ADDR   0xfffffa05
#define	LVPW   BYTE_REF(LVPW_ADDR)
#define	LXMAX_ADDR   0xfffffa08
#define	LXMAX   WORD_REF(LXMAX_ADDR)
#define	LXMAX_XM_MASK   0x02f0 /* Bits 0-3 and 10-15 are reserved */
#define	LYMAX_ADDR   0xfffffa0a
#define	LYMAX   WORD_REF(LYMAX_ADDR)
#define	LYMAX_YM_MASK   0x01ff /* Bits 9-15 are reserved */
#define	LCXP_ADDR   0xfffffa18
#define	LCXP   WORD_REF(LCXP_ADDR)
#define	LCXP_CC_MASK   0xc000 /* Cursor Control */
#define	LCXP_CC_TRAMSPARENT   0x0000
#define	LCXP_CC_BLACK   0x4000
#define	LCXP_CC_REVERSED   0x8000
#define	LCXP_CC_WHITE   0xc000
#define	LCXP_CXP_MASK   0x02ff /* Cursor X position */
#define	LCYP_ADDR   0xfffffa1a
#define	LCYP   WORD_REF(LCYP_ADDR)
#define	LCYP_CYP_MASK   0x01ff /* Cursor Y Position */
#define	LCWCH_ADDR   0xfffffa1c
#define	LCWCH   WORD_REF(LCWCH_ADDR)
#define	LCWCH_CH_MASK   0x001f /* Cursor Height */
#define	LCWCH_CH_SHIFT   0
#define	LCWCH_CW_MASK   0x1f00 /* Cursor Width */
#define	LCWCH_CW_SHIFT   8
#define	LBLKC_ADDR   0xfffffa1f
#define	LBLKC   BYTE_REF(LBLKC_ADDR)
#define	LBLKC_BD_MASK   0x7f /* Blink Divisor */
#define	LBLKC_BD_SHIFT   0
#define	LBLKC_BKEN   0x80 /* Blink Enabled */
#define	LPICF_ADDR   0xfffffa20
#define	LPICF   BYTE_REF(LPICF_ADDR)
#define	LPICF_GS_MASK   0x03 /* Gray-Scale Mode */
#define	LPICF_GS_BW   0x00
#define	LPICF_GS_GRAY_4   0x01
#define	LPICF_GS_GRAY_16   0x02
#define	LPICF_PBSIZ_MASK   0x0c /* Panel Bus Width */
#define	LPICF_PBSIZ_1   0x00
#define	LPICF_PBSIZ_2   0x04
#define	LPICF_PBSIZ_4   0x08
#define	LPOLCF_ADDR   0xfffffa21
#define	LPOLCF   BYTE_REF(LPOLCF_ADDR)
#define	LPOLCF_PIXPOL   0x01 /* Pixel Polarity */
#define	LPOLCF_LPPOL   0x02 /* Line Pulse Polarity */
#define	LPOLCF_FLMPOL   0x04 /* Frame Marker Polarity */
#define	LPOLCF_LCKPOL   0x08 /* LCD Shift Lock Polarity */
#define	LACDRC_ADDR   0xfffffa23
#define	LACDRC   BYTE_REF(LACDRC_ADDR)
#define	LACDRC_ACDSLT   0x80 /* Signal Source Select */
#define	LACDRC_ACD_MASK   0x0f /* Alternate Crystal Direction Control */
#define	LACDRC_ACD_SHIFT   0
#define	LPXCD_ADDR   0xfffffa25
#define	LPXCD   BYTE_REF(LPXCD_ADDR)
#define	LPXCD_PCD_MASK   0x3f /* Pixel Clock Divider */
#define	LPXCD_PCD_SHIFT   0
#define	LCKCON_ADDR   0xfffffa27
#define	LCKCON   BYTE_REF(LCKCON_ADDR)
#define	LCKCON_DWS_MASK   0x0f /* Display Wait-State */
#define	LCKCON_DWS_SHIFT   0
#define	LCKCON_DWIDTH   0x40 /* Display Memory Width */
#define	LCKCON_LCDON   0x80 /* Enable LCD Controller */
#define	LCKCON_DW_MASK   LCKCON_DWS_MASK
#define	LCKCON_DW_SHIFT   LCKCON_DWS_SHIFT
#define	LRRA_ADDR   0xfffffa29
#define	LRRA   BYTE_REF(LRRA_ADDR)
#define	LPOSR_ADDR   0xfffffa2d
#define	LPOSR   BYTE_REF(LPOSR_ADDR)
#define	LPOSR_POS_MASK   0x0f /* Pixel Offset Code */
#define	LPOSR_POS_SHIFT   0
#define	LFRCM_ADDR   0xfffffa31
#define	LFRCM   BYTE_REF(LFRCM_ADDR)
#define	LFRCM_YMOD_MASK   0x0f /* Vertical Modulation */
#define	LFRCM_YMOD_SHIFT   0
#define	LFRCM_XMOD_MASK   0xf0 /* Horizontal Modulation */
#define	LFRCM_XMOD_SHIFT   4
#define	LGPMR_ADDR   0xfffffa33
#define	LGPMR   BYTE_REF(LGPMR_ADDR)
#define	LGPMR_G1_MASK   0x0f
#define	LGPMR_G1_SHIFT   0
#define	LGPMR_G2_MASK   0xf0
#define	LGPMR_G2_SHIFT   4
#define	PWMR_ADDR   0xfffffa36
#define	PWMR   WORD_REF(PWMR_ADDR)
#define	PWMR_PW_MASK   0x00ff /* Pulse Width */
#define	PWMR_PW_SHIFT   0
#define	PWMR_CCPEN   0x0100 /* Contrast Control Enable */
#define	PWMR_SRC_MASK   0x0600 /* Input Clock Source */
#define	PWMR_SRC_LINE   0x0000 /* Line Pulse */
#define	PWMR_SRC_PIXEL   0x0200 /* Pixel Clock */
#define	PWMR_SRC_LCD   0x4000 /* LCD clock */
#define	RTCTIME_ADDR   0xfffffb00
#define	RTCTIME   LONG_REF(RTCTIME_ADDR)
#define	RTCTIME_SECONDS_MASK   0x0000003f /* Seconds */
#define	RTCTIME_SECONDS_SHIFT   0
#define	RTCTIME_MINUTES_MASK   0x003f0000 /* Minutes */
#define	RTCTIME_MINUTES_SHIFT   16
#define	RTCTIME_HOURS_MASK   0x1f000000 /* Hours */
#define	RTCTIME_HOURS_SHIFT   24
#define	RTCALRM_ADDR   0xfffffb04
#define	RTCALRM   LONG_REF(RTCALRM_ADDR)
#define	RTCALRM_SECONDS_MASK   0x0000003f /* Seconds */
#define	RTCALRM_SECONDS_SHIFT   0
#define	RTCALRM_MINUTES_MASK   0x003f0000 /* Minutes */
#define	RTCALRM_MINUTES_SHIFT   16
#define	RTCALRM_HOURS_MASK   0x1f000000 /* Hours */
#define	RTCALRM_HOURS_SHIFT   24
#define	WATCHDOG_ADDR   0xfffffb0a
#define	WATCHDOG   WORD_REF(WATCHDOG_ADDR)
#define	WATCHDOG_EN   0x0001 /* Watchdog Enabled */
#define	WATCHDOG_ISEL   0x0002 /* Select the watchdog interrupt */
#define	WATCHDOG_INTF   0x0080 /* Watchdog interrupt occurred */
#define	WATCHDOG_CNT_MASK   0x0300 /* Watchdog Counter */
#define	WATCHDOG_CNT_SHIFT   8
#define	RTCCTL_ADDR   0xfffffb0c
#define	RTCCTL   WORD_REF(RTCCTL_ADDR)
#define	RTCCTL_XTL   0x0020 /* Crystal Selection */
#define	RTCCTL_EN   0x0080 /* RTC Enable */
#define	RTCCTL_384   RTCCTL_XTL
#define	RTCCTL_ENABLE   RTCCTL_EN
#define	RTCISR_ADDR   0xfffffb0e
#define	RTCISR   WORD_REF(RTCISR_ADDR)
#define	RTCISR_SW   0x0001 /* Stopwatch timed out */
#define	RTCISR_MIN   0x0002 /* 1-minute interrupt has occurred */
#define	RTCISR_ALM   0x0004 /* Alarm interrupt has occurred */
#define	RTCISR_DAY   0x0008 /* 24-hour rollover interrupt has occurred */
#define	RTCISR_1HZ   0x0010 /* 1Hz interrupt has occurred */
#define	RTCISR_HR   0x0020 /* 1-hour interrupt has occurred */
#define	RTCISR_SAM0   0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
#define	RTCISR_SAM1   0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
#define	RTCISR_SAM2   0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
#define	RTCISR_SAM3   0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
#define	RTCISR_SAM4   0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
#define	RTCISR_SAM5   0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
#define	RTCISR_SAM6   0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
#define	RTCISR_SAM7   0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
#define	RTCIENR_ADDR   0xfffffb10
#define	RTCIENR   WORD_REF(RTCIENR_ADDR)
#define	RTCIENR_SW   0x0001 /* Stopwatch interrupt enable */
#define	RTCIENR_MIN   0x0002 /* 1-minute interrupt enable */
#define	RTCIENR_ALM   0x0004 /* Alarm interrupt enable */
#define	RTCIENR_DAY   0x0008 /* 24-hour rollover interrupt enable */
#define	RTCIENR_1HZ   0x0010 /* 1Hz interrupt enable */
#define	RTCIENR_HR   0x0020 /* 1-hour interrupt enable */
#define	RTCIENR_SAM0   0x0100 /* 4Hz / 4.6875Hz interrupt enable */
#define	RTCIENR_SAM1   0x0200 /* 8Hz / 9.3750Hz interrupt enable */
#define	RTCIENR_SAM2   0x0400 /* 16Hz / 18.7500Hz interrupt enable */
#define	RTCIENR_SAM3   0x0800 /* 32Hz / 37.5000Hz interrupt enable */
#define	RTCIENR_SAM4   0x1000 /* 64Hz / 75.0000Hz interrupt enable */
#define	RTCIENR_SAM5   0x2000 /* 128Hz / 150.0000Hz interrupt enable */
#define	RTCIENR_SAM6   0x4000 /* 256Hz / 300.0000Hz interrupt enable */
#define	RTCIENR_SAM7   0x8000 /* 512Hz / 600.0000Hz interrupt enable */
#define	STPWCH_ADDR   0xfffffb12
#define	STPWCH   WORD_REF(STPWCH)
#define	STPWCH_CNT_MASK   0x003f /* Stopwatch countdown value */
#define	SPTWCH_CNT_SHIFT   0
#define	DAYR_ADDR   0xfffffb1a
#define	DAYR   WORD_REF(DAYR_ADDR)
#define	DAYR_DAYS_MASK   0x1ff /* Day Setting */
#define	DAYR_DAYS_SHIFT   0
#define	DAYALARM_ADDR   0xfffffb1c
#define	DAYALARM   WORD_REF(DAYALARM_ADDR)
#define	DAYALARM_DAYSAL_MASK   0x01ff /* Day Setting of the Alarm */
#define	DAYALARM_DAYSAL_SHIFT   0
#define	DRAMMC_ADDR   0xfffffc00
#define	DRAMMC   WORD_REF(DRAMMC_ADDR)
#define	DRAMMC_ROW12_MASK   0xc000 /* Row address bit for MD12 */
#define	DRAMMC_ROW12_PA10   0x0000
#define	DRAMMC_ROW12_PA21   0x4000
#define	DRAMMC_ROW12_PA23   0x8000
#define	DRAMMC_ROW0_MASK   0x3000 /* Row address bit for MD0 */
#define	DRAMMC_ROW0_PA11   0x0000
#define	DRAMMC_ROW0_PA22   0x1000
#define	DRAMMC_ROW0_PA23   0x2000
#define	DRAMMC_ROW11   0x0800 /* Row address bit for MD11 PA20/PA22 */
#define	DRAMMC_ROW10   0x0400 /* Row address bit for MD10 PA19/PA21 */
#define	DRAMMC_ROW9   0x0200 /* Row address bit for MD9 PA9/PA19 */
#define	DRAMMC_ROW8   0x0100 /* Row address bit for MD8 PA10/PA20 */
#define	DRAMMC_COL10   0x0080 /* Col address bit for MD10 PA11/PA0 */
#define	DRAMMC_COL9   0x0040 /* Col address bit for MD9 PA10/PA0 */
#define	DRAMMC_COL8   0x0020 /* Col address bit for MD8 PA9/PA0 */
#define	DRAMMC_REF_MASK   0x001f /* Reresh Cycle */
#define	DRAMMC_REF_SHIFT   0
#define	DRAMC_ADDR   0xfffffc02
#define	DRAMC   WORD_REF(DRAMC_ADDR)
#define	DRAMC_DWE   0x0001 /* DRAM Write Enable */
#define	DRAMC_RST   0x0002 /* Reset Burst Refresh Enable */
#define	DRAMC_LPR   0x0004 /* Low-Power Refresh Enable */
#define	DRAMC_SLW   0x0008 /* Slow RAM */
#define	DRAMC_LSP   0x0010 /* Light Sleep */
#define	DRAMC_MSW   0x0020 /* Slow Multiplexing */
#define	DRAMC_WS_MASK   0x00c0 /* Wait-states */
#define	DRAMC_WS_SHIFT   6
#define	DRAMC_PGSZ_MASK   0x0300 /* Page Size for fast page mode */
#define	DRAMC_PGSZ_SHIFT   8
#define	DRAMC_PGSZ_256K   0x0000
#define	DRAMC_PGSZ_512K   0x0100
#define	DRAMC_PGSZ_1024K   0x0200
#define	DRAMC_PGSZ_2048K   0x0300
#define	DRAMC_EDO   0x0400 /* EDO DRAM */
#define	DRAMC_CLK   0x0800 /* Refresh Timer Clock source select */
#define	DRAMC_BC_MASK   0x3000 /* Page Access Clock Cycle (FP mode) */
#define	DRAMC_BC_SHIFT   12
#define	DRAMC_RM   0x4000 /* Refresh Mode */
#define	DRAMC_EN   0x8000 /* DRAM Controller enable */
#define	ICEMACR_ADDR   0xfffffd00
#define	ICEMACR   LONG_REF(ICEMACR_ADDR)
#define	ICEMAMR_ADDR   0xfffffd04
#define	ICEMAMR   LONG_REF(ICEMAMR_ADDR)
#define	ICEMCCR_ADDR   0xfffffd08
#define	ICEMCCR   WORD_REF(ICEMCCR_ADDR)
#define	ICEMCCR_PD   0x0001 /* Program/Data Cycle Selection */
#define	ICEMCCR_RW   0x0002 /* Read/Write Cycle Selection */
#define	ICEMCMR_ADDR   0xfffffd0a
#define	ICEMCMR   WORD_REF(ICEMCMR_ADDR)
#define	ICEMCMR_PDM   0x0001 /* Program/Data Cycle Mask */
#define	ICEMCMR_RWM   0x0002 /* Read/Write Cycle Mask */
#define	ICEMCR_ADDR   0xfffffd0c
#define	ICEMCR   WORD_REF(ICEMCR_ADDR)
#define	ICEMCR_CEN   0x0001 /* Compare Enable */
#define	ICEMCR_PBEN   0x0002 /* Program Break Enable */
#define	ICEMCR_SB   0x0004 /* Single Breakpoint */
#define	ICEMCR_HMDIS   0x0008 /* HardMap disable */
#define	ICEMCR_BBIEN   0x0010 /* Bus Break Interrupt Enable */
#define	ICEMSR_ADDR   0xfffffd0e
#define	ICEMSR   WORD_REF(ICEMSR_ADDR)
#define	ICEMSR_EMUEN   0x0001 /* Emulation Enable */
#define	ICEMSR_BRKIRQ   0x0002 /* A-Line Vector Fetch Detected */
#define	ICEMSR_BBIRQ   0x0004 /* Bus Break Interrupt Detected */
#define	ICEMSR_EMIRQ   0x0008 /* EMUIRQ Falling Edge Detected */

Macro Definition Documentation

#define BYTE_REF

(

addr

)

(*((volatile unsigned char*)addr))

Definition at line 16 of file MC68EZ328.h.

#define CSA   WORD_REF(CSA_ADDR)

Definition at line 77 of file MC68EZ328.h.

#define CSA_ADDR   0xfffff110

Definition at line 72 of file MC68EZ328.h.

#define CSA_BSW   0x0080 /* Data Bus Width */

Definition at line 87 of file MC68EZ328.h.

#define CSA_EN   0x0001 /* Chip-Select Enable */

Definition at line 82 of file MC68EZ328.h.

#define CSA_FLASH   0x0100 /* FLASH Memory Support */

Definition at line 88 of file MC68EZ328.h.

#define CSA_RO   0x8000 /* Read-Only */

Definition at line 89 of file MC68EZ328.h.

#define CSA_SIZ_MASK   0x000e /* Chip-Select Size */

Definition at line 83 of file MC68EZ328.h.

#define CSA_SIZ_SHIFT   1

Definition at line 84 of file MC68EZ328.h.

#define CSA_WS_MASK   0x0070 /* Wait State */

Definition at line 85 of file MC68EZ328.h.

#define CSA_WS_SHIFT   4

Definition at line 86 of file MC68EZ328.h.

#define CSB   WORD_REF(CSB_ADDR)

Definition at line 78 of file MC68EZ328.h.

#define CSB_ADDR   0xfffff112

Definition at line 73 of file MC68EZ328.h.

#define CSB_BSW   0x0080 /* Data Bus Width */

Definition at line 96 of file MC68EZ328.h.

#define CSB_EN   0x0001 /* Chip-Select Enable */

Definition at line 91 of file MC68EZ328.h.

#define CSB_FLASH   0x0100 /* FLASH Memory Support */

Definition at line 97 of file MC68EZ328.h.

#define CSB_RO   0x8000 /* Read-Only */

Definition at line 102 of file MC68EZ328.h.

#define CSB_ROP   0x2000 /* Readonly if protected */

Definition at line 100 of file MC68EZ328.h.

#define CSB_SIZ_MASK   0x000e /* Chip-Select Size */

Definition at line 92 of file MC68EZ328.h.

#define CSB_SIZ_SHIFT   1

Definition at line 93 of file MC68EZ328.h.

#define CSB_SOP   0x4000 /* Supervisor only if protected */

Definition at line 101 of file MC68EZ328.h.

#define CSB_UPSIZ_MASK   0x1800 /* Unprotected memory block size */

Definition at line 98 of file MC68EZ328.h.

#define CSB_UPSIZ_SHIFT   11

Definition at line 99 of file MC68EZ328.h.

#define CSB_WS_MASK   0x0070 /* Wait State */

Definition at line 94 of file MC68EZ328.h.

#define CSB_WS_SHIFT   4

Definition at line 95 of file MC68EZ328.h.

#define CSC   WORD_REF(CSC_ADDR)

Definition at line 79 of file MC68EZ328.h.

#define CSC_ADDR   0xfffff114

Definition at line 74 of file MC68EZ328.h.

#define CSC_BSW   0x0080 /* Data Bus Width */

Definition at line 109 of file MC68EZ328.h.

#define CSC_EN   0x0001 /* Chip-Select Enable */

Definition at line 104 of file MC68EZ328.h.

#define CSC_FLASH   0x0100 /* FLASH Memory Support */

Definition at line 110 of file MC68EZ328.h.

#define CSC_RO   0x8000 /* Read-Only */

Definition at line 115 of file MC68EZ328.h.

#define CSC_ROP   0x2000 /* Readonly if protected */

Definition at line 113 of file MC68EZ328.h.

#define CSC_SIZ_MASK   0x000e /* Chip-Select Size */

Definition at line 105 of file MC68EZ328.h.

#define CSC_SIZ_SHIFT   1

Definition at line 106 of file MC68EZ328.h.

#define CSC_SOP   0x4000 /* Supervisor only if protected */

Definition at line 114 of file MC68EZ328.h.

#define CSC_UPSIZ_MASK   0x1800 /* Unprotected memory block size */

Definition at line 111 of file MC68EZ328.h.

#define CSC_UPSIZ_SHIFT   11

Definition at line 112 of file MC68EZ328.h.

#define CSC_WS_MASK   0x0070 /* Wait State */

Definition at line 107 of file MC68EZ328.h.

#define CSC_WS_SHIFT   4

Definition at line 108 of file MC68EZ328.h.

#define CSD   WORD_REF(CSD_ADDR)

Definition at line 80 of file MC68EZ328.h.

#define CSD_ADDR   0xfffff116

Definition at line 75 of file MC68EZ328.h.

#define CSD_BSW   0x0080 /* Data Bus Width */

Definition at line 122 of file MC68EZ328.h.

#define CSD_COMB   0x0400 /* Combining */

Definition at line 125 of file MC68EZ328.h.

#define CSD_DRAM   0x0200 /* Dram Selection */

Definition at line 124 of file MC68EZ328.h.

#define CSD_EN   0x0001 /* Chip-Select Enable */

Definition at line 117 of file MC68EZ328.h.

#define CSD_FLASH   0x0100 /* FLASH Memory Support */

Definition at line 123 of file MC68EZ328.h.

#define CSD_RO   0x8000 /* Read-Only */

Definition at line 130 of file MC68EZ328.h.

#define CSD_ROP   0x2000 /* Readonly if protected */

Definition at line 128 of file MC68EZ328.h.

#define CSD_SIZ_MASK   0x000e /* Chip-Select Size */

Definition at line 118 of file MC68EZ328.h.

#define CSD_SIZ_SHIFT   1

Definition at line 119 of file MC68EZ328.h.

#define CSD_SOP   0x4000 /* Supervisor only if protected */

Definition at line 129 of file MC68EZ328.h.

#define CSD_UPSIZ_MASK   0x1800 /* Unprotected memory block size */

Definition at line 126 of file MC68EZ328.h.

#define CSD_UPSIZ_SHIFT   11

Definition at line 127 of file MC68EZ328.h.

#define CSD_WS_MASK   0x0070 /* Wait State */

Definition at line 120 of file MC68EZ328.h.

#define CSD_WS_SHIFT   4

Definition at line 121 of file MC68EZ328.h.

#define CSGBA   WORD_REF(CSGBA_ADDR)

Definition at line 64 of file MC68EZ328.h.

#define CSGBA_ADDR   0xfffff100

Definition at line 58 of file MC68EZ328.h.

#define CSGBB   WORD_REF(CSGBB_ADDR)

Definition at line 65 of file MC68EZ328.h.

#define CSGBB_ADDR   0xfffff102

Definition at line 59 of file MC68EZ328.h.

#define CSGBC   WORD_REF(CSGBC_ADDR)

Definition at line 66 of file MC68EZ328.h.

#define CSGBC_ADDR   0xfffff104

Definition at line 61 of file MC68EZ328.h.

#define CSGBD   WORD_REF(CSGBD_ADDR)

Definition at line 67 of file MC68EZ328.h.

#define CSGBD_ADDR   0xfffff106

Definition at line 62 of file MC68EZ328.h.

#define DAYALARM   WORD_REF(DAYALARM_ADDR)

Definition at line 1131 of file MC68EZ328.h.

#define DAYALARM_ADDR   0xfffffb1c

Definition at line 1130 of file MC68EZ328.h.

#define DAYALARM_DAYSAL_MASK   0x01ff /* Day Setting of the Alarm */

Definition at line 1133 of file MC68EZ328.h.

#define DAYALARM_DAYSAL_SHIFT   0

Definition at line 1134 of file MC68EZ328.h.

#define DAYR   WORD_REF(DAYR_ADDR)

Definition at line 1122 of file MC68EZ328.h.

#define DAYR_ADDR   0xfffffb1a

Definition at line 1121 of file MC68EZ328.h.

#define DAYR_DAYS_MASK   0x1ff /* Day Setting */

Definition at line 1124 of file MC68EZ328.h.

#define DAYR_DAYS_SHIFT   0

Definition at line 1125 of file MC68EZ328.h.

#define DRAMC   WORD_REF(DRAMC_ADDR)

Definition at line 1170 of file MC68EZ328.h.

#define DRAMC_ADDR   0xfffffc02

Definition at line 1169 of file MC68EZ328.h.

#define DRAMC_BC_MASK   0x3000 /* Page Access Clock Cycle (FP mode) */

Definition at line 1188 of file MC68EZ328.h.

#define DRAMC_BC_SHIFT   12

Definition at line 1189 of file MC68EZ328.h.

#define DRAMC_CLK   0x0800 /* Refresh Timer Clock source select */

Definition at line 1187 of file MC68EZ328.h.

#define DRAMC_DWE   0x0001 /* DRAM Write Enable */

Definition at line 1172 of file MC68EZ328.h.

#define DRAMC_EDO   0x0400 /* EDO DRAM */

Definition at line 1186 of file MC68EZ328.h.

#define DRAMC_EN   0x8000 /* DRAM Controller enable */

Definition at line 1191 of file MC68EZ328.h.

#define DRAMC_LPR   0x0004 /* Low-Power Refresh Enable */

Definition at line 1174 of file MC68EZ328.h.

#define DRAMC_LSP   0x0010 /* Light Sleep */

Definition at line 1176 of file MC68EZ328.h.

#define DRAMC_MSW   0x0020 /* Slow Multiplexing */

Definition at line 1177 of file MC68EZ328.h.

#define DRAMC_PGSZ_1024K   0x0200

Definition at line 1184 of file MC68EZ328.h.

#define DRAMC_PGSZ_2048K   0x0300

Definition at line 1185 of file MC68EZ328.h.

#define DRAMC_PGSZ_256K   0x0000

Definition at line 1182 of file MC68EZ328.h.

#define DRAMC_PGSZ_512K   0x0100

Definition at line 1183 of file MC68EZ328.h.

#define DRAMC_PGSZ_MASK   0x0300 /* Page Size for fast page mode */

Definition at line 1180 of file MC68EZ328.h.

#define DRAMC_PGSZ_SHIFT   8

Definition at line 1181 of file MC68EZ328.h.

#define DRAMC_RM   0x4000 /* Refresh Mode */

Definition at line 1190 of file MC68EZ328.h.

#define DRAMC_RST   0x0002 /* Reset Burst Refresh Enable */

Definition at line 1173 of file MC68EZ328.h.

#define DRAMC_SLW   0x0008 /* Slow RAM */

Definition at line 1175 of file MC68EZ328.h.

#define DRAMC_WS_MASK   0x00c0 /* Wait-states */

Definition at line 1178 of file MC68EZ328.h.

#define DRAMC_WS_SHIFT   6

Definition at line 1179 of file MC68EZ328.h.

#define DRAMMC   WORD_REF(DRAMMC_ADDR)

Definition at line 1146 of file MC68EZ328.h.

#define DRAMMC_ADDR   0xfffffc00

Definition at line 1145 of file MC68EZ328.h.

#define DRAMMC_COL10   0x0080 /* Col address bit for MD10 PA11/PA0 */

Definition at line 1160 of file MC68EZ328.h.

#define DRAMMC_COL8   0x0020 /* Col address bit for MD8 PA9/PA0 */

Definition at line 1162 of file MC68EZ328.h.

#define DRAMMC_COL9   0x0040 /* Col address bit for MD9 PA10/PA0 */

Definition at line 1161 of file MC68EZ328.h.

#define DRAMMC_REF_MASK   0x001f /* Reresh Cycle */

Definition at line 1163 of file MC68EZ328.h.

#define DRAMMC_REF_SHIFT   0

Definition at line 1164 of file MC68EZ328.h.

#define DRAMMC_ROW0_MASK   0x3000 /* Row address bit for MD0 */

Definition at line 1152 of file MC68EZ328.h.

#define DRAMMC_ROW0_PA11   0x0000

Definition at line 1153 of file MC68EZ328.h.

#define DRAMMC_ROW0_PA22   0x1000

Definition at line 1154 of file MC68EZ328.h.

#define DRAMMC_ROW0_PA23   0x2000

Definition at line 1155 of file MC68EZ328.h.

#define DRAMMC_ROW10   0x0400 /* Row address bit for MD10 PA19/PA21 */

Definition at line 1157 of file MC68EZ328.h.

#define DRAMMC_ROW11   0x0800 /* Row address bit for MD11 PA20/PA22 */

Definition at line 1156 of file MC68EZ328.h.

#define DRAMMC_ROW12_MASK   0xc000 /* Row address bit for MD12 */

Definition at line 1148 of file MC68EZ328.h.

#define DRAMMC_ROW12_PA10   0x0000

Definition at line 1149 of file MC68EZ328.h.

#define DRAMMC_ROW12_PA21   0x4000

Definition at line 1150 of file MC68EZ328.h.

#define DRAMMC_ROW12_PA23   0x8000

Definition at line 1151 of file MC68EZ328.h.

#define DRAMMC_ROW8   0x0100 /* Row address bit for MD8 PA10/PA20 */

Definition at line 1159 of file MC68EZ328.h.

#define DRAMMC_ROW9   0x0200 /* Row address bit for MD9 PA9/PA19 */

Definition at line 1158 of file MC68EZ328.h.

#define EMIQ_IRQ_NUM   23 /* Emulator Interrupt */

Definition at line 245 of file MC68EZ328.h.

#define EMUCS   WORD_REF(EMUCS_ADDR)

Definition at line 136 of file MC68EZ328.h.

#define EMUCS_ADDR   0xfffff118

Definition at line 135 of file MC68EZ328.h.

#define EMUCS_WS_MASK   0x0070

Definition at line 138 of file MC68EZ328.h.

#define EMUCS_WS_SHIFT   4

Definition at line 139 of file MC68EZ328.h.

#define GET_FIELD	(		reg,
			field
	)		(((reg) & field##_MASK) >> field##_SHIFT)

Definition at line 21 of file MC68EZ328.h.

#define ICEMACR   LONG_REF(ICEMACR_ADDR)

Definition at line 1204 of file MC68EZ328.h.

#define ICEMACR_ADDR   0xfffffd00

Definition at line 1203 of file MC68EZ328.h.

#define ICEMAMR   LONG_REF(ICEMAMR_ADDR)

Definition at line 1210 of file MC68EZ328.h.

#define ICEMAMR_ADDR   0xfffffd04

Definition at line 1209 of file MC68EZ328.h.

#define ICEMCCR   WORD_REF(ICEMCCR_ADDR)

Definition at line 1216 of file MC68EZ328.h.

#define ICEMCCR_ADDR   0xfffffd08

Definition at line 1215 of file MC68EZ328.h.

#define ICEMCCR_PD   0x0001 /* Program/Data Cycle Selection */

Definition at line 1218 of file MC68EZ328.h.

#define ICEMCCR_RW   0x0002 /* Read/Write Cycle Selection */

Definition at line 1219 of file MC68EZ328.h.

#define ICEMCMR   WORD_REF(ICEMCMR_ADDR)

Definition at line 1225 of file MC68EZ328.h.

#define ICEMCMR_ADDR   0xfffffd0a

Definition at line 1224 of file MC68EZ328.h.

#define ICEMCMR_PDM   0x0001 /* Program/Data Cycle Mask */

Definition at line 1227 of file MC68EZ328.h.

#define ICEMCMR_RWM   0x0002 /* Read/Write Cycle Mask */

Definition at line 1228 of file MC68EZ328.h.

#define ICEMCR   WORD_REF(ICEMCR_ADDR)

Definition at line 1234 of file MC68EZ328.h.

#define ICEMCR_ADDR   0xfffffd0c

Definition at line 1233 of file MC68EZ328.h.

#define ICEMCR_BBIEN   0x0010 /* Bus Break Interrupt Enable */

Definition at line 1240 of file MC68EZ328.h.

#define ICEMCR_CEN   0x0001 /* Compare Enable */

Definition at line 1236 of file MC68EZ328.h.

#define ICEMCR_HMDIS   0x0008 /* HardMap disable */

Definition at line 1239 of file MC68EZ328.h.

#define ICEMCR_PBEN   0x0002 /* Program Break Enable */

Definition at line 1237 of file MC68EZ328.h.

#define ICEMCR_SB   0x0004 /* Single Breakpoint */

Definition at line 1238 of file MC68EZ328.h.

#define ICEMSR   WORD_REF(ICEMSR_ADDR)

Definition at line 1246 of file MC68EZ328.h.

#define ICEMSR_ADDR   0xfffffd0e

Definition at line 1245 of file MC68EZ328.h.

#define ICEMSR_BBIRQ   0x0004 /* Bus Break Interrupt Detected */

Definition at line 1250 of file MC68EZ328.h.

#define ICEMSR_BRKIRQ   0x0002 /* A-Line Vector Fetch Detected */

Definition at line 1249 of file MC68EZ328.h.

#define ICEMSR_EMIRQ   0x0008 /* EMUIRQ Falling Edge Detected */

Definition at line 1251 of file MC68EZ328.h.

#define ICEMSR_EMUEN   0x0001 /* Emulation Enable */

Definition at line 1248 of file MC68EZ328.h.

#define ICR   WORD_REF(ICR_ADDR)

Definition at line 206 of file MC68EZ328.h.

#define ICR_ADDR   0xfffff302

Definition at line 205 of file MC68EZ328.h.

#define ICR_ET1   0x0800 /* Edge Trigger Select for IRQ1 */

Definition at line 212 of file MC68EZ328.h.

#define ICR_ET2   0x0400 /* Edge Trigger Select for IRQ2 */

Definition at line 211 of file MC68EZ328.h.

#define ICR_ET3   0x0200 /* Edge Trigger Select for IRQ3 */

Definition at line 210 of file MC68EZ328.h.

#define ICR_ET6   0x0100 /* Edge Trigger Select for IRQ6 */

Definition at line 209 of file MC68EZ328.h.

#define ICR_POL1   0x8000 /* Polarity Control for IRQ1 */

Definition at line 216 of file MC68EZ328.h.

#define ICR_POL2   0x4000 /* Polarity Control for IRQ2 */

Definition at line 215 of file MC68EZ328.h.

#define ICR_POL3   0x2000 /* Polarity Control for IRQ3 */

Definition at line 214 of file MC68EZ328.h.

#define ICR_POL5   0x0080 /* Polarity Control for IRQ5 */

Definition at line 208 of file MC68EZ328.h.

#define ICR_POL6   0x1000 /* Polarity Control for IRQ6 */

Definition at line 213 of file MC68EZ328.h.

#define IMR   LONG_REF(IMR_ADDR)

Definition at line 222 of file MC68EZ328.h.

#define IMR_ADDR   0xfffff304

Definition at line 221 of file MC68EZ328.h.

#define IMR_MEMIQ   (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */

Definition at line 271 of file MC68EZ328.h.

#define IMR_MINT0   (1 << INT0_IRQ_NUM) /* Mask External INT0 */

Definition at line 261 of file MC68EZ328.h.

#define IMR_MINT1   (1 << INT1_IRQ_NUM) /* Mask External INT1 */

Definition at line 262 of file MC68EZ328.h.

#define IMR_MINT2   (1 << INT2_IRQ_NUM) /* Mask External INT2 */

Definition at line 263 of file MC68EZ328.h.

#define IMR_MINT3   (1 << INT3_IRQ_NUM) /* Mask External INT3 */

Definition at line 264 of file MC68EZ328.h.

#define IMR_MIRQ1   (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */

Definition at line 265 of file MC68EZ328.h.

#define IMR_MIRQ2   (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */

Definition at line 266 of file MC68EZ328.h.

#define IMR_MIRQ3   (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */

Definition at line 267 of file MC68EZ328.h.

#define IMR_MIRQ5   (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */

Definition at line 269 of file MC68EZ328.h.

#define IMR_MIRQ6   (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */

Definition at line 268 of file MC68EZ328.h.

#define IMR_MKB   (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */

Definition at line 259 of file MC68EZ328.h.

#define IMR_MPWM   (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */

Definition at line 260 of file MC68EZ328.h.

#define IMR_MRTC   (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */

Definition at line 258 of file MC68EZ328.h.

#define IMR_MSAM   (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */

Definition at line 270 of file MC68EZ328.h.

#define IMR_MSPI   (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */

Definition at line 254 of file MC68EZ328.h.

#define IMR_MSPIM   IMR_MSPI

Definition at line 274 of file MC68EZ328.h.

#define IMR_MTMR   (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */

Definition at line 255 of file MC68EZ328.h.

#define IMR_MTMR1   IMR_MTMR

Definition at line 275 of file MC68EZ328.h.

#define IMR_MUART   (1 << UART_IRQ_NUM) /* Mask UART interrupt */

Definition at line 256 of file MC68EZ328.h.

#define IMR_MWDT   (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */

Definition at line 257 of file MC68EZ328.h.

#define INT0_IRQ_NUM   8 /* External INT0 */

Definition at line 235 of file MC68EZ328.h.

#define INT1_IRQ_NUM   9 /* External INT1 */

Definition at line 236 of file MC68EZ328.h.

#define INT2_IRQ_NUM   10 /* External INT2 */

Definition at line 237 of file MC68EZ328.h.

#define INT3_IRQ_NUM   11 /* External INT3 */

Definition at line 238 of file MC68EZ328.h.

#define IPR   LONG_REF(IPR_ADDR)

Definition at line 310 of file MC68EZ328.h.

#define IPR_ADDR   0xfffff30c

Definition at line 309 of file MC68EZ328.h.

#define IPR_EMIQ   (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */

Definition at line 329 of file MC68EZ328.h.

#define IPR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */

Definition at line 319 of file MC68EZ328.h.

#define IPR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */

Definition at line 320 of file MC68EZ328.h.

#define IPR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */

Definition at line 321 of file MC68EZ328.h.

#define IPR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */

Definition at line 322 of file MC68EZ328.h.

#define IPR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */

Definition at line 323 of file MC68EZ328.h.

#define IPR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */

Definition at line 324 of file MC68EZ328.h.

#define IPR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */

Definition at line 325 of file MC68EZ328.h.

#define IPR_IRQ5   (1 << IRQ5_IRQ_NUM) /* IRQ5 */

Definition at line 327 of file MC68EZ328.h.

#define IPR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */

Definition at line 326 of file MC68EZ328.h.

#define IPR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */

Definition at line 317 of file MC68EZ328.h.

#define IPR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */

Definition at line 318 of file MC68EZ328.h.

#define IPR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */

Definition at line 316 of file MC68EZ328.h.

#define IPR_SAM   (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */

Definition at line 328 of file MC68EZ328.h.

#define IPR_SPI   (1 << SPI_IRQ_NUM) /* SPI interrupt */

Definition at line 312 of file MC68EZ328.h.

#define IPR_SPIM   IPR_SPI

Definition at line 332 of file MC68EZ328.h.

#define IPR_TMR   (1 << TMR_IRQ_NUM) /* Timer interrupt */

Definition at line 313 of file MC68EZ328.h.

#define IPR_TMR1   IPR_TMR

Definition at line 333 of file MC68EZ328.h.

#define IPR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */

Definition at line 314 of file MC68EZ328.h.

#define IPR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */

Definition at line 315 of file MC68EZ328.h.

#define IRQ1_IRQ_NUM   16 /* IRQ1 */

Definition at line 239 of file MC68EZ328.h.

#define IRQ2_IRQ_NUM   17 /* IRQ2 */

Definition at line 240 of file MC68EZ328.h.

#define IRQ3_IRQ_NUM   18 /* IRQ3 */

Definition at line 241 of file MC68EZ328.h.

#define IRQ5_IRQ_NUM   20 /* IRQ5 */

Definition at line 243 of file MC68EZ328.h.

#define IRQ6_IRQ_NUM   19 /* IRQ6 */

Definition at line 242 of file MC68EZ328.h.

#define ISR   LONG_REF(ISR_ADDR)

Definition at line 281 of file MC68EZ328.h.

#define ISR_ADDR   0xfffff30c

Definition at line 280 of file MC68EZ328.h.

#define ISR_EMIQ   (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */

Definition at line 300 of file MC68EZ328.h.

#define ISR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */

Definition at line 290 of file MC68EZ328.h.

#define ISR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */

Definition at line 291 of file MC68EZ328.h.

#define ISR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */

Definition at line 292 of file MC68EZ328.h.

#define ISR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */

Definition at line 293 of file MC68EZ328.h.

#define ISR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */

Definition at line 294 of file MC68EZ328.h.

#define ISR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */

Definition at line 295 of file MC68EZ328.h.

#define ISR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */

Definition at line 296 of file MC68EZ328.h.

#define ISR_IRQ5   (1 << IRQ5_IRQ_NUM) /* IRQ5 */

Definition at line 298 of file MC68EZ328.h.

#define ISR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */

Definition at line 297 of file MC68EZ328.h.

#define ISR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */

Definition at line 288 of file MC68EZ328.h.

#define ISR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */

Definition at line 289 of file MC68EZ328.h.

#define ISR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */

Definition at line 287 of file MC68EZ328.h.

#define ISR_SAM   (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */

Definition at line 299 of file MC68EZ328.h.

#define ISR_SPI   (1 << SPI_IRQ_NUM) /* SPI interrupt */

Definition at line 283 of file MC68EZ328.h.

#define ISR_SPIM   ISR_SPI

Definition at line 303 of file MC68EZ328.h.

#define ISR_TMR   (1 << TMR_IRQ_NUM) /* Timer interrupt */

Definition at line 284 of file MC68EZ328.h.

#define ISR_TMR1   ISR_TMR

Definition at line 304 of file MC68EZ328.h.

#define ISR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */

Definition at line 285 of file MC68EZ328.h.

#define ISR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */

Definition at line 286 of file MC68EZ328.h.

#define IVR   BYTE_REF(IVR_ADDR)

Definition at line 198 of file MC68EZ328.h.

#define IVR_ADDR   0xfffff300

Definition at line 197 of file MC68EZ328.h.

#define IVR_VECTOR_MASK   0xF8

Definition at line 200 of file MC68EZ328.h.

#define KB_IRQ_NUM   6 /* Keyboard Interrupt */

Definition at line 233 of file MC68EZ328.h.

#define LACDRC   BYTE_REF(LACDRC_ADDR)

Definition at line 929 of file MC68EZ328.h.

#define LACDRC_ACD_MASK   0x0f /* Alternate Crystal Direction Control */

Definition at line 932 of file MC68EZ328.h.

#define LACDRC_ACD_SHIFT   0

Definition at line 933 of file MC68EZ328.h.

#define LACDRC_ACDSLT   0x80 /* Signal Source Select */

Definition at line 931 of file MC68EZ328.h.

#define LACDRC_ADDR   0xfffffa23

Definition at line 928 of file MC68EZ328.h.

#define LBLKC   BYTE_REF(LBLKC_ADDR)

Definition at line 893 of file MC68EZ328.h.

#define LBLKC_ADDR   0xfffffa1f

Definition at line 892 of file MC68EZ328.h.

#define LBLKC_BD_MASK   0x7f /* Blink Divisor */

Definition at line 895 of file MC68EZ328.h.

#define LBLKC_BD_SHIFT   0

Definition at line 896 of file MC68EZ328.h.

#define LBLKC_BKEN   0x80 /* Blink Enabled */

Definition at line 897 of file MC68EZ328.h.

#define LCKCON   BYTE_REF(LCKCON_ADDR)

Definition at line 948 of file MC68EZ328.h.

#define LCKCON_ADDR   0xfffffa27

Definition at line 947 of file MC68EZ328.h.

#define LCKCON_DW_MASK   LCKCON_DWS_MASK

Definition at line 956 of file MC68EZ328.h.

#define LCKCON_DW_SHIFT   LCKCON_DWS_SHIFT

Definition at line 957 of file MC68EZ328.h.

#define LCKCON_DWIDTH   0x40 /* Display Memory Width */

Definition at line 952 of file MC68EZ328.h.

#define LCKCON_DWS_MASK   0x0f /* Display Wait-State */

Definition at line 950 of file MC68EZ328.h.

#define LCKCON_DWS_SHIFT   0

Definition at line 951 of file MC68EZ328.h.

#define LCKCON_LCDON   0x80 /* Enable LCD Controller */

Definition at line 953 of file MC68EZ328.h.

#define LCWCH   WORD_REF(LCWCH_ADDR)

Definition at line 882 of file MC68EZ328.h.

#define LCWCH_ADDR   0xfffffa1c

Definition at line 881 of file MC68EZ328.h.

#define LCWCH_CH_MASK   0x001f /* Cursor Height */

Definition at line 884 of file MC68EZ328.h.

#define LCWCH_CH_SHIFT   0

Definition at line 885 of file MC68EZ328.h.

#define LCWCH_CW_MASK   0x1f00 /* Cursor Width */

Definition at line 886 of file MC68EZ328.h.

#define LCWCH_CW_SHIFT   8

Definition at line 887 of file MC68EZ328.h.

#define LCXP   WORD_REF(LCXP_ADDR)

Definition at line 861 of file MC68EZ328.h.

#define LCXP_ADDR   0xfffffa18

Definition at line 860 of file MC68EZ328.h.

#define LCXP_CC_BLACK   0x4000

Definition at line 865 of file MC68EZ328.h.

#define LCXP_CC_MASK   0xc000 /* Cursor Control */

Definition at line 863 of file MC68EZ328.h.

#define LCXP_CC_REVERSED   0x8000

Definition at line 866 of file MC68EZ328.h.

#define LCXP_CC_TRAMSPARENT   0x0000

Definition at line 864 of file MC68EZ328.h.

#define LCXP_CC_WHITE   0xc000

Definition at line 867 of file MC68EZ328.h.

#define LCXP_CXP_MASK   0x02ff /* Cursor X position */

Definition at line 868 of file MC68EZ328.h.

#define LCYP   WORD_REF(LCYP_ADDR)

Definition at line 874 of file MC68EZ328.h.

#define LCYP_ADDR   0xfffffa1a

Definition at line 873 of file MC68EZ328.h.

#define LCYP_CYP_MASK   0x01ff /* Cursor Y Position */

Definition at line 876 of file MC68EZ328.h.

#define LFRCM   BYTE_REF(LFRCM_ADDR)

Definition at line 978 of file MC68EZ328.h.

#define LFRCM_ADDR   0xfffffa31

Definition at line 977 of file MC68EZ328.h.

#define LFRCM_XMOD_MASK   0xf0 /* Horizontal Modulation */

Definition at line 982 of file MC68EZ328.h.

#define LFRCM_XMOD_SHIFT   4

Definition at line 983 of file MC68EZ328.h.

#define LFRCM_YMOD_MASK   0x0f /* Vertical Modulation */

Definition at line 980 of file MC68EZ328.h.

#define LFRCM_YMOD_SHIFT   0

Definition at line 981 of file MC68EZ328.h.

#define LGPMR   BYTE_REF(LGPMR_ADDR)

Definition at line 989 of file MC68EZ328.h.

#define LGPMR_ADDR   0xfffffa33

Definition at line 988 of file MC68EZ328.h.

#define LGPMR_G1_MASK   0x0f

Definition at line 991 of file MC68EZ328.h.

#define LGPMR_G1_SHIFT   0

Definition at line 992 of file MC68EZ328.h.

#define LGPMR_G2_MASK   0xf0

Definition at line 993 of file MC68EZ328.h.

#define LGPMR_G2_SHIFT   4

Definition at line 994 of file MC68EZ328.h.

#define LONG_REF

(

addr

)

(*((volatile unsigned long*)addr))

Definition at line 18 of file MC68EZ328.h.

#define LPICF   BYTE_REF(LPICF_ADDR)

Definition at line 903 of file MC68EZ328.h.

#define LPICF_ADDR   0xfffffa20

Definition at line 902 of file MC68EZ328.h.

#define LPICF_GS_BW   0x00

Definition at line 906 of file MC68EZ328.h.

#define LPICF_GS_GRAY_16   0x02

Definition at line 908 of file MC68EZ328.h.

#define LPICF_GS_GRAY_4   0x01

Definition at line 907 of file MC68EZ328.h.

#define LPICF_GS_MASK   0x03 /* Gray-Scale Mode */

Definition at line 905 of file MC68EZ328.h.

#define LPICF_PBSIZ_1   0x00

Definition at line 910 of file MC68EZ328.h.

#define LPICF_PBSIZ_2   0x04

Definition at line 911 of file MC68EZ328.h.

#define LPICF_PBSIZ_4   0x08

Definition at line 912 of file MC68EZ328.h.

#define LPICF_PBSIZ_MASK   0x0c /* Panel Bus Width */

Definition at line 909 of file MC68EZ328.h.

#define LPOLCF   BYTE_REF(LPOLCF_ADDR)

Definition at line 918 of file MC68EZ328.h.

#define LPOLCF_ADDR   0xfffffa21

Definition at line 917 of file MC68EZ328.h.

#define LPOLCF_FLMPOL   0x04 /* Frame Marker Polarity */

Definition at line 922 of file MC68EZ328.h.

#define LPOLCF_LCKPOL   0x08 /* LCD Shift Lock Polarity */

Definition at line 923 of file MC68EZ328.h.

#define LPOLCF_LPPOL   0x02 /* Line Pulse Polarity */

Definition at line 921 of file MC68EZ328.h.

#define LPOLCF_PIXPOL   0x01 /* Pixel Polarity */

Definition at line 920 of file MC68EZ328.h.

#define LPOSR   BYTE_REF(LPOSR_ADDR)

Definition at line 969 of file MC68EZ328.h.

#define LPOSR_ADDR   0xfffffa2d

Definition at line 968 of file MC68EZ328.h.

#define LPOSR_POS_MASK   0x0f /* Pixel Offset Code */

Definition at line 971 of file MC68EZ328.h.

#define LPOSR_POS_SHIFT   0

Definition at line 972 of file MC68EZ328.h.

#define LPXCD   BYTE_REF(LPXCD_ADDR)

Definition at line 939 of file MC68EZ328.h.

#define LPXCD_ADDR   0xfffffa25

Definition at line 938 of file MC68EZ328.h.

#define LPXCD_PCD_MASK   0x3f /* Pixel Clock Divider */

Definition at line 941 of file MC68EZ328.h.

#define LPXCD_PCD_SHIFT   0

Definition at line 942 of file MC68EZ328.h.

#define LRRA   BYTE_REF(LRRA_ADDR)

Definition at line 963 of file MC68EZ328.h.

#define LRRA_ADDR   0xfffffa29

Definition at line 962 of file MC68EZ328.h.

#define LSSA   LONG_REF(LSSA_ADDR)

Definition at line 831 of file MC68EZ328.h.

#define LSSA_ADDR   0xfffffa00

Definition at line 830 of file MC68EZ328.h.

#define LSSA_SSA_MASK   0x1ffffffe /* Bits 0 and 29-31 are reserved */

Definition at line 833 of file MC68EZ328.h.

#define LVPW   BYTE_REF(LVPW_ADDR)

Definition at line 839 of file MC68EZ328.h.

#define LVPW_ADDR   0xfffffa05

Definition at line 838 of file MC68EZ328.h.

#define LXMAX   WORD_REF(LXMAX_ADDR)

Definition at line 845 of file MC68EZ328.h.

#define LXMAX_ADDR   0xfffffa08

Definition at line 844 of file MC68EZ328.h.

#define LXMAX_XM_MASK   0x02f0 /* Bits 0-3 and 10-15 are reserved */

Definition at line 847 of file MC68EZ328.h.

#define LYMAX   WORD_REF(LYMAX_ADDR)

Definition at line 853 of file MC68EZ328.h.

#define LYMAX_ADDR   0xfffffa0a

Definition at line 852 of file MC68EZ328.h.

#define LYMAX_YM_MASK   0x01ff /* Bits 9-15 are reserved */

Definition at line 855 of file MC68EZ328.h.

#define MRR   LONG_REF(MRR_ADDR)

Definition at line 47 of file MC68EZ328.h.

#define MRR_ADDR   0xfffff004

Definition at line 46 of file MC68EZ328.h.

#define NIPR   WORD_REF(NIPR_ADDR)

Definition at line 787 of file MC68EZ328.h.

#define NIPR_ADDR   0xfffff90a

Definition at line 786 of file MC68EZ328.h.

#define NIPR_PRE_SEL   0x8000 /* Non-integer prescaler select */

Definition at line 793 of file MC68EZ328.h.

#define NIPR_SELECT_MASK   0x0700 /* Tap Selection */

Definition at line 791 of file MC68EZ328.h.

#define NIPR_SELECT_SHIFT   8

Definition at line 792 of file MC68EZ328.h.

#define NIPR_STEP_VALUE_MASK   0x00ff /* NI prescaler step value */

Definition at line 789 of file MC68EZ328.h.

#define NIPR_STEP_VALUE_SHIFT   0

Definition at line 790 of file MC68EZ328.h.

#define PA

(

x

)

(1 << (x))

Definition at line 352 of file MC68EZ328.h.

#define PADATA   BYTE_REF(PADATA_ADDR)

Definition at line 349 of file MC68EZ328.h.

#define PADATA_ADDR   0xfffff401 /* Port A data register */

Definition at line 345 of file MC68EZ328.h.

#define PADIR   BYTE_REF(PADIR_ADDR)

Definition at line 348 of file MC68EZ328.h.

#define PADIR_ADDR   0xfffff400 /* Port A direction reg */

Definition at line 344 of file MC68EZ328.h.

#define PAPUEN   BYTE_REF(PAPUEN_ADDR)

Definition at line 350 of file MC68EZ328.h.

#define PAPUEN_ADDR   0xfffff402 /* Port A Pull-Up enable reg */

Definition at line 346 of file MC68EZ328.h.

#define PB

(

x

)

(1 << (x))

Definition at line 367 of file MC68EZ328.h.

#define PB_CSB0   0x01 /* Use CSB0 as PB[0] */

Definition at line 369 of file MC68EZ328.h.

#define PB_CSB1   0x02 /* Use CSB1 as PB[1] */

Definition at line 370 of file MC68EZ328.h.

#define PB_CSC0_RAS0   0x04 /* Use CSC0/RAS0 as PB[2] */

Definition at line 371 of file MC68EZ328.h.

#define PB_CSC1_RAS1   0x08 /* Use CSC1/RAS1 as PB[3] */

Definition at line 372 of file MC68EZ328.h.

#define PB_CSD0_CAS0   0x10 /* Use CSD0/CAS0 as PB[4] */

Definition at line 373 of file MC68EZ328.h.

#define PB_CSD1_CAS1   0x20 /* Use CSD1/CAS1 as PB[5] */

Definition at line 374 of file MC68EZ328.h.

#define PB_PWMO   0x80 /* Use PWMO as PB[7] */

Definition at line 376 of file MC68EZ328.h.

#define PB_TIN_TOUT   0x40 /* Use TIN/TOUT as PB[6] */

Definition at line 375 of file MC68EZ328.h.

#define PBDATA   BYTE_REF(PBDATA_ADDR)

Definition at line 363 of file MC68EZ328.h.

#define PBDATA_ADDR   0xfffff409 /* Port B data register */

Definition at line 358 of file MC68EZ328.h.

#define PBDIR   BYTE_REF(PBDIR_ADDR)

Definition at line 362 of file MC68EZ328.h.

#define PBDIR_ADDR   0xfffff408 /* Port B direction reg */

Definition at line 357 of file MC68EZ328.h.

#define PBPUEN   BYTE_REF(PBPUEN_ADDR)

Definition at line 364 of file MC68EZ328.h.

#define PBPUEN_ADDR   0xfffff40a /* Port B Pull-Up enable reg */

Definition at line 359 of file MC68EZ328.h.

#define PBSEL   BYTE_REF(PBSEL_ADDR)

Definition at line 365 of file MC68EZ328.h.

#define PBSEL_ADDR   0xfffff40b /* Port B Select Register */

Definition at line 360 of file MC68EZ328.h.

#define PC

(

x

)

(1 << (x))

Definition at line 391 of file MC68EZ328.h.

#define PC_LACD   0x80 /* Use LACD as PC[7] */

Definition at line 400 of file MC68EZ328.h.

#define PC_LCLK   0x40 /* Use LCLK as PC[6] */

Definition at line 399 of file MC68EZ328.h.

#define PC_LD0   0x01 /* Use LD0 as PC[0] */

Definition at line 393 of file MC68EZ328.h.

#define PC_LD1   0x02 /* Use LD1 as PC[1] */

Definition at line 394 of file MC68EZ328.h.

#define PC_LD2   0x04 /* Use LD2 as PC[2] */

Definition at line 395 of file MC68EZ328.h.

#define PC_LD3   0x08 /* Use LD3 as PC[3] */

Definition at line 396 of file MC68EZ328.h.

#define PC_LFLM   0x10 /* Use LFLM as PC[4] */

Definition at line 397 of file MC68EZ328.h.

#define PC_LLP   0x20 /* Use LLP as PC[5] */

Definition at line 398 of file MC68EZ328.h.

#define PCDATA   BYTE_REF(PCDATA_ADDR)

Definition at line 387 of file MC68EZ328.h.

#define PCDATA_ADDR   0xfffff411 /* Port C data register */

Definition at line 382 of file MC68EZ328.h.

#define PCDIR   BYTE_REF(PCDIR_ADDR)

Definition at line 386 of file MC68EZ328.h.

#define PCDIR_ADDR   0xfffff410 /* Port C direction reg */

Definition at line 381 of file MC68EZ328.h.

#define PCPDEN   BYTE_REF(PCPDEN_ADDR)

Definition at line 388 of file MC68EZ328.h.

#define PCPDEN_ADDR   0xfffff412 /* Port C Pull-Down enb. reg */

Definition at line 383 of file MC68EZ328.h.

#define PCSEL   BYTE_REF(PCSEL_ADDR)

Definition at line 389 of file MC68EZ328.h.

#define PCSEL_ADDR   0xfffff413 /* Port C Select Register */

Definition at line 384 of file MC68EZ328.h.

#define PCTRL   BYTE_REF(PCTRL_ADDR)

Definition at line 182 of file MC68EZ328.h.

#define PCTRL_ADDR   0xfffff207

Definition at line 181 of file MC68EZ328.h.

#define PCTRL_PCEN   0x80 /* Power Control Enable */

Definition at line 186 of file MC68EZ328.h.

#define PCTRL_WIDTH_MASK   0x1f /* CPU Clock bursts width */

Definition at line 184 of file MC68EZ328.h.

#define PCTRL_WIDTH_SHIFT   0

Definition at line 185 of file MC68EZ328.h.

#define PD

(

x

)

(1 << (x))

Definition at line 423 of file MC68EZ328.h.

#define PD_INT0   0x01 /* Use INT0 as PD[0] */

Definition at line 425 of file MC68EZ328.h.

#define PD_INT1   0x02 /* Use INT1 as PD[1] */

Definition at line 426 of file MC68EZ328.h.

#define PD_INT2   0x04 /* Use INT2 as PD[2] */

Definition at line 427 of file MC68EZ328.h.

#define PD_INT3   0x08 /* Use INT3 as PD[3] */

Definition at line 428 of file MC68EZ328.h.

#define PD_IRQ1   0x10 /* Use IRQ1 as PD[4] */

Definition at line 429 of file MC68EZ328.h.

#define PD_IRQ2   0x20 /* Use IRQ2 as PD[5] */

Definition at line 430 of file MC68EZ328.h.

#define PD_IRQ3   0x40 /* Use IRQ3 as PD[6] */

Definition at line 431 of file MC68EZ328.h.

#define PD_IRQ6   0x80 /* Use IRQ6 as PD[7] */

Definition at line 432 of file MC68EZ328.h.

#define PDDATA   BYTE_REF(PDDATA_ADDR)

Definition at line 415 of file MC68EZ328.h.

#define PDDATA_ADDR   0xfffff419 /* Port D data register */

Definition at line 406 of file MC68EZ328.h.

#define PDDIR   BYTE_REF(PDDIR_ADDR)

Definition at line 414 of file MC68EZ328.h.

#define PDDIR_ADDR   0xfffff418 /* Port D direction reg */

Definition at line 405 of file MC68EZ328.h.

#define PDIQEG   BYTE_REF(PDIQEG_ADDR)

Definition at line 421 of file MC68EZ328.h.

#define PDIQEG_ADDR   0xfffff41f /* Port D IRQ Edge Register */

Definition at line 412 of file MC68EZ328.h.

#define PDIRQEN   BYTE_REF(PDIRQEN_ADDR)

Definition at line 419 of file MC68EZ328.h.

#define PDIRQEN_ADDR   0xfffff41d /* Port D IRQ enable register */

Definition at line 410 of file MC68EZ328.h.

#define PDKBEN   BYTE_REF(PDKBEN_ADDR)

Definition at line 420 of file MC68EZ328.h.

#define PDKBEN_ADDR   0xfffff41e /* Port D Keyboard Enable reg */

Definition at line 411 of file MC68EZ328.h.

#define PDPOL   BYTE_REF(PDPOL_ADDR)

Definition at line 418 of file MC68EZ328.h.

#define PDPOL_ADDR   0xfffff41c /* Port D Polarity Register */

Definition at line 409 of file MC68EZ328.h.

#define PDPUEN   BYTE_REF(PDPUEN_ADDR)

Definition at line 416 of file MC68EZ328.h.

#define PDPUEN_ADDR   0xfffff41a /* Port D Pull-Up enable reg */

Definition at line 407 of file MC68EZ328.h.

#define PDSEL   BYTE_REF(PDSEL_ADDR)

Definition at line 417 of file MC68EZ328.h.

#define PDSEL_ADDR   0xfffff41b /* Port D Select Register */

Definition at line 408 of file MC68EZ328.h.

#define PE

(

x

)

(1 << (x))

Definition at line 447 of file MC68EZ328.h.

#define PE_CTS   0x80 /* Use CTS as PE[7] */

Definition at line 456 of file MC68EZ328.h.

#define PE_DWE   0x08 /* Use DWE as PE[3] */

Definition at line 452 of file MC68EZ328.h.

#define PE_RTS   0x40 /* Use RTS as PE[6] */

Definition at line 455 of file MC68EZ328.h.

#define PE_RXD   0x10 /* Use RXD as PE[4] */

Definition at line 453 of file MC68EZ328.h.

#define PE_SPMCLK   0x04 /* Use SPMCLK as PE[2] */

Definition at line 451 of file MC68EZ328.h.

#define PE_SPMRXD   0x02 /* Use SPMRXD as PE[1] */

Definition at line 450 of file MC68EZ328.h.

#define PE_SPMTXD   0x01 /* Use SPMTXD as PE[0] */

Definition at line 449 of file MC68EZ328.h.

#define PE_TXD   0x20 /* Use TXD as PE[5] */

Definition at line 454 of file MC68EZ328.h.

#define PEDATA   BYTE_REF(PEDATA_ADDR)

Definition at line 443 of file MC68EZ328.h.

#define PEDATA_ADDR   0xfffff421 /* Port E data register */

Definition at line 438 of file MC68EZ328.h.

#define PEDIR   BYTE_REF(PEDIR_ADDR)

Definition at line 442 of file MC68EZ328.h.

#define PEDIR_ADDR   0xfffff420 /* Port E direction reg */

Definition at line 437 of file MC68EZ328.h.

#define PEPUEN   BYTE_REF(PEPUEN_ADDR)

Definition at line 444 of file MC68EZ328.h.

#define PEPUEN_ADDR   0xfffff422 /* Port E Pull-Up enable reg */

Definition at line 439 of file MC68EZ328.h.

#define PESEL   BYTE_REF(PESEL_ADDR)

Definition at line 445 of file MC68EZ328.h.

#define PESEL_ADDR   0xfffff423 /* Port E Select Register */

Definition at line 440 of file MC68EZ328.h.

#define PF

(

x

)

(1 << (x))

Definition at line 471 of file MC68EZ328.h.

#define PF_A20   0x08 /* Use A20 as PF[3] */

Definition at line 476 of file MC68EZ328.h.

#define PF_A21   0x10 /* Use A21 as PF[4] */

Definition at line 477 of file MC68EZ328.h.

#define PF_A22   0x20 /* Use A22 as PF[5] */

Definition at line 478 of file MC68EZ328.h.

#define PF_A23   0x40 /* Use A23 as PF[6] */

Definition at line 479 of file MC68EZ328.h.

#define PF_CLKO   0x04 /* Use CLKO as PF[2] */

Definition at line 475 of file MC68EZ328.h.

#define PF_CSA1   0x80 /* Use CSA1 as PF[7] */

Definition at line 480 of file MC68EZ328.h.

#define PF_IRQ5   0x02 /* Use IRQ5 as PF[1] */

Definition at line 474 of file MC68EZ328.h.

#define PF_LCONTRAST   0x01 /* Use LCONTRAST as PF[0] */

Definition at line 473 of file MC68EZ328.h.

#define PFDATA   BYTE_REF(PFDATA_ADDR)

Definition at line 467 of file MC68EZ328.h.

#define PFDATA_ADDR   0xfffff429 /* Port F data register */

Definition at line 462 of file MC68EZ328.h.

#define PFDIR   BYTE_REF(PFDIR_ADDR)

Definition at line 466 of file MC68EZ328.h.

#define PFDIR_ADDR   0xfffff428 /* Port F direction reg */

Definition at line 461 of file MC68EZ328.h.

#define PFPUEN   BYTE_REF(PFPUEN_ADDR)

Definition at line 468 of file MC68EZ328.h.

#define PFPUEN_ADDR   0xfffff42a /* Port F Pull-Up enable reg */

Definition at line 463 of file MC68EZ328.h.

#define PFSEL   BYTE_REF(PFSEL_ADDR)

Definition at line 469 of file MC68EZ328.h.

#define PFSEL_ADDR   0xfffff42b /* Port F Select Register */

Definition at line 464 of file MC68EZ328.h.

#define PG

(

x

)

(1 << (x))

Definition at line 495 of file MC68EZ328.h.

#define PG_A0   0x02 /* Use A0 as PG[1] */

Definition at line 498 of file MC68EZ328.h.

#define PG_BUSW_DTACK   0x01 /* Use BUSW/DTACK as PG[0] */

Definition at line 497 of file MC68EZ328.h.

#define PG_EMUBRK   0x20 /* Use EMUBRK as PG[5] */

Definition at line 502 of file MC68EZ328.h.

#define PG_EMUCS   0x10 /* Use EMUCS as PG[4] */

Definition at line 501 of file MC68EZ328.h.

#define PG_EMUIRQ   0x04 /* Use EMUIRQ as PG[2] */

Definition at line 499 of file MC68EZ328.h.

#define PG_HIZ_P_D   0x08 /* Use HIZ/P/D as PG[3] */

Definition at line 500 of file MC68EZ328.h.

#define PGDATA   BYTE_REF(PGDATA_ADDR)

Definition at line 491 of file MC68EZ328.h.

#define PGDATA_ADDR   0xfffff431 /* Port G data register */

Definition at line 486 of file MC68EZ328.h.

#define PGDIR   BYTE_REF(PGDIR_ADDR)

Definition at line 490 of file MC68EZ328.h.

#define PGDIR_ADDR   0xfffff430 /* Port G direction reg */

Definition at line 485 of file MC68EZ328.h.

#define PGPUEN   BYTE_REF(PGPUEN_ADDR)

Definition at line 492 of file MC68EZ328.h.

#define PGPUEN_ADDR   0xfffff432 /* Port G Pull-Up enable reg */

Definition at line 487 of file MC68EZ328.h.

#define PGSEL   BYTE_REF(PGSEL_ADDR)

Definition at line 493 of file MC68EZ328.h.

#define PGSEL_ADDR   0xfffff433 /* Port G Select Register */

Definition at line 488 of file MC68EZ328.h.

#define PLLCR   WORD_REF(PLLCR_ADDR)

Definition at line 151 of file MC68EZ328.h.

#define PLLCR_ADDR   0xfffff200

Definition at line 150 of file MC68EZ328.h.

#define PLLCR_CLKEN   0x0010 /* Clock (CLKO pin) enable */

Definition at line 154 of file MC68EZ328.h.

#define PLLCR_DISPLL   0x0008 /* Disable PLL */

Definition at line 153 of file MC68EZ328.h.

#define PLLCR_LCDCLK_SEL_MASK   0x3800 /* LCD Clock Selection */

Definition at line 158 of file MC68EZ328.h.

#define PLLCR_LCDCLK_SEL_SHIFT   11

Definition at line 159 of file MC68EZ328.h.

#define PLLCR_PIXCLK_SEL_MASK   PLLCR_LCDCLK_SEL_MASK

Definition at line 162 of file MC68EZ328.h.

#define PLLCR_PIXCLK_SEL_SHIFT   PLLCR_LCDCLK_SEL_SHIFT

Definition at line 163 of file MC68EZ328.h.

#define PLLCR_PRESC   0x0020 /* VCO prescaler */

Definition at line 155 of file MC68EZ328.h.

#define PLLCR_SYSCLK_SEL_MASK   0x0700 /* System Clock Selection */

Definition at line 156 of file MC68EZ328.h.

#define PLLCR_SYSCLK_SEL_SHIFT   8

Definition at line 157 of file MC68EZ328.h.

#define PLLFSR   WORD_REF(PLLFSR_ADDR)

Definition at line 169 of file MC68EZ328.h.

#define PLLFSR_ADDR   0xfffff202

Definition at line 168 of file MC68EZ328.h.

#define PLLFSR_CLK32   0x8000 /* Clock 32 (kHz) */

Definition at line 176 of file MC68EZ328.h.

#define PLLFSR_PC_MASK   0x00ff /* P Count */

Definition at line 171 of file MC68EZ328.h.

#define PLLFSR_PC_SHIFT   0

Definition at line 172 of file MC68EZ328.h.

#define PLLFSR_PROT   0x4000 /* Protect P & Q */

Definition at line 175 of file MC68EZ328.h.

#define PLLFSR_QC_MASK   0x0f00 /* Q Count */

Definition at line 173 of file MC68EZ328.h.

#define PLLFSR_QC_SHIFT   8

Definition at line 174 of file MC68EZ328.h.

#define PMNC_FIFOAV   0x0020 /* FIFO Available */

Definition at line 521 of file MC68EZ328.h.

#define PUT_FIELD	(		field,
			val
	)		(((val) << field##_SHIFT) & field##_MASK)

Definition at line 20 of file MC68EZ328.h.

#define PWM_IRQ_NUM   7 /* Pulse-Width Modulator int. */

Definition at line 234 of file MC68EZ328.h.

#define PWMC   WORD_REF(PWMC_ADDR)

Definition at line 514 of file MC68EZ328.h.

#define PWMC_ADDR   0xfffff500

Definition at line 513 of file MC68EZ328.h.

#define PWMC_CLKSEL_MASK   0x0003 /* Clock Selection */

Definition at line 516 of file MC68EZ328.h.

#define PWMC_CLKSEL_SHIFT   0

Definition at line 517 of file MC68EZ328.h.

#define PWMC_CLKSRC   0x8000 /* Clock Source Select */

Definition at line 526 of file MC68EZ328.h.

#define PWMC_EN   0x0010 /* Enable PWM */

Definition at line 520 of file MC68EZ328.h.

#define PWMC_IRQ   0x0080 /* Interrupt Request (FIFO empty) */

Definition at line 523 of file MC68EZ328.h.

#define PWMC_IRQEN   0x0040 /* Interrupt Request Enable */

Definition at line 522 of file MC68EZ328.h.

#define PWMC_PRESCALER_MASK   0x7f00 /* Incoming Clock prescaler */

Definition at line 524 of file MC68EZ328.h.

#define PWMC_PRESCALER_SHIFT   8

Definition at line 525 of file MC68EZ328.h.

#define PWMC_PWMEN   PWMC_EN

Definition at line 529 of file MC68EZ328.h.

#define PWMC_REPEAT_MASK   0x000c /* Sample Repeats */

Definition at line 518 of file MC68EZ328.h.

#define PWMC_REPEAT_SHIFT   2

Definition at line 519 of file MC68EZ328.h.

#define PWMCNT   BYTE_REF(PWMCNT_ADDR)

Definition at line 547 of file MC68EZ328.h.

#define PWMCNT_ADDR   0xfffff505

Definition at line 546 of file MC68EZ328.h.

#define PWMP   BYTE_REF(PWMP_ADDR)

Definition at line 541 of file MC68EZ328.h.

#define PWMP_ADDR   0xfffff504

Definition at line 540 of file MC68EZ328.h.

#define PWMR   WORD_REF(PWMR_ADDR)

Definition at line 1000 of file MC68EZ328.h.

#define PWMR_ADDR   0xfffffa36

Definition at line 999 of file MC68EZ328.h.

#define PWMR_CCPEN   0x0100 /* Contrast Control Enable */

Definition at line 1004 of file MC68EZ328.h.

#define PWMR_PW_MASK   0x00ff /* Pulse Width */

Definition at line 1002 of file MC68EZ328.h.

#define PWMR_PW_SHIFT   0

Definition at line 1003 of file MC68EZ328.h.

#define PWMR_SRC_LCD   0x4000 /* LCD clock */

Definition at line 1008 of file MC68EZ328.h.

#define PWMR_SRC_LINE   0x0000 /* Line Pulse */

Definition at line 1006 of file MC68EZ328.h.

#define PWMR_SRC_MASK   0x0600 /* Input Clock Source */

Definition at line 1005 of file MC68EZ328.h.

#define PWMR_SRC_PIXEL   0x0200 /* Pixel Clock */

Definition at line 1007 of file MC68EZ328.h.

#define PWMS   WORD_REF(PWMS_ADDR)

Definition at line 535 of file MC68EZ328.h.

#define PWMS_ADDR   0xfffff502

Definition at line 534 of file MC68EZ328.h.

#define RTC_IRQ_NUM   4 /* RTC interrupt */

Definition at line 232 of file MC68EZ328.h.

#define RTCALRM   LONG_REF(RTCALRM_ADDR)

Definition at line 1033 of file MC68EZ328.h.

#define RTCALRM_ADDR   0xfffffb04

Definition at line 1032 of file MC68EZ328.h.

#define RTCALRM_HOURS_MASK   0x1f000000 /* Hours */

Definition at line 1039 of file MC68EZ328.h.

#define RTCALRM_HOURS_SHIFT   24

Definition at line 1040 of file MC68EZ328.h.

#define RTCALRM_MINUTES_MASK   0x003f0000 /* Minutes */

Definition at line 1037 of file MC68EZ328.h.

#define RTCALRM_MINUTES_SHIFT   16

Definition at line 1038 of file MC68EZ328.h.

#define RTCALRM_SECONDS_MASK   0x0000003f /* Seconds */

Definition at line 1035 of file MC68EZ328.h.

#define RTCALRM_SECONDS_SHIFT   0

Definition at line 1036 of file MC68EZ328.h.

#define RTCCTL   WORD_REF(RTCCTL_ADDR)

Definition at line 1058 of file MC68EZ328.h.

#define RTCCTL_384   RTCCTL_XTL

Definition at line 1064 of file MC68EZ328.h.

#define RTCCTL_ADDR   0xfffffb0c

Definition at line 1057 of file MC68EZ328.h.

#define RTCCTL_EN   0x0080 /* RTC Enable */

Definition at line 1061 of file MC68EZ328.h.

#define RTCCTL_ENABLE   RTCCTL_EN

Definition at line 1065 of file MC68EZ328.h.

#define RTCCTL_XTL   0x0020 /* Crystal Selection */

Definition at line 1060 of file MC68EZ328.h.

#define RTCIENR   WORD_REF(RTCIENR_ADDR)

Definition at line 1092 of file MC68EZ328.h.

#define RTCIENR_1HZ   0x0010 /* 1Hz interrupt enable */

Definition at line 1098 of file MC68EZ328.h.

#define RTCIENR_ADDR   0xfffffb10

Definition at line 1091 of file MC68EZ328.h.

#define RTCIENR_ALM   0x0004 /* Alarm interrupt enable */

Definition at line 1096 of file MC68EZ328.h.

#define RTCIENR_DAY   0x0008 /* 24-hour rollover interrupt enable */

Definition at line 1097 of file MC68EZ328.h.

#define RTCIENR_HR   0x0020 /* 1-hour interrupt enable */

Definition at line 1099 of file MC68EZ328.h.

#define RTCIENR_MIN   0x0002 /* 1-minute interrupt enable */

Definition at line 1095 of file MC68EZ328.h.

#define RTCIENR_SAM0   0x0100 /* 4Hz / 4.6875Hz interrupt enable */

Definition at line 1100 of file MC68EZ328.h.

#define RTCIENR_SAM1   0x0200 /* 8Hz / 9.3750Hz interrupt enable */

Definition at line 1101 of file MC68EZ328.h.

#define RTCIENR_SAM2   0x0400 /* 16Hz / 18.7500Hz interrupt enable */

Definition at line 1102 of file MC68EZ328.h.

#define RTCIENR_SAM3   0x0800 /* 32Hz / 37.5000Hz interrupt enable */

Definition at line 1103 of file MC68EZ328.h.

#define RTCIENR_SAM4   0x1000 /* 64Hz / 75.0000Hz interrupt enable */

Definition at line 1104 of file MC68EZ328.h.

#define RTCIENR_SAM5   0x2000 /* 128Hz / 150.0000Hz interrupt enable */

Definition at line 1105 of file MC68EZ328.h.

#define RTCIENR_SAM6   0x4000 /* 256Hz / 300.0000Hz interrupt enable */

Definition at line 1106 of file MC68EZ328.h.

#define RTCIENR_SAM7   0x8000 /* 512Hz / 600.0000Hz interrupt enable */

Definition at line 1107 of file MC68EZ328.h.

#define RTCIENR_SW   0x0001 /* Stopwatch interrupt enable */

Definition at line 1094 of file MC68EZ328.h.

#define RTCISR   WORD_REF(RTCISR_ADDR)

Definition at line 1071 of file MC68EZ328.h.

#define RTCISR_1HZ   0x0010 /* 1Hz interrupt has occurred */

Definition at line 1077 of file MC68EZ328.h.

#define RTCISR_ADDR   0xfffffb0e

Definition at line 1070 of file MC68EZ328.h.

#define RTCISR_ALM   0x0004 /* Alarm interrupt has occurred */

Definition at line 1075 of file MC68EZ328.h.

#define RTCISR_DAY   0x0008 /* 24-hour rollover interrupt has occurred */

Definition at line 1076 of file MC68EZ328.h.

#define RTCISR_HR   0x0020 /* 1-hour interrupt has occurred */

Definition at line 1078 of file MC68EZ328.h.

#define RTCISR_MIN   0x0002 /* 1-minute interrupt has occurred */

Definition at line 1074 of file MC68EZ328.h.

#define RTCISR_SAM0   0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */

Definition at line 1079 of file MC68EZ328.h.

#define RTCISR_SAM1   0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */

Definition at line 1080 of file MC68EZ328.h.

#define RTCISR_SAM2   0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */

Definition at line 1081 of file MC68EZ328.h.

#define RTCISR_SAM3   0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */

Definition at line 1082 of file MC68EZ328.h.

#define RTCISR_SAM4   0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */

Definition at line 1083 of file MC68EZ328.h.

#define RTCISR_SAM5   0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */

Definition at line 1084 of file MC68EZ328.h.

#define RTCISR_SAM6   0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */

Definition at line 1085 of file MC68EZ328.h.

#define RTCISR_SAM7   0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */

Definition at line 1086 of file MC68EZ328.h.

#define RTCISR_SW   0x0001 /* Stopwatch timed out */

Definition at line 1073 of file MC68EZ328.h.

#define RTCTIME   LONG_REF(RTCTIME_ADDR)

Definition at line 1020 of file MC68EZ328.h.

#define RTCTIME_ADDR   0xfffffb00

Definition at line 1019 of file MC68EZ328.h.

#define RTCTIME_HOURS_MASK   0x1f000000 /* Hours */

Definition at line 1026 of file MC68EZ328.h.

#define RTCTIME_HOURS_SHIFT   24

Definition at line 1027 of file MC68EZ328.h.

#define RTCTIME_MINUTES_MASK   0x003f0000 /* Minutes */

Definition at line 1024 of file MC68EZ328.h.

#define RTCTIME_MINUTES_SHIFT   16

Definition at line 1025 of file MC68EZ328.h.

#define RTCTIME_SECONDS_MASK   0x0000003f /* Seconds */

Definition at line 1022 of file MC68EZ328.h.

#define RTCTIME_SECONDS_SHIFT   0

Definition at line 1023 of file MC68EZ328.h.

#define SAM_IRQ_NUM   22 /* Sampling Timer for RTC */

Definition at line 244 of file MC68EZ328.h.

#define SCR   BYTE_REF(SCR_ADDR)

Definition at line 33 of file MC68EZ328.h.

#define SCR_ADDR   0xfffff000

Definition at line 32 of file MC68EZ328.h.

#define SCR_BETEN   0x10 /* Bus-Error Time-Out Enable */

Definition at line 38 of file MC68EZ328.h.

#define SCR_BETO   0x80 /* Bus-Error TimeOut */

Definition at line 41 of file MC68EZ328.h.

#define SCR_DMAP   0x04 /* Double Map */

Definition at line 36 of file MC68EZ328.h.

#define SCR_PRV   0x20 /* Privilege Violation */

Definition at line 39 of file MC68EZ328.h.

#define SCR_SO   0x08 /* Supervisor Only */

Definition at line 37 of file MC68EZ328.h.

#define SCR_WDTH8   0x01 /* 8-Bit Width Select */

Definition at line 35 of file MC68EZ328.h.

#define SCR_WPV   0x40 /* Write Protect Violation */

Definition at line 40 of file MC68EZ328.h.

#define SPI_IRQ_NUM   0 /* SPI interrupt */

Definition at line 228 of file MC68EZ328.h.

#define SPIM_IRQ_NUM   SPI_IRQ_NUM

Definition at line 248 of file MC68EZ328.h.

#define SPIMCONT   WORD_REF(SPIMCONT_ADDR)

Definition at line 648 of file MC68EZ328.h.

#define SPIMCONT_ADDR   0xfffff802

Definition at line 647 of file MC68EZ328.h.

#define SPIMCONT_BIT_COUNT_MASK   0x000f /* Transfer Length in Bytes */

Definition at line 650 of file MC68EZ328.h.

#define SPIMCONT_BIT_COUNT_SHIFT   0

Definition at line 651 of file MC68EZ328.h.

#define SPIMCONT_DATA_RATE_MASK   0xe000 /* SPIM Data Rate */

Definition at line 658 of file MC68EZ328.h.

#define SPIMCONT_DATA_RATE_SHIFT   13

Definition at line 659 of file MC68EZ328.h.

#define SPIMCONT_ENABLE   0x0200 /* Enable SPIM */

Definition at line 657 of file MC68EZ328.h.

#define SPIMCONT_IRQ   0x0080 /* Interrupt Request */

Definition at line 655 of file MC68EZ328.h.

#define SPIMCONT_IRQEN   0x0040 /* IRQ Enable */

Definition at line 654 of file MC68EZ328.h.

#define SPIMCONT_PHA   0x0020 /* Clock/Data phase relationship */

Definition at line 653 of file MC68EZ328.h.

#define SPIMCONT_POL   0x0010 /* SPMCLK Signel Polarity */

Definition at line 652 of file MC68EZ328.h.

#define SPIMCONT_SPIMEN   SPIMCONT_ENABLE

Definition at line 663 of file MC68EZ328.h.

#define SPIMCONT_SPIMIRQ   SPIMCONT_IRQ

Definition at line 662 of file MC68EZ328.h.

#define SPIMCONT_XCH   0x0100 /* Exchange */

Definition at line 656 of file MC68EZ328.h.

#define SPIMDATA   WORD_REF(SPIMDATA_ADDR)

Definition at line 642 of file MC68EZ328.h.

#define SPIMDATA_ADDR   0xfffff800

Definition at line 641 of file MC68EZ328.h.

#define SPTWCH_CNT_SHIFT   0

Definition at line 1116 of file MC68EZ328.h.

#define STPWCH   WORD_REF(STPWCH)

Definition at line 1113 of file MC68EZ328.h.

#define STPWCH_ADDR   0xfffffb12

Definition at line 1112 of file MC68EZ328.h.

#define STPWCH_CNT_MASK   0x003f /* Stopwatch countdown value */

Definition at line 1115 of file MC68EZ328.h.

#define TCMP   WORD_REF(TCMP_ADDR)

Definition at line 593 of file MC68EZ328.h.

#define TCMP1   TCMP

Definition at line 597 of file MC68EZ328.h.

#define TCMP1_ADDR   TCMP_ADDR

Definition at line 596 of file MC68EZ328.h.

#define TCMP_ADDR   0xfffff604

Definition at line 592 of file MC68EZ328.h.

#define TCN   WORD_REF(TCN_ADDR)

Definition at line 613 of file MC68EZ328.h.

#define TCN1   TCN

Definition at line 617 of file MC68EZ328.h.

#define TCN1_ADDR   TCN_ADDR

Definition at line 616 of file MC68EZ328.h.

#define TCN_ADDR   0xfffff608

Definition at line 612 of file MC68EZ328.h.

#define TCR   WORD_REF(TCR_ADDR)

Definition at line 603 of file MC68EZ328.h.

#define TCR1   TCR

Definition at line 607 of file MC68EZ328.h.

#define TCR1_ADDR   TCR_ADDR

Definition at line 606 of file MC68EZ328.h.

#define TCR_ADDR   0xfffff606

Definition at line 602 of file MC68EZ328.h.

#define TCTL   WORD_REF(TCTL_ADDR)

Definition at line 559 of file MC68EZ328.h.

#define TCTL1   TCTL

Definition at line 577 of file MC68EZ328.h.

#define TCTL1_ADDR   TCTL_ADDR

Definition at line 576 of file MC68EZ328.h.

#define TCTL_ADDR   0xfffff600

Definition at line 558 of file MC68EZ328.h.

#define TCTL_CAP_FE   0x0080 /* Capture on falling edge */

Definition at line 572 of file MC68EZ328.h.

#define TCTL_CAP_MASK   0x00c0 /* Capture Edge: */

Definition at line 570 of file MC68EZ328.h.

#define TCTL_CAP_RE   0x0040 /* Capture on rizing edge */

Definition at line 571 of file MC68EZ328.h.

#define TCTL_CLKSOURCE_32KHZ   0x0008 /* 32kHz clock to prescaler */

Definition at line 567 of file MC68EZ328.h.

#define TCTL_CLKSOURCE_MASK   0x000e /* Clock Source: */

Definition at line 562 of file MC68EZ328.h.

#define TCTL_CLKSOURCE_STOP   0x0000 /* Stop count (disabled) */

Definition at line 563 of file MC68EZ328.h.

#define TCTL_CLKSOURCE_SYSCLK   0x0002 /* SYSCLK to prescaler */

Definition at line 564 of file MC68EZ328.h.

#define TCTL_CLKSOURCE_SYSCLK_16   0x0004 /* SYSCLK/16 to prescaler */

Definition at line 565 of file MC68EZ328.h.

#define TCTL_CLKSOURCE_TIN   0x0006 /* TIN to prescaler */

Definition at line 566 of file MC68EZ328.h.

#define TCTL_FRR   0x0010 /* Free-Run Mode */

Definition at line 573 of file MC68EZ328.h.

#define TCTL_IRQEN   0x0010 /* IRQ Enable */

Definition at line 568 of file MC68EZ328.h.

#define TCTL_OM   0x0020 /* Output Mode */

Definition at line 569 of file MC68EZ328.h.

#define TCTL_TEN   0x0001 /* Timer Enable */

Definition at line 561 of file MC68EZ328.h.

#define TMR1_IRQ_NUM   TMR_IRQ_NUM

Definition at line 249 of file MC68EZ328.h.

#define TMR_IRQ_NUM   1 /* Timer interrupt */

Definition at line 229 of file MC68EZ328.h.

#define TPRER   WORD_REF(TPRER_ADDR)

Definition at line 583 of file MC68EZ328.h.

#define TPRER1   TPRER

Definition at line 587 of file MC68EZ328.h.

#define TPRER1_ADDR   TPRER_ADDR

Definition at line 586 of file MC68EZ328.h.

#define TPRER_ADDR   0xfffff602

Definition at line 582 of file MC68EZ328.h.

#define TSTAT   WORD_REF(TSTAT_ADDR)

Definition at line 623 of file MC68EZ328.h.

#define TSTAT1   TSTAT

Definition at line 630 of file MC68EZ328.h.

#define TSTAT1_ADDR   TSTAT_ADDR

Definition at line 629 of file MC68EZ328.h.

#define TSTAT_ADDR   0xfffff60a

Definition at line 622 of file MC68EZ328.h.

#define TSTAT_CAPT   0x0001 /* Capture Event occurred */

Definition at line 626 of file MC68EZ328.h.

#define TSTAT_COMP   0x0001 /* Compare Event occurred */

Definition at line 625 of file MC68EZ328.h.

#define UART_IRQ_NUM   2 /* UART interrupt */

Definition at line 230 of file MC68EZ328.h.

#define UBAUD   WORD_REF(UBAUD_ADDR)

Definition at line 711 of file MC68EZ328.h.

#define UBAUD_ADDR   0xfffff902

Definition at line 710 of file MC68EZ328.h.

#define UBAUD_BAUD_SRC   0x0800 /* Baud Rate Source */

Definition at line 717 of file MC68EZ328.h.

#define UBAUD_DIVIDE_MASK   0x0700 /* Baud Rate freq. divizor */

Definition at line 715 of file MC68EZ328.h.

#define UBAUD_DIVIDE_SHIFT   8

Definition at line 716 of file MC68EZ328.h.

#define UBAUD_PRESCALER_MASK   0x003f /* Actual divisor is 65 - PRESCALER */

Definition at line 713 of file MC68EZ328.h.

#define UBAUD_PRESCALER_SHIFT   0

Definition at line 714 of file MC68EZ328.h.

#define UBAUD_UCLKDIR   0x2000 /* UCLK Direction */

Definition at line 718 of file MC68EZ328.h.

#define UMISC   WORD_REF(UMISC_ADDR)

Definition at line 768 of file MC68EZ328.h.

#define UMISC_ADDR   0xfffff908

Definition at line 767 of file MC68EZ328.h.

#define UMISC_BAUD_RESET   0x0800 /* Reset Baud Rate Generation Counters */

Definition at line 777 of file MC68EZ328.h.

#define UMISC_BAUD_TEST   0x8000 /* Enable Baud Test Mode */

Definition at line 781 of file MC68EZ328.h.

#define UMISC_CLKSRC   0x4000 /* Clock Source */

Definition at line 780 of file MC68EZ328.h.

#define UMISC_FORCE_PERR   0x2000 /* Force Parity Error */

Definition at line 779 of file MC68EZ328.h.

#define UMISC_IR_TEST   0x0400 /* IRDA Test Enable */

Definition at line 776 of file MC68EZ328.h.

#define UMISC_IRDA_EN   0x0020 /* Infra-Red Enable */

Definition at line 773 of file MC68EZ328.h.

#define UMISC_IRDA_LOOP   0x0010 /* IrDA Loopback Enable */

Definition at line 772 of file MC68EZ328.h.

#define UMISC_LOOP   0x1000 /* Serial Loopback Enable */

Definition at line 778 of file MC68EZ328.h.

#define UMISC_RTS   0x0040 /* Set RTS status */

Definition at line 774 of file MC68EZ328.h.

#define UMISC_RTSCONT   0x0080 /* Choose RTS control */

Definition at line 775 of file MC68EZ328.h.

#define UMISC_RX_POL   0x0008 /* Receive Polarity */

Definition at line 771 of file MC68EZ328.h.

#define UMISC_TX_POL   0x0004 /* Transmit Polarity */

Definition at line 770 of file MC68EZ328.h.

#define URX   WORD_REF(URX_ADDR)

Definition at line 724 of file MC68EZ328.h.

#define URX_ADDR   0xfffff904

Definition at line 723 of file MC68EZ328.h.

#define URX_BREAK   0x0200 /* Break Detected */

Definition at line 732 of file MC68EZ328.h.

#define URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */

Definition at line 736 of file MC68EZ328.h.

#define URX_FIFO_FULL   0x8000 /* FIFO is Full */

Definition at line 738 of file MC68EZ328.h.

#define URX_FIFO_HALF   0x4000 /* FIFO is Half-Full */

Definition at line 737 of file MC68EZ328.h.

#define URX_FRAME_ERROR   0x0400 /* Framing Error */

Definition at line 733 of file MC68EZ328.h.

#define URX_OLD_DATA   0x1000 /* Old data in FIFO */

Definition at line 735 of file MC68EZ328.h.

#define URX_OVRUN   0x0800 /* Serial Overrun */

Definition at line 734 of file MC68EZ328.h.

#define URX_PARITY_ERROR   0x0100 /* Parity Error */

Definition at line 731 of file MC68EZ328.h.

#define URX_RXDATA   BYTE_REF(URX_RXDATA_ADDR)

Definition at line 727 of file MC68EZ328.h.

#define URX_RXDATA_ADDR   0xfffff905

Definition at line 726 of file MC68EZ328.h.

#define URX_RXDATA_MASK   0x00ff /* Received data */

Definition at line 729 of file MC68EZ328.h.

#define URX_RXDATA_SHIFT   0

Definition at line 730 of file MC68EZ328.h.

#define USTCNT   WORD_REF(USTCNT_ADDR)

Definition at line 675 of file MC68EZ328.h.

#define USTCNT_8_7   0x0100 /* Eight or seven-bit transmission */

Definition at line 685 of file MC68EZ328.h.

#define USTCNT_ADDR   0xfffff900

Definition at line 674 of file MC68EZ328.h.

#define USTCNT_CLKM   0x1000 /* Clock Mode Select */

Definition at line 689 of file MC68EZ328.h.

#define USTCNT_CLKMODE   USTCNT_CLKM

Definition at line 704 of file MC68EZ328.h.

#define USTCNT_CTSD   0x0040 /* CTS Delta Interrupt Enable */

Definition at line 683 of file MC68EZ328.h.

#define USTCNT_CTSDELTAEN   USTCNT_CTSD

Definition at line 701 of file MC68EZ328.h.

#define USTCNT_ODD   0x0400 /* Odd Parity */

Definition at line 687 of file MC68EZ328.h.

#define USTCNT_ODD_EVEN   USTCNT_ODD

Definition at line 702 of file MC68EZ328.h.

#define USTCNT_ODEN   0x0080 /* Old Data Interrupt Enable */

Definition at line 684 of file MC68EZ328.h.

#define USTCNT_PARITYEN   USTCNT_PEN

Definition at line 703 of file MC68EZ328.h.

#define USTCNT_PEN   0x0800 /* Parity Enable */

Definition at line 688 of file MC68EZ328.h.

#define USTCNT_RXEN   0x4000 /* Receiver Enable */

Definition at line 691 of file MC68EZ328.h.

#define USTCNT_RXFE   0x0020 /* Receiver Full Interrupt Enable */

Definition at line 682 of file MC68EZ328.h.

#define USTCNT_RXFULLEN   USTCNT_RXFE

Definition at line 700 of file MC68EZ328.h.

#define USTCNT_RXHALFEN   USTCNT_RXHE

Definition at line 699 of file MC68EZ328.h.

#define USTCNT_RXHE   0x0010 /* Receiver Half-Full Interrupt Enable */

Definition at line 681 of file MC68EZ328.h.

#define USTCNT_RXRE   0x0008 /* Receiver Ready Interrupt Enable */

Definition at line 680 of file MC68EZ328.h.

#define USTCNT_RXREADYEN   USTCNT_RXRE

Definition at line 698 of file MC68EZ328.h.

#define USTCNT_STOP   0x0200 /* Stop bit transmission */

Definition at line 686 of file MC68EZ328.h.

#define USTCNT_TXAE   0x0001 /* Transmitter Available Interrupt Enable */

Definition at line 677 of file MC68EZ328.h.

#define USTCNT_TXAVAILEN   USTCNT_TXAE

Definition at line 695 of file MC68EZ328.h.

#define USTCNT_TXEE   0x0004 /* Transmitter Empty Interrupt Enable */

Definition at line 679 of file MC68EZ328.h.

#define USTCNT_TXEMPTYEN   USTCNT_TXEE

Definition at line 697 of file MC68EZ328.h.

#define USTCNT_TXEN   0x2000 /* Transmitter Enable */

Definition at line 690 of file MC68EZ328.h.

#define USTCNT_TXHALFEN   USTCNT_TXHE

Definition at line 696 of file MC68EZ328.h.

#define USTCNT_TXHE   0x0002 /* Transmitter Half Empty Enable */

Definition at line 678 of file MC68EZ328.h.

#define USTCNT_UARTEN   USTCNT_UEN

Definition at line 705 of file MC68EZ328.h.

#define USTCNT_UEN   0x8000 /* UART Enable */

Definition at line 692 of file MC68EZ328.h.

#define UTX   WORD_REF(UTX_ADDR)

Definition at line 744 of file MC68EZ328.h.

#define UTX_ADDR   0xfffff906

Definition at line 743 of file MC68EZ328.h.

#define UTX_BUSY   0x0400 /* FIFO is busy, sending a character */

Definition at line 753 of file MC68EZ328.h.

#define UTX_CTS_DELTA   0x0100 /* CTS changed */

Definition at line 751 of file MC68EZ328.h.

#define UTX_CTS_STAT   0x0200 /* CTS State */

Definition at line 752 of file MC68EZ328.h.

#define UTX_CTS_STATUS   UTX_CTS_STAT

Definition at line 761 of file MC68EZ328.h.

#define UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */

Definition at line 758 of file MC68EZ328.h.

#define UTX_FIFO_HALF   0x4000 /* Transmit FIFO is half empty */

Definition at line 757 of file MC68EZ328.h.

#define UTX_IGNORE_CTS   UTX_NOCTS

Definition at line 762 of file MC68EZ328.h.

#define UTX_NOCTS   0x0800 /* Ignore CTS */

Definition at line 754 of file MC68EZ328.h.

#define UTX_SEND_BREAK   0x1000 /* Send a BREAK */

Definition at line 755 of file MC68EZ328.h.

#define UTX_TX_AVAIL   0x2000 /* Transmit FIFO has a slot available */

Definition at line 756 of file MC68EZ328.h.

#define UTX_TXDATA   BYTE_REF(UTX_TXDATA_ADDR)

Definition at line 747 of file MC68EZ328.h.

#define UTX_TXDATA_ADDR   0xfffff907

Definition at line 746 of file MC68EZ328.h.

#define UTX_TXDATA_MASK   0x00ff /* Data to be transmitted */

Definition at line 749 of file MC68EZ328.h.

#define UTX_TXDATA_SHIFT   0

Definition at line 750 of file MC68EZ328.h.

#define WATCHDOG   WORD_REF(WATCHDOG_ADDR)

Definition at line 1046 of file MC68EZ328.h.

#define WATCHDOG_ADDR   0xfffffb0a

Definition at line 1045 of file MC68EZ328.h.

#define WATCHDOG_CNT_MASK   0x0300 /* Watchdog Counter */

Definition at line 1051 of file MC68EZ328.h.

#define WATCHDOG_CNT_SHIFT   8

Definition at line 1052 of file MC68EZ328.h.

#define WATCHDOG_EN   0x0001 /* Watchdog Enabled */

Definition at line 1048 of file MC68EZ328.h.

#define WATCHDOG_INTF   0x0080 /* Watchdog interrupt occurred */

Definition at line 1050 of file MC68EZ328.h.

#define WATCHDOG_ISEL   0x0002 /* Select the watchdog interrupt */

Definition at line 1049 of file MC68EZ328.h.

#define WDT_IRQ_NUM   3 /* Watchdog Timer interrupt */

Definition at line 231 of file MC68EZ328.h.

#define WORD_REF

(

addr

)

(*((volatile unsigned short*)addr))

Definition at line 17 of file MC68EZ328.h.