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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/interrupt.h>#include <linux/device.h>#include <linux/kernel.h>#include <linux/slab.h>#include <linux/sysfs.h>#include <linux/spi/spi.h>#include <linux/regulator/consumer.h>#include <linux/err.h>#include <linux/sched.h>#include <linux/delay.h>#include <linux/iio/iio.h>#include <linux/iio/sysfs.h>#include <linux/iio/buffer.h>#include <linux/iio/trigger.h>#include <linux/iio/trigger_consumer.h>#include <linux/iio/triggered_buffer.h>#include <linux/iio/adc/ad_sigma_delta.h>#include "ad7192.h"Go to the source code of this file.
Data Structures | |
| struct | ad7192_state |
Macros | |
| #define | AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ |
| #define | AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ |
| #define | AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ |
| #define | AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ |
| #define | AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ |
| #define | AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ |
| #define | AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ |
| #define | AD7192_REG_OFFSET |
| #define | AD7192_REG_FULLSALE |
| #define | AD7192_COMM_WEN (1 << 7) /* Write Enable */ |
| #define | AD7192_COMM_WRITE (0 << 6) /* Write Operation */ |
| #define | AD7192_COMM_READ (1 << 6) /* Read Operation */ |
| #define | AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ |
| #define | AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ |
| #define | AD7192_STAT_RDY (1 << 7) /* Ready */ |
| #define | AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ |
| #define | AD7192_STAT_NOREF (1 << 5) /* Error no external reference */ |
| #define | AD7192_STAT_PARITY (1 << 4) /* Parity */ |
| #define | AD7192_STAT_CH3 (1 << 2) /* Channel 3 */ |
| #define | AD7192_STAT_CH2 (1 << 1) /* Channel 2 */ |
| #define | AD7192_STAT_CH1 (1 << 0) /* Channel 1 */ |
| #define | AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ |
| #define | AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ |
| #define | AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */ |
| #define | AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ |
| #define | AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */ |
| #define | AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/ |
| #define | AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */ |
| #define | AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/ |
| #define | AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */ |
| #define | AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */ |
| #define | AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ |
| #define | AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ |
| #define | AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ |
| #define | AD7192_MODE_IDLE 2 /* Idle Mode */ |
| #define | AD7192_MODE_PWRDN 3 /* Power-Down Mode */ |
| #define | AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ |
| #define | AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ |
| #define | AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ |
| #define | AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ |
| #define | AD7192_CLK_EXT_MCLK1_2 |
| #define | AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ |
| #define | AD7192_CLK_INT |
| #define | AD7192_CLK_INT_CO |
| #define | AD7192_CONF_CHOP (1 << 23) /* CHOP enable */ |
| #define | AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */ |
| #define | AD7192_CONF_CHAN(x) (((1 << (x)) & 0xFF) << 8) /* Channel select */ |
| #define | AD7192_CONF_CHAN_MASK (0xFF << 8) /* Channel select mask */ |
| #define | AD7192_CONF_BURN (1 << 7) /* Burnout current enable */ |
| #define | AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */ |
| #define | AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */ |
| #define | AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */ |
| #define | AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ |
| #define | AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */ |
| #define | AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */ |
| #define | AD7192_CH_TEMP 2 /* Temp Sensor */ |
| #define | AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */ |
| #define | AD7192_CH_AIN1 4 /* AIN1 - AINCOM */ |
| #define | AD7192_CH_AIN2 5 /* AIN2 - AINCOM */ |
| #define | AD7192_CH_AIN3 6 /* AIN3 - AINCOM */ |
| #define | AD7192_CH_AIN4 7 /* AIN4 - AINCOM */ |
| #define | ID_AD7190 0x4 |
| #define | ID_AD7192 0x0 |
| #define | ID_AD7195 0x6 |
| #define | AD7192_ID_MASK 0x0F |
| #define | AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */ |
| #define | AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */ |
| #define | AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */ |
| #define | AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */ |
| #define | AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */ |
| #define | AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */ |
| #define | AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */ |
| #define | AD7192_INT_FREQ_MHz 4915200 |
Functions | |
| MODULE_DEVICE_TABLE (spi, ad7192_id) | |
| module_spi_driver (ad7192_driver) | |
| MODULE_AUTHOR ("Michael Hennerich <[email protected]>") | |
| MODULE_DESCRIPTION ("Analog Devices AD7190, AD7192, AD7195 ADC") | |
| MODULE_LICENSE ("GPL v2") | |
| #define AD7192_CLK_EXT_MCLK1_2 |
| #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ |
| #define AD7192_CLK_INT |
| #define AD7192_CLK_INT_CO |
| #define AD7192_CONF_CHAN_MASK (0xFF << 8) /* Channel select mask */ |
| #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */ |
| #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */ |
| #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */ |
| #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ |
| #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ |
| #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ |
| #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ |
| #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */ |
| #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */ |
| #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ |
| #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */ |
| #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ |
| #define AD7192_REG_FULLSALE |
| #define AD7192_REG_OFFSET |
| #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ |
| MODULE_AUTHOR | ( | "Michael Hennerich <[email protected]>" | ) |
| MODULE_DESCRIPTION | ( | "Analog Devices | AD7190, |
| AD7192 | , | ||
| AD7195 ADC" | |||
| ) |
| MODULE_DEVICE_TABLE | ( | spi | , |
| ad7192_id | |||
| ) |
| MODULE_LICENSE | ( | "GPL v2" | ) |
| module_spi_driver | ( | ad7192_driver | ) |
1.8.2