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ahci.h
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1 /*
2  * ahci.h - Common AHCI SATA definitions and declarations
3  *
4  * Maintained by: Jeff Garzik <[email protected]>
5  * Please ALWAYS copy [email protected]
6  * on emails.
7  *
8  * Copyright 2004-2005 Red Hat, Inc.
9  *
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2, or (at your option)
14  * any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; see the file COPYING. If not, write to
23  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24  *
25  *
26  * libata documentation is available via 'make {ps|pdf}docs',
27  * as Documentation/DocBook/libata.*
28  *
29  * AHCI hardware documentation:
30  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32  *
33  */
34 
35 #ifndef _AHCI_H
36 #define _AHCI_H
37 
38 #include <linux/clk.h>
39 #include <linux/libata.h>
40 
41 /* Enclosure Management Control */
42 #define EM_CTRL_MSG_TYPE 0x000f0000
43 
44 /* Enclosure Management LED Message Type */
45 #define EM_MSG_LED_HBA_PORT 0x0000000f
46 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
47 #define EM_MSG_LED_VALUE 0xffff0000
48 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
49 #define EM_MSG_LED_VALUE_OFF 0xfff80000
50 #define EM_MSG_LED_VALUE_ON 0x00010000
51 
52 enum {
54  AHCI_MAX_SG = 168, /* hardware max is 64K */
55  AHCI_DMA_BOUNDARY = 0xffffffff,
68  (AHCI_RX_FIS_SZ * 16),
69  AHCI_IRQ_ON_SG = (1 << 31),
70  AHCI_CMD_ATAPI = (1 << 5),
71  AHCI_CMD_WRITE = (1 << 6),
72  AHCI_CMD_PREFETCH = (1 << 7),
73  AHCI_CMD_RESET = (1 << 8),
74  AHCI_CMD_CLR_BUSY = (1 << 10),
75 
76  RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
77  RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78  RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
79  RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 
81  /* global controller registers */
82  HOST_CAP = 0x00, /* host capabilities */
83  HOST_CTL = 0x04, /* global host control */
84  HOST_IRQ_STAT = 0x08, /* interrupt status */
85  HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
86  HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
87  HOST_EM_LOC = 0x1c, /* Enclosure Management location */
88  HOST_EM_CTL = 0x20, /* Enclosure Management Control */
89  HOST_CAP2 = 0x24, /* host capabilities, extended */
90 
91  /* HOST_CTL bits */
92  HOST_RESET = (1 << 0), /* reset controller; self-clear */
93  HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
94  HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
95 
96  /* HOST_CAP bits */
97  HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
98  HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
99  HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
100  HOST_CAP_PART = (1 << 13), /* Partial state capable */
101  HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
102  HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
103  HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
104  HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
105  HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
106  HOST_CAP_CLO = (1 << 24), /* Command List Override support */
107  HOST_CAP_LED = (1 << 25), /* Supports activity LED */
108  HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
109  HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
110  HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
111  HOST_CAP_SNTF = (1 << 29), /* SNotification register */
112  HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
113  HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
114 
115  /* HOST_CAP2 bits */
116  HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
117  HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
118  HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
119  HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
120  HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
121  HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
122 
123  /* registers for each SATA port */
124  PORT_LST_ADDR = 0x00, /* command list DMA addr */
125  PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
126  PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
127  PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
128  PORT_IRQ_STAT = 0x10, /* interrupt status */
129  PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
130  PORT_CMD = 0x18, /* port command */
131  PORT_TFDATA = 0x20, /* taskfile data */
132  PORT_SIG = 0x24, /* device TF signature */
133  PORT_CMD_ISSUE = 0x38, /* command issue */
134  PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
135  PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
136  PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
137  PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
138  PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
139  PORT_FBS = 0x40, /* FIS-based Switching */
140  PORT_DEVSLP = 0x44, /* device sleep */
141 
142  /* PORT_IRQ_{STAT,MASK} bits */
143  PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
144  PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
145  PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
146  PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
147  PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
148  PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
149  PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
150  PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
151 
152  PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
153  PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
154  PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
155  PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
156  PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
157  PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
158  PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
159  PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
160  PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
161 
174 
175  /* PORT_CMD bits */
176  PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
177  PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
178  PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
179  PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
180  PORT_CMD_PMP = (1 << 17), /* PMP attached */
181  PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182  PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183  PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
184  PORT_CMD_CLO = (1 << 3), /* Command list override */
185  PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186  PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187  PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188 
189  PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
190  PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191  PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192  PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
193 
194  /* PORT_FBS bits */
195  PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
196  PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
197  PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
198  PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
199  PORT_FBS_SDE = (1 << 2), /* FBS single device error */
200  PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
201  PORT_FBS_EN = (1 << 0), /* Enable FBS */
202 
203  /* PORT_DEVSLP bits */
204  PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
205  PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
206  PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
207  PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
208  PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
209  PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
210  PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
211 
212  /* hpriv->flags bits */
213 
214 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
215 
216  AHCI_HFLAG_NO_NCQ = (1 << 0),
217  AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
218  AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
219  AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
220  AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
221  AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
222  AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
223  AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
224  AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
225  AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
226  AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
227  link offline */
228  AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
229  AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
230  AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
231  AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
232  port start (wait until
233  error-handling stage) */
234 
235  /* ap->flags bits */
236 
239 
240  ICH_MAP = 0x90, /* ICH MAP register */
241 
242  /* em constants */
245 
246  /* em_ctl bits */
247  EM_CTL_RST = (1 << 9), /* Reset */
248  EM_CTL_TM = (1 << 8), /* Transmit Message */
249  EM_CTL_MR = (1 << 0), /* Message Received */
250  EM_CTL_ALHD = (1 << 26), /* Activity LED */
251  EM_CTL_XMT = (1 << 25), /* Transmit Only */
252  EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
253  EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
254  EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
255  EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
256  EM_CTL_LED = (1 << 16), /* LED messages supported */
257 
258  /* em message type */
259  EM_MSG_TYPE_LED = (1 << 0), /* LED */
260  EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
261  EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
262  EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
263 };
264 
265 struct ahci_cmd_hdr {
271 };
272 
273 struct ahci_sg {
278 };
279 
280 struct ahci_em_priv {
283  unsigned long saved_activity;
284  unsigned long activity;
285  unsigned long led_state;
286 };
287 
292  void *cmd_tbl;
294  void *rx_fis;
296  /* for NCQ spurious interrupt analysis */
297  unsigned int ncq_saw_d2h:1;
298  unsigned int ncq_saw_dmas:1;
299  unsigned int ncq_saw_sdb:1;
300  u32 intr_mask; /* interrupts to enable */
301  bool fbs_supported; /* set iff FBS is supported */
302  bool fbs_enabled; /* set iff FBS is enabled */
303  int fbs_last_dev; /* save FBS.DEV of last FIS */
304  /* enclosure management info per PM slot */
306 };
307 
309  void __iomem * mmio; /* bus-independent mem map */
310  unsigned int flags; /* AHCI_HFLAG_* */
311  u32 cap; /* cap to use */
312  u32 cap2; /* cap2 to use */
313  u32 port_map; /* port map to use */
314  u32 saved_cap; /* saved initial cap */
315  u32 saved_cap2; /* saved initial cap2 */
316  u32 saved_port_map; /* saved initial port_map */
317  u32 em_loc; /* enclosure management location */
318  u32 em_buf_sz; /* EM buffer size in byte */
319  u32 em_msg_type; /* EM message type */
320  struct clk *clk; /* Only for platforms supporting clk */
321 };
322 
323 extern int ahci_ignore_sss;
324 
325 extern struct device_attribute *ahci_shost_attrs[];
326 extern struct device_attribute *ahci_sdev_attrs[];
327 
328 #define AHCI_SHT(drv_name) \
329  ATA_NCQ_SHT(drv_name), \
330  .can_queue = AHCI_MAX_CMDS - 1, \
331  .sg_tablesize = AHCI_MAX_SG, \
332  .dma_boundary = AHCI_DMA_BOUNDARY, \
333  .shost_attrs = ahci_shost_attrs, \
334  .sdev_attrs = ahci_sdev_attrs
335 
336 extern struct ata_port_operations ahci_ops;
338 
339 unsigned int ahci_dev_classify(struct ata_port *ap);
340 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
341  u32 opts);
342 void ahci_save_initial_config(struct device *dev,
343  struct ahci_host_priv *hpriv,
344  unsigned int force_port_map,
345  unsigned int mask_port_map);
346 void ahci_init_controller(struct ata_host *host);
347 int ahci_reset_controller(struct ata_host *host);
348 
349 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
350  int pmp, unsigned long deadline,
351  int (*check_ready)(struct ata_link *link));
352 
353 int ahci_stop_engine(struct ata_port *ap);
354 void ahci_start_engine(struct ata_port *ap);
355 int ahci_check_ready(struct ata_link *link);
356 int ahci_kick_engine(struct ata_port *ap);
357 int ahci_port_resume(struct ata_port *ap);
358 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
359  struct ata_port_info *pi);
360 int ahci_reset_em(struct ata_host *host);
361 irqreturn_t ahci_interrupt(int irq, void *dev_instance);
362 void ahci_print_info(struct ata_host *host, const char *scc_s);
363 
364 static inline void __iomem *__ahci_port_base(struct ata_host *host,
365  unsigned int port_no)
366 {
367  struct ahci_host_priv *hpriv = host->private_data;
368  void __iomem *mmio = hpriv->mmio;
369 
370  return mmio + 0x100 + (port_no * 0x80);
371 }
372 
373 static inline void __iomem *ahci_port_base(struct ata_port *ap)
374 {
375  return __ahci_port_base(ap->host, ap->port_no);
376 }
377 
378 static inline int ahci_nr_ports(u32 cap)
379 {
380  return (cap & 0x1f) + 1;
381 }
382 
383 #endif /* _AHCI_H */