|
| #define | TRUE 1 |
| |
| #define | FALSE 0 |
| |
| #define | ALL_CHANNELS '\0' |
| |
| #define | ALL_TARGETS_MASK 0xFFFF |
| |
| #define | INITIATOR_WILDCARD (~0) |
| |
| #define | SCSIID_TARGET(ahc, scsiid) |
| |
| #define | SCSIID_OUR_ID(scsiid) ((scsiid) & OID) |
| |
| #define | SCSIID_CHANNEL(ahc, scsiid) |
| |
| #define | SCB_IS_SCSIBUS_B(ahc, scb) (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') |
| |
| #define | SCB_GET_OUR_ID(scb) SCSIID_OUR_ID((scb)->hscb->scsiid) |
| |
| #define | SCB_GET_TARGET(ahc, scb) SCSIID_TARGET((ahc), (scb)->hscb->scsiid) |
| |
| #define | SCB_GET_CHANNEL(ahc, scb) SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) |
| |
| #define | SCB_GET_LUN(scb) ((scb)->hscb->lun & LID) |
| |
| #define | SCB_GET_TARGET_OFFSET(ahc, scb) (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) |
| |
| #define | SCB_GET_TARGET_MASK(ahc, scb) (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) |
| |
| #define | SCB_IS_SILENT(scb) (((scb)->flags & SCB_SILENT) != 0) |
| |
| #define | TCL_TARGET_OFFSET(tcl) ((((tcl) >> 4) & TID) >> 4) |
| |
| #define | TCL_LUN(tcl) (tcl & (AHC_NUM_LUNS - 1)) |
| |
| #define | BUILD_TCL(scsiid, lun) ((lun) | (((scsiid) & TID) << 4)) |
| |
| #define | AHC_TMODE_ENABLE 0 |
| |
| #define | AHC_NUM_TARGETS 16 |
| |
| #define | AHC_NUM_LUNS 64 |
| |
| #define | AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ |
| |
| #define | AHC_SCB_MAX 255 |
| |
| #define | AHC_MAX_QUEUE 253 |
| |
| #define | AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) |
| |
| #define | AHC_TMODE_CMDS 256 |
| |
| #define | AHC_BUSRESET_DELAY 25 |
| |
| #define | SG_PTR_MASK 0xFFFFFFF8 |
| |
| #define | AHC_DMA_LAST_SEG 0x80000000 |
| |
| #define | AHC_SG_HIGH_ADDR_MASK 0x7F000000 |
| |
| #define | AHC_SG_LEN_MASK 0x00FFFFFF |
| |
| #define | AHC_TMODE_EVENT_BUFFER_SIZE 8 |
| |
| #define | EVENT_TYPE_BUS_RESET 0xFF |
| |
| #define | AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ |
| |
| #define | AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ |
| |
| #define | AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ |
| |
| #define | AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ |
| |
| #define | AHC_WIDTH_UNKNOWN 0xFF |
| |
| #define | AHC_PERIOD_UNKNOWN 0xFF |
| |
| #define | AHC_OFFSET_UNKNOWN 0xFF |
| |
| #define | AHC_PPR_OPTS_UNKNOWN 0xFF |
| |
| #define | ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ |
| |
| #define | ST_SXFR 0x010 /* Rate Single Transition Only */ |
| |
| #define | DT_SXFR 0x040 /* Rate Double Transition Only */ |
| |
| #define | AHC_ASYNC_XFER_PERIOD 0x45 |
| |
| #define | AHC_ULTRA2_XFER_PERIOD 0x0a |
| |
| #define | AHC_SYNCRATE_DT 0 |
| |
| #define | AHC_SYNCRATE_ULTRA2 1 |
| |
| #define | AHC_SYNCRATE_ULTRA 3 |
| |
| #define | AHC_SYNCRATE_FAST 6 |
| |
| #define | AHC_SYNCRATE_MAX AHC_SYNCRATE_DT |
| |
| #define | AHC_SYNCRATE_MIN 13 |
| |
| #define | CFXFER 0x0007 /* synchronous transfer rate */ |
| |
| #define | CFSYNCH 0x0008 /* enable synchronous transfer */ |
| |
| #define | CFDISC 0x0010 /* enable disconnection */ |
| |
| #define | CFWIDEB 0x0020 /* wide bus device */ |
| |
| #define | CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ |
| |
| #define | CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ |
| |
| #define | CFSTART 0x0100 /* send start unit SCSI command */ |
| |
| #define | CFINCBIOS 0x0200 /* include in BIOS scan */ |
| |
| #define | CFRNFOUND 0x0400 /* report even if not found */ |
| |
| #define | CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ |
| |
| #define | CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ |
| |
| #define | CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ |
| |
| #define | CFSUPREM 0x0001 /* support all removeable drives */ |
| |
| #define | CFSUPREMB 0x0002 /* support removeable boot drives */ |
| |
| #define | CFBIOSEN 0x0004 /* BIOS enabled */ |
| |
| #define | CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ |
| |
| #define | CFSM2DRV 0x0010 /* support more than two drives */ |
| |
| #define | CFSTPWLEVEL 0x0010 /* Termination level control */ |
| |
| #define | CF284XEXTEND 0x0020 /* extended translation (284x cards) */ |
| |
| #define | CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ |
| |
| #define | CFTERM_MENU 0x0040 /* BIOS displays termination menu */ |
| |
| #define | CFEXTEND 0x0080 /* extended translation enabled */ |
| |
| #define | CFSCAMEN 0x0100 /* SCAM enable */ |
| |
| #define | CFMSG_LEVEL 0x0600 /* BIOS Message Level */ |
| |
| #define | CFMSG_VERBOSE 0x0000 |
| |
| #define | CFMSG_SILENT 0x0200 |
| |
| #define | CFMSG_DIAG 0x0400 |
| |
| #define | CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ |
| |
| #define | CFAUTOTERM 0x0001 /* Perform Auto termination */ |
| |
| #define | CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ |
| |
| #define | CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ |
| |
| #define | CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ |
| |
| #define | CFSTERM 0x0004 /* SCSI low byte termination */ |
| |
| #define | CFWSTERM 0x0008 /* SCSI high byte termination */ |
| |
| #define | CFSPARITY 0x0010 /* SCSI parity */ |
| |
| #define | CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ |
| |
| #define | CFMULTILUN 0x0020 |
| |
| #define | CFRESETB 0x0040 /* reset SCSI bus at boot */ |
| |
| #define | CFCLUSTERENB 0x0080 /* Cluster Enable */ |
| |
| #define | CFBOOTCHAN 0x0300 /* probe this channel first */ |
| |
| #define | CFBOOTCHANSHIFT 8 |
| |
| #define | CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ |
| |
| #define | CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ |
| |
| #define | CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ |
| |
| #define | CFENABLEDV 0x4000 /* Perform Domain Validation*/ |
| |
| #define | CFSCSIID 0x000f /* host adapter SCSI ID */ |
| |
| #define | CFBRTIME 0xff00 /* bus release time */ |
| |
| #define | CFMAXTARG 0x00ff /* maximum targets */ |
| |
| #define | CFBOOTLUN 0x0f00 /* Lun to boot from */ |
| |
| #define | CFBOOTID 0xf000 /* Target to boot from */ |
| |
| #define | CFSIGNATURE 0x250 |
| |
| #define | CFSIGNATURE2 0x300 |
| |
| #define | AHC_PCI_TARGET_PERR_THRESH 10 |
| |
| #define | AHC_EISA_SLOT_OFFSET 0xc00 |
| |
| #define | AHC_EISA_IOSIZE 0x100 |
| |
|
| enum | ahc_chip {
AHC_NONE = 0x0000,
AHC_CHIPID_MASK = 0x00FF,
AHC_AIC7770 = 0x0001,
AHC_AIC7850 = 0x0002,
AHC_AIC7855 = 0x0003,
AHC_AIC7859 = 0x0004,
AHC_AIC7860 = 0x0005,
AHC_AIC7870 = 0x0006,
AHC_AIC7880 = 0x0007,
AHC_AIC7895 = 0x0008,
AHC_AIC7895C = 0x0009,
AHC_AIC7890 = 0x000a,
AHC_AIC7896 = 0x000b,
AHC_AIC7892 = 0x000c,
AHC_AIC7899 = 0x000d,
AHC_VL = 0x0100,
AHC_EISA = 0x0200,
AHC_PCI = 0x0400,
AHC_BUS_MASK = 0x0F00,
AHC_NONE = 0x0000,
AHC_CHIPID_MASK = 0x00ff,
AHC_AIC7770 = 0x0001,
AHC_AIC7850 = 0x0002,
AHC_AIC7860 = 0x0003,
AHC_AIC7870 = 0x0004,
AHC_AIC7880 = 0x0005,
AHC_AIC7890 = 0x0006,
AHC_AIC7895 = 0x0007,
AHC_AIC7896 = 0x0008,
AHC_AIC7892 = 0x0009,
AHC_AIC7899 = 0x000a,
AHC_VL = 0x0100,
AHC_EISA = 0x0200,
AHC_PCI = 0x0400
} |
| |
| enum | ahc_feature {
AHC_FENONE = 0x00000,
AHC_ULTRA = 0x00001,
AHC_ULTRA2 = 0x00002,
AHC_WIDE = 0x00004,
AHC_TWIN = 0x00008,
AHC_MORE_SRAM = 0x00010,
AHC_CMD_CHAN = 0x00020,
AHC_QUEUE_REGS = 0x00040,
AHC_SG_PRELOAD = 0x00080,
AHC_SPIOCAP = 0x00100,
AHC_MULTI_TID = 0x00200,
AHC_HS_MAILBOX = 0x00400,
AHC_DT = 0x00800,
AHC_NEW_TERMCTL = 0x01000,
AHC_MULTI_FUNC = 0x02000,
AHC_LARGE_SCBS = 0x04000,
AHC_AUTORATE = 0x08000,
AHC_AUTOPAUSE = 0x10000,
AHC_TARGETMODE = 0x20000,
AHC_MULTIROLE = 0x40000,
AHC_REMOVABLE = 0x80000,
AHC_HVD = 0x100000,
AHC_AIC7770_FE = AHC_FENONE,
AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
AHC_AIC7860_FE = AHC_AIC7850_FE,
AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE,
AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
AHC_AIC7890_FE,
AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
AHC_AIC7895_FE,
AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC,
AHC_FENONE = 0x0000,
AHC_ULTRA = 0x0001,
AHC_ULTRA2 = 0x0002,
AHC_WIDE = 0x0004,
AHC_TWIN = 0x0008,
AHC_MORE_SRAM = 0x0010,
AHC_CMD_CHAN = 0x0020,
AHC_QUEUE_REGS = 0x0040,
AHC_SG_PRELOAD = 0x0080,
AHC_SPIOCAP = 0x0100,
AHC_ULTRA3 = 0x0200,
AHC_NEW_AUTOTERM = 0x0400,
AHC_AIC7770_FE = AHC_FENONE,
AHC_AIC7850_FE = AHC_SPIOCAP,
AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP,
AHC_AIC7870_FE = AHC_FENONE,
AHC_AIC7880_FE = AHC_ULTRA,
AHC_AIC7890_FE,
AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA,
AHC_AIC7896_FE = AHC_AIC7890_FE,
AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_ULTRA3,
AHC_AIC7899_FE = AHC_AIC7890_FE|AHC_ULTRA3
} |
| |
| enum | ahc_bug {
AHC_BUGNONE = 0x00,
AHC_TMODE_WIDEODD_BUG = 0x01,
AHC_AUTOFLUSH_BUG = 0x02,
AHC_CACHETHEN_BUG = 0x04,
AHC_CACHETHEN_DIS_BUG = 0x08,
AHC_PCI_2_1_RETRY_BUG = 0x10,
AHC_PCI_MWI_BUG = 0x20,
AHC_SCBCHAN_UPLOAD_BUG = 0x40
} |
| |
| enum | ahc_flag {
AHC_FNONE = 0x000,
AHC_PRIMARY_CHANNEL = 0x003,
AHC_USEDEFAULTS = 0x004,
AHC_SEQUENCER_DEBUG = 0x008,
AHC_SHARED_SRAM = 0x010,
AHC_LARGE_SEEPROM = 0x020,
AHC_RESET_BUS_A = 0x040,
AHC_RESET_BUS_B = 0x080,
AHC_EXTENDED_TRANS_A = 0x100,
AHC_EXTENDED_TRANS_B = 0x200,
AHC_TERM_ENB_A = 0x400,
AHC_TERM_ENB_B = 0x800,
AHC_INITIATORROLE = 0x1000,
AHC_TARGETROLE = 0x2000,
AHC_NEWEEPROM_FMT = 0x4000,
AHC_TQINFIFO_BLOCKED = 0x10000,
AHC_INT50_SPEEDFLEX = 0x20000,
AHC_SCB_BTT = 0x40000,
AHC_BIOS_ENABLED = 0x80000,
AHC_ALL_INTERRUPTS = 0x100000,
AHC_PAGESCBS = 0x400000,
AHC_EDGE_INTERRUPT = 0x800000,
AHC_39BIT_ADDRESSING = 0x1000000,
AHC_LSCBS_ENABLED = 0x2000000,
AHC_SCB_CONFIG_USED = 0x4000000,
AHC_NO_BIOS_INIT = 0x8000000,
AHC_DISABLE_PCI_PERR = 0x10000000,
AHC_HAS_TERM_LOGIC = 0x20000000
} |
| |
| enum | scb_flag {
SCB_FLAG_NONE = 0x00000,
SCB_TRANSMISSION_ERROR = 0x00001,
SCB_OTHERTCL_TIMEOUT = 0x00002,
SCB_DEVICE_RESET = 0x00004,
SCB_SENSE = 0x00008,
SCB_CDB32_PTR = 0x00010,
SCB_RECOVERY_SCB = 0x00020,
SCB_AUTO_NEGOTIATE = 0x00040,
SCB_NEGOTIATE = 0x00080,
SCB_ABORT = 0x00100,
SCB_ACTIVE = 0x00200,
SCB_TARGET_IMMEDIATE = 0x00400,
SCB_PACKETIZED = 0x00800,
SCB_EXPECT_PPR_BUSFREE = 0x01000,
SCB_PKT_SENSE = 0x02000,
SCB_EXTERNAL_RESET = 0x04000,
SCB_ON_COL_LIST = 0x08000,
SCB_SILENT = 0x10000,
SCB_FREE = 0x0000,
SCB_OTHERTCL_TIMEOUT = 0x0002,
SCB_DEVICE_RESET = 0x0004,
SCB_SENSE = 0x0008,
SCB_CDB32_PTR = 0x0010,
SCB_RECOVERY_SCB = 0x0020,
SCB_AUTO_NEGOTIATE = 0x0040,
SCB_NEGOTIATE = 0x0080,
SCB_ABORT = 0x0100,
SCB_UNTAGGEDQ = 0x0200,
SCB_ACTIVE = 0x0400,
SCB_TARGET_IMMEDIATE = 0x0800,
SCB_TRANSMISSION_ERROR = 0x1000,
SCB_TARGET_SCB = 0x2000,
SCB_SILENT = 0x4000
} |
| |
| enum | ahc_msg_type {
MSG_TYPE_NONE = 0x00,
MSG_TYPE_INITIATOR_MSGOUT = 0x01,
MSG_TYPE_INITIATOR_MSGIN = 0x02,
MSG_TYPE_TARGET_MSGOUT = 0x03,
MSG_TYPE_TARGET_MSGIN = 0x04
} |
| |
| enum | msg_loop_stat {
MSGLOOP_IN_PROG,
MSGLOOP_MSGCOMPLETE,
MSGLOOP_TERMINATED,
MSGLOOP_IN_PROG,
MSGLOOP_MSGCOMPLETE,
MSGLOOP_TERMINATED
} |
| |
| enum | role_t {
ROLE_UNKNOWN,
ROLE_INITIATOR,
ROLE_TARGET,
ROLE_UNKNOWN,
ROLE_INITIATOR,
ROLE_TARGET
} |
| |
| enum | ahc_search_action { SEARCH_COMPLETE,
SEARCH_COUNT,
SEARCH_REMOVE
} |
| |
| enum | ahc_neg_type { AHC_NEG_TO_GOAL,
AHC_NEG_IF_NON_ASYNC,
AHC_NEG_ALWAYS
} |
| |
| enum | ahc_queue_alg { AHC_QUEUE_NONE,
AHC_QUEUE_BASIC,
AHC_QUEUE_TAGGED
} |
| |
|
| | TAILQ_HEAD (scb_tailq, scb) |
| |
| struct ahc_pci_identity * | ahc_find_pci_device (ahc_dev_softc_t) |
| |
| int | ahc_pci_config (struct ahc_softc *, const struct ahc_pci_identity *) |
| |
| int | ahc_pci_test_register_access (struct ahc_softc *) |
| |
| struct aic7770_identity * | aic7770_find_device (uint32_t) |
| |
| int | aic7770_config (struct ahc_softc *ahc, struct aic7770_identity *, u_int port) |
| |
| int | ahc_probe_scbs (struct ahc_softc *) |
| |
| void | ahc_qinfifo_requeue_tail (struct ahc_softc *ahc, struct scb *scb) |
| |
| int | ahc_match_scb (struct ahc_softc *ahc, struct scb *scb, int target, char channel, int lun, u_int tag, role_t role) |
| |
| struct ahc_softc * | ahc_alloc (void *platform_arg, char *name) |
| |
| int | ahc_softc_init (struct ahc_softc *) |
| |
| void | ahc_controller_info (struct ahc_softc *ahc, char *buf) |
| |
| int | ahc_chip_init (struct ahc_softc *ahc) |
| |
| int | ahc_init (struct ahc_softc *ahc) |
| |
| void | ahc_intr_enable (struct ahc_softc *ahc, int enable) |
| |
| void | ahc_pause_and_flushwork (struct ahc_softc *ahc) |
| |
| void | ahc_set_unit (struct ahc_softc *, int) |
| |
| void | ahc_set_name (struct ahc_softc *, char *) |
| |
| void | ahc_free (struct ahc_softc *ahc) |
| |
| int | ahc_reset (struct ahc_softc *ahc, int reinit) |
| |
| int | ahc_search_qinfifo (struct ahc_softc *ahc, int target, char channel, int lun, u_int tag, role_t role, uint32_t status, ahc_search_action action) |
| |
| int | ahc_search_untagged_queues (struct ahc_softc *ahc, ahc_io_ctx_t ctx, int target, char channel, int lun, uint32_t status, ahc_search_action action) |
| |
| int | ahc_search_disc_list (struct ahc_softc *ahc, int target, char channel, int lun, u_int tag, int stop_on_first, int remove, int save_state) |
| |
| int | ahc_reset_channel (struct ahc_softc *ahc, char channel, int initiate_reset) |
| |
| void | ahc_compile_devinfo (struct ahc_devinfo *devinfo, u_int our_id, u_int target, u_int lun, char channel, role_t role) |
| |
| struct ahc_syncrate * | ahc_find_syncrate (struct ahc_softc *ahc, u_int *period, u_int *ppr_options, u_int maxsync) |
| |
| u_int | ahc_find_period (struct ahc_softc *ahc, u_int scsirate, u_int maxsync) |
| |
| int | ahc_update_neg_request (struct ahc_softc *, struct ahc_devinfo *, struct ahc_tmode_tstate *, struct ahc_initiator_tinfo *, ahc_neg_type) |
| |
| void | ahc_set_width (struct ahc_softc *ahc, struct ahc_devinfo *devinfo, u_int width, u_int type, int paused) |
| |
| void | ahc_set_syncrate (struct ahc_softc *ahc, struct ahc_devinfo *devinfo, const struct ahc_syncrate *syncrate, u_int period, u_int offset, u_int ppr_options, u_int type, int paused) |
| |
| void | ahc_print_devinfo (struct ahc_softc *ahc, struct ahc_devinfo *dev) |
| |
| void | ahc_dump_card_state (struct ahc_softc *ahc) |
| |
| int | ahc_print_register (const ahc_reg_parse_entry_t *table, u_int num_entries, const char *name, u_int address, u_int value, u_int *cur_column, u_int wrap_point) |
| |
| int | ahc_acquire_seeprom (struct ahc_softc *ahc, struct seeprom_descriptor *sd) |
| |
| void | ahc_release_seeprom (struct seeprom_descriptor *sd) |
| |
1.8.2