|
| #define | TRUE 1 |
| |
| #define | FALSE 0 |
| |
| #define | ALL_CHANNELS '\0' |
| |
| #define | ALL_TARGETS_MASK 0xFFFF |
| |
| #define | INITIATOR_WILDCARD (~0) |
| |
| #define | SCB_LIST_NULL 0xFF00 |
| |
| #define | SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) |
| |
| #define | QOUTFIFO_ENTRY_VALID 0x80 |
| |
| #define | SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) |
| |
| #define | SCSIID_TARGET(ahd, scsiid) (((scsiid) & TID) >> TID_SHIFT) |
| |
| #define | SCSIID_OUR_ID(scsiid) ((scsiid) & OID) |
| |
| #define | SCSIID_CHANNEL(ahd, scsiid) ('A') |
| |
| #define | SCB_IS_SCSIBUS_B(ahd, scb) (0) |
| |
| #define | SCB_GET_OUR_ID(scb) SCSIID_OUR_ID((scb)->hscb->scsiid) |
| |
| #define | SCB_GET_TARGET(ahd, scb) SCSIID_TARGET((ahd), (scb)->hscb->scsiid) |
| |
| #define | SCB_GET_CHANNEL(ahd, scb) SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) |
| |
| #define | SCB_GET_LUN(scb) ((scb)->hscb->lun) |
| |
| #define | SCB_GET_TARGET_OFFSET(ahd, scb) SCB_GET_TARGET(ahd, scb) |
| |
| #define | SCB_GET_TARGET_MASK(ahd, scb) (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) |
| |
| #define | SCB_IS_SILENT(scb) (((scb)->flags & SCB_SILENT) != 0) |
| |
| #define | TCL_TARGET_OFFSET(tcl) ((((tcl) >> 4) & TID) >> 4) |
| |
| #define | TCL_LUN(tcl) (tcl & (AHD_NUM_LUNS - 1)) |
| |
| #define | BUILD_TCL(scsiid, lun) ((lun) | (((scsiid) & TID) << 4)) |
| |
| #define | BUILD_TCL_RAW(target, channel, lun) ((lun) | ((target) << 8)) |
| |
| #define | SCB_GET_TAG(scb) ahd_le16toh(scb->hscb->tag) |
| |
| #define | AHD_TMODE_ENABLE 0 |
| |
| #define | AHD_BUILD_COL_IDX(target, lun) (((lun) << 4) | target) |
| |
| #define | AHD_GET_SCB_COL_IDX(ahd, scb) ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) |
| |
| #define | AHD_SET_SCB_COL_IDX(scb, col_idx) |
| |
| #define | AHD_COPY_SCB_COL_IDX(dst, src) |
| |
| #define | AHD_NEVER_COL_IDX 0xFFFF |
| |
| #define | AHD_NUM_TARGETS 16 |
| |
| #define | AHD_NUM_LUNS_NONPKT 64 |
| |
| #define | AHD_NUM_LUNS 256 |
| |
| #define | AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ |
| |
| #define | AHD_SCB_MAX 512 |
| |
| #define | AHD_MAX_QUEUE AHD_SCB_MAX |
| |
| #define | AHD_QIN_SIZE AHD_MAX_QUEUE |
| |
| #define | AHD_QOUT_SIZE AHD_MAX_QUEUE |
| |
| #define | AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) |
| |
| #define | AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE |
| |
| #define | AHD_TMODE_CMDS 256 |
| |
| #define | AHD_BUSRESET_DELAY 25 |
| |
| #define | MAX_CDB_LEN 16 |
| |
| #define | MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) |
| |
| #define | SG_PTR_MASK 0xFFFFFFF8 |
| |
| #define | AHD_DMA_LAST_SEG 0x80000000 |
| |
| #define | AHD_SG_HIGH_ADDR_MASK 0x7F000000 |
| |
| #define | AHD_SG_LEN_MASK 0x00FFFFFF |
| |
| #define | pending_links links2.le |
| |
| #define | collision_links links2.le |
| |
| #define | AHD_MAX_LQ_CRC_ERRORS 5 |
| |
| #define | AHD_TMODE_EVENT_BUFFER_SIZE 8 |
| |
| #define | EVENT_TYPE_BUS_RESET 0xFF |
| |
| #define | AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ |
| |
| #define | AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ |
| |
| #define | AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ |
| |
| #define | AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ |
| |
| #define | AHD_PERIOD_10MHz 0x19 |
| |
| #define | AHD_WIDTH_UNKNOWN 0xFF |
| |
| #define | AHD_PERIOD_UNKNOWN 0xFF |
| |
| #define | AHD_OFFSET_UNKNOWN 0xFF |
| |
| #define | AHD_PPR_OPTS_UNKNOWN 0xFF |
| |
| #define | AHD_SYNCRATE_160 0x8 |
| |
| #define | AHD_SYNCRATE_PACED 0x8 |
| |
| #define | AHD_SYNCRATE_DT 0x9 |
| |
| #define | AHD_SYNCRATE_ULTRA2 0xa |
| |
| #define | AHD_SYNCRATE_ULTRA 0xc |
| |
| #define | AHD_SYNCRATE_FAST 0x19 |
| |
| #define | AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST |
| |
| #define | AHD_SYNCRATE_SYNC 0x32 |
| |
| #define | AHD_SYNCRATE_MIN 0x60 |
| |
| #define | AHD_SYNCRATE_ASYNC 0xFF |
| |
| #define | AHD_SYNCRATE_MAX AHD_SYNCRATE_160 |
| |
| #define | AHD_ASYNC_XFER_PERIOD 0x44 |
| |
| #define | AHD_SYNCRATE_REVA_120 0x8 |
| |
| #define | AHD_SYNCRATE_REVA_160 0x7 |
| |
| #define | CFXFER 0x003F /* synchronous transfer rate */ |
| |
| #define | CFXFER_ASYNC 0x3F |
| |
| #define | CFQAS 0x0040 /* Negotiate QAS */ |
| |
| #define | CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ |
| |
| #define | CFSTART 0x0100 /* send start unit SCSI command */ |
| |
| #define | CFINCBIOS 0x0200 /* include in BIOS scan */ |
| |
| #define | CFDISC 0x0400 /* enable disconnection */ |
| |
| #define | CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ |
| |
| #define | CFWIDEB 0x1000 /* wide bus device */ |
| |
| #define | CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ |
| |
| #define | CFSUPREM 0x0001 /* support all removeable drives */ |
| |
| #define | CFSUPREMB 0x0002 /* support removeable boot drives */ |
| |
| #define | CFBIOSSTATE 0x000C /* BIOS Action State */ |
| |
| #define | CFBS_DISABLED 0x00 |
| |
| #define | CFBS_ENABLED 0x04 |
| |
| #define | CFBS_DISABLED_SCAN 0x08 |
| |
| #define | CFENABLEDV 0x0010 /* Perform Domain Validation */ |
| |
| #define | CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ |
| |
| #define | CFSPARITY 0x0040 /* SCSI parity */ |
| |
| #define | CFEXTEND 0x0080 /* extended translation enabled */ |
| |
| #define | CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ |
| |
| #define | CFMSG_LEVEL 0x0600 /* BIOS Message Level */ |
| |
| #define | CFMSG_VERBOSE 0x0000 |
| |
| #define | CFMSG_SILENT 0x0200 |
| |
| #define | CFMSG_DIAG 0x0400 |
| |
| #define | CFRESETB 0x0800 /* reset SCSI bus at boot */ |
| |
| #define | CFAUTOTERM 0x0001 /* Perform Auto termination */ |
| |
| #define | CFSTERM 0x0002 /* SCSI low byte termination */ |
| |
| #define | CFWSTERM 0x0004 /* SCSI high byte termination */ |
| |
| #define | CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ |
| |
| #define | CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ |
| |
| #define | CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ |
| |
| #define | CFSTPWLEVEL 0x0040 /* Termination level control */ |
| |
| #define | CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ |
| |
| #define | CFTERM_MENU 0x0100 /* BIOS displays termination menu */ |
| |
| #define | CFCLUSTERENB 0x8000 /* Cluster Enable */ |
| |
| #define | CFSCSIID 0x000f /* host adapter SCSI ID */ |
| |
| #define | CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ |
| |
| #define | CFMAXTARG 0x00ff /* maximum targets */ |
| |
| #define | CFBOOTLUN 0x0f00 /* Lun to boot from */ |
| |
| #define | CFBOOTID 0xf000 /* Target to boot from */ |
| |
| #define | CFSIGNATURE 0x400 |
| |
| #define | VPDMASTERBIOS 0x0001 |
| |
| #define | VPDBOOTHOST 0x0002 |
| |
| #define | FLXADDR_TERMCTL 0x0 |
| |
| #define | FLX_TERMCTL_ENSECHIGH 0x8 |
| |
| #define | FLX_TERMCTL_ENSECLOW 0x4 |
| |
| #define | FLX_TERMCTL_ENPRIHIGH 0x2 |
| |
| #define | FLX_TERMCTL_ENPRILOW 0x1 |
| |
| #define | FLXADDR_ROMSTAT_CURSENSECTL 0x1 |
| |
| #define | FLX_ROMSTAT_SEECFG 0xF0 |
| |
| #define | FLX_ROMSTAT_EECFG 0x0F |
| |
| #define | FLX_ROMSTAT_SEE_93C66 0x00 |
| |
| #define | FLX_ROMSTAT_SEE_NONE 0xF0 |
| |
| #define | FLX_ROMSTAT_EE_512x8 0x0 |
| |
| #define | FLX_ROMSTAT_EE_1MBx8 0x1 |
| |
| #define | FLX_ROMSTAT_EE_2MBx8 0x2 |
| |
| #define | FLX_ROMSTAT_EE_4MBx8 0x3 |
| |
| #define | FLX_ROMSTAT_EE_16MBx8 0x4 |
| |
| #define | CURSENSE_ENB 0x1 |
| |
| #define | FLXADDR_FLEXSTAT 0x2 |
| |
| #define | FLX_FSTAT_BUSY 0x1 |
| |
| #define | FLXADDR_CURRENT_STAT 0x4 |
| |
| #define | FLX_CSTAT_SEC_HIGH 0xC0 |
| |
| #define | FLX_CSTAT_SEC_LOW 0x30 |
| |
| #define | FLX_CSTAT_PRI_HIGH 0x0C |
| |
| #define | FLX_CSTAT_PRI_LOW 0x03 |
| |
| #define | FLX_CSTAT_MASK 0x03 |
| |
| #define | FLX_CSTAT_SHIFT 2 |
| |
| #define | FLX_CSTAT_OKAY 0x0 |
| |
| #define | FLX_CSTAT_OVER 0x1 |
| |
| #define | FLX_CSTAT_UNDER 0x2 |
| |
| #define | FLX_CSTAT_INVALID 0x3 |
| |
| #define | AHD_MK_MSK(x) (0x01 << (x)) |
| |
| #define | AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) |
| |
| #define | AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) |
| |
| #define | AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) |
| |
| #define | AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) |
| |
| #define | AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) |
| |
| #define | AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) |
| |
| #define | AHD_MODE_ANY_MSK (~0) |
| |
| #define | AHD_STAT_UPDATE_US 250000 /* 250ms */ |
| |
| #define | AHD_STAT_BUCKETS 4 |
| |
| #define | AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ |
| |
| #define | AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 |
| |
| #define | AHD_INT_COALESCING_MAXCMDS_MAX 127 |
| |
| #define | AHD_INT_COALESCING_MINCMDS_DEFAULT 5 |
| |
| #define | AHD_INT_COALESCING_MINCMDS_MAX 127 |
| |
| #define | AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 |
| |
| #define | AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 |
| |
| #define | AHD_PRECOMP_SLEW_INDEX (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) |
| |
| #define | AHD_AMPLITUDE_INDEX (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) |
| |
| #define | AHD_SET_SLEWRATE(ahd, new_slew) |
| |
| #define | AHD_SET_PRECOMP(ahd, new_pcomp) |
| |
| #define | AHD_SET_AMPLITUDE(ahd, new_amp) |
| |
| #define | AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ |
| |
| #define | AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ |
| |
| #define | AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ |
| |
| #define | AHD_EISA_SLOT_OFFSET 0xc00 |
| |
| #define | AHD_EISA_IOSIZE 0x100 |
| |
|
| enum | ahd_chip {
AHD_NONE = 0x0000,
AHD_CHIPID_MASK = 0x00FF,
AHD_AIC7901 = 0x0001,
AHD_AIC7902 = 0x0002,
AHD_AIC7901A = 0x0003,
AHD_PCI = 0x0100,
AHD_PCIX = 0x0200,
AHD_BUS_MASK = 0x0F00
} |
| |
| enum | ahd_feature {
AHD_FENONE = 0x00000,
AHD_WIDE = 0x00001,
AHD_AIC79XXB_SLOWCRC = 0x00002,
AHD_MULTI_FUNC = 0x00100,
AHD_TARGETMODE = 0x01000,
AHD_MULTIROLE = 0x02000,
AHD_RTI = 0x04000,
AHD_NEW_IOCELL_OPTS = 0x08000,
AHD_NEW_DFCNTRL_OPTS = 0x10000,
AHD_FAST_CDB_DELIVERY = 0x20000,
AHD_REMOVABLE = 0x00000,
AHD_AIC7901_FE = AHD_FENONE,
AHD_AIC7901A_FE = AHD_FENONE,
AHD_AIC7902_FE = AHD_MULTI_FUNC
} |
| |
| enum | ahd_bug {
AHD_BUGNONE = 0x0000,
AHD_SENT_SCB_UPDATE_BUG = 0x0001,
AHD_ABORT_LQI_BUG = 0x0002,
AHD_PKT_BITBUCKET_BUG = 0x0004,
AHD_LONG_SETIMO_BUG = 0x0008,
AHD_NLQICRC_DELAYED_BUG = 0x0010,
AHD_SCSIRST_BUG = 0x0020,
AHD_PCIX_CHIPRST_BUG = 0x0040,
AHD_PCIX_MMAPIO_BUG = 0x0080,
AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
AHD_PCIX_BUG_MASK,
AHD_LQO_ATNO_BUG = 0x0200,
AHD_AUTOFLUSH_BUG = 0x0400,
AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
AHD_PKTIZED_STATUS_BUG = 0x1000,
AHD_PKT_LUN_BUG = 0x2000,
AHD_NONPACKFIFO_BUG = 0x4000,
AHD_MDFF_WSCBPTR_BUG = 0x8000,
AHD_REG_SLOW_SETTLE_BUG = 0x10000,
AHD_SET_MODE_BUG = 0x20000,
AHD_BUSFREEREV_BUG = 0x40000,
AHD_PACED_NEGTABLE_BUG = 0x80000,
AHD_LQOOVERRUN_BUG = 0x100000,
AHD_INTCOLLISION_BUG = 0x200000,
AHD_EARLY_REQ_BUG = 0x400000,
AHD_FAINT_LED_BUG = 0x800000
} |
| |
| enum | ahd_flag {
AHD_FNONE = 0x00000,
AHD_BOOT_CHANNEL = 0x00001,
AHD_USEDEFAULTS = 0x00004,
AHD_SEQUENCER_DEBUG = 0x00008,
AHD_RESET_BUS_A = 0x00010,
AHD_EXTENDED_TRANS_A = 0x00020,
AHD_TERM_ENB_A = 0x00040,
AHD_SPCHK_ENB_A = 0x00080,
AHD_STPWLEVEL_A = 0x00100,
AHD_INITIATORROLE = 0x00200,
AHD_TARGETROLE = 0x00400,
AHD_RESOURCE_SHORTAGE = 0x00800,
AHD_TQINFIFO_BLOCKED = 0x01000,
AHD_INT50_SPEEDFLEX = 0x02000,
AHD_BIOS_ENABLED = 0x04000,
AHD_ALL_INTERRUPTS = 0x08000,
AHD_39BIT_ADDRESSING = 0x10000,
AHD_64BIT_ADDRESSING = 0x20000,
AHD_CURRENT_SENSING = 0x40000,
AHD_SCB_CONFIG_USED = 0x80000,
AHD_HP_BOARD = 0x100000,
AHD_BUS_RESET_ACTIVE = 0x200000,
AHD_UPDATE_PEND_CMDS = 0x400000,
AHD_RUNNING_QOUTFIFO = 0x800000,
AHD_HAD_FIRST_SEL = 0x1000000
} |
| |
| enum | scb_flag {
SCB_FLAG_NONE = 0x00000,
SCB_TRANSMISSION_ERROR = 0x00001,
SCB_OTHERTCL_TIMEOUT = 0x00002,
SCB_DEVICE_RESET = 0x00004,
SCB_SENSE = 0x00008,
SCB_CDB32_PTR = 0x00010,
SCB_RECOVERY_SCB = 0x00020,
SCB_AUTO_NEGOTIATE = 0x00040,
SCB_NEGOTIATE = 0x00080,
SCB_ABORT = 0x00100,
SCB_ACTIVE = 0x00200,
SCB_TARGET_IMMEDIATE = 0x00400,
SCB_PACKETIZED = 0x00800,
SCB_EXPECT_PPR_BUSFREE = 0x01000,
SCB_PKT_SENSE = 0x02000,
SCB_EXTERNAL_RESET = 0x04000,
SCB_ON_COL_LIST = 0x08000,
SCB_SILENT = 0x10000,
SCB_FREE = 0x0000,
SCB_OTHERTCL_TIMEOUT = 0x0002,
SCB_DEVICE_RESET = 0x0004,
SCB_SENSE = 0x0008,
SCB_CDB32_PTR = 0x0010,
SCB_RECOVERY_SCB = 0x0020,
SCB_AUTO_NEGOTIATE = 0x0040,
SCB_NEGOTIATE = 0x0080,
SCB_ABORT = 0x0100,
SCB_UNTAGGEDQ = 0x0200,
SCB_ACTIVE = 0x0400,
SCB_TARGET_IMMEDIATE = 0x0800,
SCB_TRANSMISSION_ERROR = 0x1000,
SCB_TARGET_SCB = 0x2000,
SCB_SILENT = 0x4000
} |
| |
| enum | ahd_msg_flags {
MSG_FLAG_NONE = 0x00,
MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
MSG_FLAG_IU_REQ_CHANGED = 0x02,
MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
MSG_FLAG_PACKETIZED = 0x10
} |
| |
| enum | ahd_msg_type {
MSG_TYPE_NONE = 0x00,
MSG_TYPE_INITIATOR_MSGOUT = 0x01,
MSG_TYPE_INITIATOR_MSGIN = 0x02,
MSG_TYPE_TARGET_MSGOUT = 0x03,
MSG_TYPE_TARGET_MSGIN = 0x04
} |
| |
| enum | msg_loop_stat {
MSGLOOP_IN_PROG,
MSGLOOP_MSGCOMPLETE,
MSGLOOP_TERMINATED,
MSGLOOP_IN_PROG,
MSGLOOP_MSGCOMPLETE,
MSGLOOP_TERMINATED
} |
| |
| enum | ahd_mode {
AHD_MODE_DFF0,
AHD_MODE_DFF1,
AHD_MODE_CCHAN,
AHD_MODE_SCSI,
AHD_MODE_CFG,
AHD_MODE_UNKNOWN
} |
| |
| enum | role_t {
ROLE_UNKNOWN,
ROLE_INITIATOR,
ROLE_TARGET,
ROLE_UNKNOWN,
ROLE_INITIATOR,
ROLE_TARGET
} |
| |
| enum | ahd_search_action { SEARCH_COMPLETE,
SEARCH_COUNT,
SEARCH_REMOVE,
SEARCH_PRINT
} |
| |
| enum | ahd_neg_type { AHD_NEG_TO_GOAL,
AHD_NEG_IF_NON_ASYNC,
AHD_NEG_ALWAYS
} |
| |
| enum | ahd_queue_alg { AHD_QUEUE_NONE,
AHD_QUEUE_BASIC,
AHD_QUEUE_TAGGED
} |
| |
|
| | TAILQ_HEAD (scb_tailq, scb) |
| |
| | LIST_HEAD (scb_list, scb) |
| |
| int | ahd_read_seeprom (struct ahd_softc *ahd, uint16_t *buf, u_int start_addr, u_int count, int bstream) |
| |
| int | ahd_write_seeprom (struct ahd_softc *ahd, uint16_t *buf, u_int start_addr, u_int count) |
| |
| int | ahd_verify_cksum (struct seeprom_config *sc) |
| |
| int | ahd_acquire_seeprom (struct ahd_softc *ahd) |
| |
| void | ahd_release_seeprom (struct ahd_softc *ahd) |
| |
| struct ahd_pci_identity * | ahd_find_pci_device (ahd_dev_softc_t) |
| |
| int | ahd_pci_config (struct ahd_softc *, const struct ahd_pci_identity *) |
| |
| int | ahd_pci_test_register_access (struct ahd_softc *) |
| |
| void | ahd_qinfifo_requeue_tail (struct ahd_softc *ahd, struct scb *scb) |
| |
| struct ahd_softc * | ahd_alloc (void *platform_arg, char *name) |
| |
| int | ahd_softc_init (struct ahd_softc *) |
| |
| void | ahd_controller_info (struct ahd_softc *ahd, char *buf) |
| |
| int | ahd_init (struct ahd_softc *ahd) |
| |
| int | ahd_default_config (struct ahd_softc *ahd) |
| |
| int | ahd_parse_vpddata (struct ahd_softc *ahd, struct vpd_config *vpd) |
| |
| int | ahd_parse_cfgdata (struct ahd_softc *ahd, struct seeprom_config *sc) |
| |
| void | ahd_intr_enable (struct ahd_softc *ahd, int enable) |
| |
| void | ahd_pause_and_flushwork (struct ahd_softc *ahd) |
| |
| void | ahd_set_unit (struct ahd_softc *, int) |
| |
| void | ahd_set_name (struct ahd_softc *, char *) |
| |
| struct scb * | ahd_get_scb (struct ahd_softc *ahd, u_int col_idx) |
| |
| void | ahd_free_scb (struct ahd_softc *ahd, struct scb *scb) |
| |
| void | ahd_free (struct ahd_softc *ahd) |
| |
| int | ahd_reset (struct ahd_softc *ahd, int reinit) |
| |
| int | ahd_write_flexport (struct ahd_softc *ahd, u_int addr, u_int value) |
| |
| int | ahd_read_flexport (struct ahd_softc *ahd, u_int addr, uint8_t *value) |
| |
| int | ahd_search_qinfifo (struct ahd_softc *ahd, int target, char channel, int lun, u_int tag, role_t role, uint32_t status, ahd_search_action action) |
| |
| int | ahd_search_disc_list (struct ahd_softc *ahd, int target, char channel, int lun, u_int tag, int stop_on_first, int remove, int save_state) |
| |
| int | ahd_reset_channel (struct ahd_softc *ahd, char channel, int initiate_reset) |
| |
| void | ahd_compile_devinfo (struct ahd_devinfo *devinfo, u_int our_id, u_int target, u_int lun, char channel, role_t role) |
| |
| void | ahd_find_syncrate (struct ahd_softc *ahd, u_int *period, u_int *ppr_options, u_int maxsync) |
| |
| int | ahd_update_neg_request (struct ahd_softc *, struct ahd_devinfo *, struct ahd_tmode_tstate *, struct ahd_initiator_tinfo *, ahd_neg_type) |
| |
| void | ahd_set_width (struct ahd_softc *ahd, struct ahd_devinfo *devinfo, u_int width, u_int type, int paused) |
| |
| void | ahd_set_syncrate (struct ahd_softc *ahd, struct ahd_devinfo *devinfo, u_int period, u_int offset, u_int ppr_options, u_int type, int paused) |
| |
| void | ahd_print_devinfo (struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
| |
| void | ahd_dump_card_state (struct ahd_softc *ahd) |
| |
| int | ahd_print_register (const ahd_reg_parse_entry_t *table, u_int num_entries, const char *name, u_int address, u_int value, u_int *cur_column, u_int wrap_point) |
| |
1.8.2