#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <asm/msr.h>
#include "edac_core.h"
#include "mce_amd.h"

Data Structures
struct	error_injection

struct	reg_pair

struct	dram_range

struct	chip_select

struct	amd64_pvt

struct	ecc_settings

struct	ecc_settings::flags

struct	low_ops

struct	amd64_family_type

Macros
#define	amd64_debug(fmt, arg...) edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)

#define	amd64_info(fmt, arg...) edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define	amd64_notice(fmt, arg...) edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)

#define	amd64_warn(fmt, arg...) edac_printk(KERN_WARNING, "amd64", fmt, ##arg)

#define	amd64_err(fmt, arg...) edac_printk(KERN_ERR, "amd64", fmt, ##arg)

#define	amd64_mc_warn(mci, fmt, arg...) edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define	amd64_mc_err(mci, fmt, arg...) edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

#define	EDAC_AMD64_VERSION "3.4.0"

#define	EDAC_MOD_STR "amd64_edac"

#define	K8_REV_D 1

#define	K8_REV_E 2

#define	K8_REV_F 4

#define	NUM_CHIPSELECTS 8

#define	DRAM_RANGES 8

#define	ON true

#define	OFF false

#define	GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))

#define	PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601

#define	PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602

#define	DRAM_BASE_LO 0x40

#define	DRAM_LIMIT_LO 0x44

#define	dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))

#define	dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))

#define	dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))

#define	dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))

#define	DHAR 0xf0

#define	dhar_valid(pvt) ((pvt)->dhar & BIT(0))

#define	dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))

#define	dhar_base(pvt) ((pvt)->dhar & 0xff000000)

#define	k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)

#define	f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)

#define	DCT_CFG_SEL 0x10C

#define	DRAM_LOCAL_NODE_BASE 0x120

#define	DRAM_LOCAL_NODE_LIM 0x124

#define	DRAM_BASE_HI 0x140

#define	DRAM_LIMIT_HI 0x144

#define	DCSB0 0x40

#define	DCSB1 0x140

#define	DCSB_CS_ENABLE BIT(0)

#define	DCSM0 0x60

#define	DCSM1 0x160

#define	csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)

#define	DBAM0 0x80

#define	DBAM1 0x180

#define	DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)

#define	DBAM_MAX_VALUE 11

#define	DCLR0 0x90

#define	DCLR1 0x190

#define	REVE_WIDTH_128 BIT(16)

#define	WIDTH_128 BIT(11)

#define	DCHR0 0x94

#define	DCHR1 0x194

#define	DDR3_MODE BIT(8)

#define	DCT_SEL_LO 0x110

#define	dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)

#define	dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)

#define	dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))

#define	dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))

#define	dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define	dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))

#define	dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))

#define	SWAP_INTLV_REG 0x10c

#define	DCT_SEL_HI 0x114

#define	NBCTL 0x40

#define	NBCFG 0x44

#define	NBCFG_CHIPKILL BIT(23)

#define	NBCFG_ECC_ENABLE BIT(22)

#define	F10_NBSL_EXT_ERR_ECC 0x8

#define	NBSL_PP_OBS 0x2

#define	SCRCTRL 0x58

#define	F10_ONLINE_SPARE 0xB0

#define	online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)

#define	online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

#define	F10_NB_ARRAY_ADDR 0xB8

#define	F10_NB_ARRAY_DRAM_ECC BIT(31)

#define	SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)

#define	F10_NB_ARRAY_DATA 0xBC

#define	SET_NB_DRAM_INJECTION_WRITE(word, bits)

#define	SET_NB_DRAM_INJECTION_READ(word, bits)

#define	NBCAP 0xE8

#define	NBCAP_CHIPKILL BIT(4)

#define	NBCAP_SECDED BIT(3)

#define	NBCAP_DCT_DUAL BIT(0)

#define	EXT_NB_MCA_CFG 0x180

#define	MSR_MCGCTL_NBE BIT(4)

#define	amd64_read_pci_cfg(pdev, offset, val) __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define	amd64_write_pci_cfg(pdev, offset, val) __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

#define	amd64_read_dct_pci_cfg(pvt, offset, val) pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)

#define	to_mci(k) container_of(k, struct mem_ctl_info, dev)

Enumerations
enum	amd_families { K8_CPUS = 0, F10_CPUS, F15_CPUS, NUM_FAMILIES }

Functions
int	__amd64_write_pci_cfg_dword (struct pci_dev pdev, int offset, u32 val, const char func)

int	amd64_get_dram_hole_info (struct mem_ctl_info mci, u64 hole_base, u64 hole_offset, u64 hole_size)

Macro Definition Documentation

#define amd64_debug	(	fmt,
		arg...
	)	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)

Definition at line 77 of file amd64_edac.h.

#define amd64_err	(	fmt,
		arg...
	)	edac_printk(KERN_ERR, "amd64", fmt, ##arg)

Definition at line 89 of file amd64_edac.h.

#define amd64_info	(	fmt,
		arg...
	)	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

Definition at line 80 of file amd64_edac.h.

#define amd64_mc_err	(	mci,
		fmt,
		arg...
	)	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

Definition at line 95 of file amd64_edac.h.

#define amd64_mc_warn	(	mci,
		fmt,
		arg...
	)	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

Definition at line 92 of file amd64_edac.h.

#define amd64_notice	(	fmt,
		arg...
	)	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)

Definition at line 83 of file amd64_edac.h.

#define amd64_read_dct_pci_cfg	(	pvt,
		offset,
		val
	)	pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)

Definition at line 471 of file amd64_edac.h.

#define amd64_read_pci_cfg	(	pdev,
		offset,
		val
	)	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

Definition at line 465 of file amd64_edac.h.

#define amd64_warn	(	fmt,
		arg...
	)	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)

Definition at line 86 of file amd64_edac.h.

#define amd64_write_pci_cfg	(	pdev,
		offset,
		val
	)	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

Definition at line 468 of file amd64_edac.h.

#define csrow_enabled	(	i,
		dct,
		pvt
	)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)

Definition at line 216 of file amd64_edac.h.

#define DBAM0 0x80

Definition at line 218 of file amd64_edac.h.

#define DBAM1 0x180

Definition at line 219 of file amd64_edac.h.

#define DBAM_DIMM	(	i,
		reg
	)	((((reg) >> (4*i))) & 0xF)

Definition at line 222 of file amd64_edac.h.

#define DBAM_MAX_VALUE 11

Definition at line 224 of file amd64_edac.h.

#define DCHR0 0x94

Definition at line 231 of file amd64_edac.h.

#define DCHR1 0x194

Definition at line 232 of file amd64_edac.h.

#define DCLR0 0x90

Definition at line 226 of file amd64_edac.h.

#define DCLR1 0x190

Definition at line 227 of file amd64_edac.h.

#define DCSB0 0x40

Definition at line 209 of file amd64_edac.h.

#define DCSB1 0x140

Definition at line 210 of file amd64_edac.h.

#define DCSB_CS_ENABLE BIT(0)

Definition at line 211 of file amd64_edac.h.

#define DCSM0 0x60

Definition at line 213 of file amd64_edac.h.

#define DCSM1 0x160

Definition at line 214 of file amd64_edac.h.

#define DCT_CFG_SEL 0x10C

Definition at line 197 of file amd64_edac.h.

#define dct_data_intlv_enabled ( pvt ) ((pvt)->dct_sel_lo & BIT(5))

Definition at line 243 of file amd64_edac.h.

#define dct_ganging_enabled ( pvt ) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

Definition at line 241 of file amd64_edac.h.

#define dct_high_range_enabled ( pvt ) ((pvt)->dct_sel_lo & BIT(0))

Definition at line 238 of file amd64_edac.h.

#define dct_interleave_enabled ( pvt ) ((pvt)->dct_sel_lo & BIT(2))

Definition at line 239 of file amd64_edac.h.

#define dct_memory_cleared ( pvt ) ((pvt)->dct_sel_lo & BIT(10))

Definition at line 244 of file amd64_edac.h.

#define dct_sel_baseaddr ( pvt ) ((pvt)->dct_sel_lo & 0xFFFFF800)

Definition at line 236 of file amd64_edac.h.

#define DCT_SEL_HI 0x114

Definition at line 248 of file amd64_edac.h.

#define dct_sel_interleave_addr ( pvt ) (((pvt)->dct_sel_lo >> 6) & 0x3)

Definition at line 237 of file amd64_edac.h.

#define DCT_SEL_LO 0x110

Definition at line 235 of file amd64_edac.h.

#define DDR3_MODE BIT(8)

Definition at line 233 of file amd64_edac.h.

#define DHAR 0xf0

Definition at line 188 of file amd64_edac.h.

#define dhar_base ( pvt ) ((pvt)->dhar & 0xff000000)

Definition at line 191 of file amd64_edac.h.

#define dhar_mem_hoist_valid ( pvt ) ((pvt)->dhar & BIT(1))

Definition at line 190 of file amd64_edac.h.

#define dhar_valid ( pvt ) ((pvt)->dhar & BIT(0))

Definition at line 189 of file amd64_edac.h.

#define DRAM_BASE_HI 0x140

Definition at line 202 of file amd64_edac.h.

#define DRAM_BASE_LO 0x40

Definition at line 180 of file amd64_edac.h.

#define dram_dst_node	(	pvt,
		i
	)	((u8)(pvt->ranges[i].lim.lo & 0x7))

Definition at line 186 of file amd64_edac.h.

#define dram_intlv_en	(	pvt,
		i
	)	((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))

Definition at line 183 of file amd64_edac.h.

#define dram_intlv_sel	(	pvt,
		i
	)	((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))

Definition at line 185 of file amd64_edac.h.

#define DRAM_LIMIT_HI 0x144

Definition at line 203 of file amd64_edac.h.

#define DRAM_LIMIT_LO 0x44

Definition at line 181 of file amd64_edac.h.

#define DRAM_LOCAL_NODE_BASE 0x120

Definition at line 199 of file amd64_edac.h.

#define DRAM_LOCAL_NODE_LIM 0x124

Definition at line 200 of file amd64_edac.h.

#define DRAM_RANGES 8

Definition at line 157 of file amd64_edac.h.

#define dram_rw	(	pvt,
		i
	)	((u8)(pvt->ranges[i].base.lo & 0x3))

Definition at line 184 of file amd64_edac.h.

#define EDAC_AMD64_VERSION "3.4.0"

Definition at line 147 of file amd64_edac.h.

#define EDAC_MOD_STR "amd64_edac"

Definition at line 148 of file amd64_edac.h.

#define EXT_NB_MCA_CFG 0x180

Definition at line 288 of file amd64_edac.h.

#define f10_dhar_offset ( pvt ) (((pvt)->dhar & 0x0000ff80) << 16)

Definition at line 195 of file amd64_edac.h.

#define F10_NB_ARRAY_ADDR 0xB8

Definition at line 269 of file amd64_edac.h.

#define F10_NB_ARRAY_DATA 0xBC

Definition at line 275 of file amd64_edac.h.

#define F10_NB_ARRAY_DRAM_ECC BIT(31)

Definition at line 270 of file amd64_edac.h.

#define F10_NBSL_EXT_ERR_ECC 0x8

Definition at line 260 of file amd64_edac.h.

#define F10_ONLINE_SPARE 0xB0

Definition at line 265 of file amd64_edac.h.

#define GENMASK	(	lo,
		hi
	)	(((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))

Definition at line 168 of file amd64_edac.h.

#define k8_dhar_offset ( pvt ) (((pvt)->dhar & 0x0000ff00) << 16)

Definition at line 192 of file amd64_edac.h.

#define K8_REV_D 1

Definition at line 151 of file amd64_edac.h.

#define K8_REV_E 2

Definition at line 152 of file amd64_edac.h.

#define K8_REV_F 4

Definition at line 153 of file amd64_edac.h.

#define MSR_MCGCTL_NBE BIT(4)

Definition at line 291 of file amd64_edac.h.

#define NBCAP 0xE8

Definition at line 283 of file amd64_edac.h.

#define NBCAP_CHIPKILL BIT(4)

Definition at line 284 of file amd64_edac.h.

#define NBCAP_DCT_DUAL BIT(0)

Definition at line 286 of file amd64_edac.h.

#define NBCAP_SECDED BIT(3)

Definition at line 285 of file amd64_edac.h.

#define NBCFG 0x44

Definition at line 255 of file amd64_edac.h.

#define NBCFG_CHIPKILL BIT(23)

Definition at line 256 of file amd64_edac.h.

#define NBCFG_ECC_ENABLE BIT(22)

Definition at line 257 of file amd64_edac.h.

#define NBCTL 0x40

Definition at line 253 of file amd64_edac.h.

#define NBSL_PP_OBS 0x2

Definition at line 261 of file amd64_edac.h.

#define NUM_CHIPSELECTS 8

Definition at line 156 of file amd64_edac.h.

#define OFF false

Definition at line 160 of file amd64_edac.h.

#define ON true

Definition at line 159 of file amd64_edac.h.

#define online_spare_bad_dramcs	(	pvt,
		c
	)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)

Definition at line 267 of file amd64_edac.h.

#define online_spare_swap_done	(	pvt,
		c
	)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)

Definition at line 266 of file amd64_edac.h.

#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601

Definition at line 173 of file amd64_edac.h.

#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602

Definition at line 174 of file amd64_edac.h.

#define REVE_WIDTH_128 BIT(16)

Definition at line 228 of file amd64_edac.h.

#define SCRCTRL 0x58

Definition at line 263 of file amd64_edac.h.

#define SET_NB_ARRAY_ADDRESS ( section ) (((section) & 0x3) << 1)

Definition at line 273 of file amd64_edac.h.

#define SET_NB_DRAM_INJECTION_READ	(	word,
		bits
	)

Value:

(BIT(((word) & 0xF) + 20) | \

BIT(16) | bits)

Definition at line 279 of file amd64_edac.h.

#define SET_NB_DRAM_INJECTION_WRITE	(	word,
		bits
	)

Value:

(BIT(((word) & 0xF) + 20) | \

BIT(17) | bits)

Definition at line 276 of file amd64_edac.h.

#define SWAP_INTLV_REG 0x10c

Definition at line 246 of file amd64_edac.h.

#define to_mci ( k ) container_of(k, struct mem_ctl_info, dev)

Definition at line 477 of file amd64_edac.h.

#define WIDTH_128 BIT(11)

Definition at line 229 of file amd64_edac.h.

Enumeration Type Documentation

enum amd_families

Enumerator:

K8_CPUS
F10_CPUS
F15_CPUS
NUM_FAMILIES

Definition at line 299 of file amd64_edac.h.

Function Documentation

int __amd64_write_pci_cfg_dword	(	struct pci_dev *	pdev,
		int	offset,
		u32	val,
		const char *	func
	)

Definition at line 76 of file amd64_edac.c.

int amd64_get_dram_hole_info	(	struct mem_ctl_info *	mci,
		u64 *	hole_base,
		u64 *	hole_offset,
		u64 *	hole_size
	)

Definition at line 422 of file amd64_edac.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation