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ar9003_eeprom.c
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1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
21 
22 #define COMP_HDR_LEN 4
23 #define COMP_CKSUM_LEN 2
24 
25 #define LE16(x) __constant_cpu_to_le16(x)
26 #define LE32(x) __constant_cpu_to_le32(x)
27 
28 /* Local defines to distinguish between extension and control CTL's */
29 #define EXT_ADDITIVE (0x8000)
30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
33 
34 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
35 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
36 
37 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
38 
39 #define EEPROM_DATA_LEN_9485 1088
40 
41 static int ar9003_hw_power_interpolate(int32_t x,
42  int32_t *px, int32_t *py, u_int16_t np);
43 
44 
45 static const struct ar9300_eeprom ar9300_default = {
46  .eepromVersion = 2,
47  .templateVersion = 2,
48  .macAddr = {0, 2, 3, 4, 5, 6},
49  .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50  0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
51  .baseEepHeader = {
52  .regDmn = { LE16(0), LE16(0x1f) },
53  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
54  .opCapFlags = {
55  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
56  .eepMisc = 0,
57  },
58  .rfSilent = 0,
59  .blueToothOptions = 0,
60  .deviceCap = 0,
61  .deviceType = 5, /* takes lower byte in eeprom location */
62  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63  .params_for_tuning_caps = {0, 0},
64  .featureEnable = 0x0c,
65  /*
66  * bit0 - enable tx temp comp - disabled
67  * bit1 - enable tx volt comp - disabled
68  * bit2 - enable fastClock - enabled
69  * bit3 - enable doubling - enabled
70  * bit4 - enable internal regulator - disabled
71  * bit5 - enable pa predistortion - disabled
72  */
73  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74  .eepromWriteEnableGpio = 3,
75  .wlanDisableGpio = 0,
76  .wlanLedGpio = 8,
77  .rxBandSelectGpio = 0xff,
78  .txrxgain = 0,
79  .swreg = 0,
80  },
81  .modalHeader2G = {
82  /* ar9300_modal_eep_header 2g */
83  /* 4 idle,t1,t2,b(4 bits per setting) */
84  .antCtrlCommon = LE32(0x110),
85  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
86  .antCtrlCommon2 = LE32(0x22222),
87 
88  /*
89  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90  * rx1, rx12, b (2 bits each)
91  */
92  .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
93 
94  /*
95  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96  * for ar9280 (0xa20c/b20c 5:0)
97  */
98  .xatten1DB = {0, 0, 0},
99 
100  /*
101  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102  * for ar9280 (0xa20c/b20c 16:12
103  */
104  .xatten1Margin = {0, 0, 0},
105  .tempSlope = 36,
106  .voltSlope = 0,
107 
108  /*
109  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110  * channels in usual fbin coding format
111  */
112  .spurChans = {0, 0, 0, 0, 0},
113 
114  /*
115  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116  * if the register is per chain
117  */
118  .noiseFloorThreshCh = {-1, 0, 0},
119  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
120  .quick_drop = 0,
121  .xpaBiasLvl = 0,
122  .txFrameToDataStart = 0x0e,
123  .txFrameToPaOn = 0x0e,
124  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
125  .antennaGain = 0,
126  .switchSettling = 0x2c,
127  .adcDesiredSize = -30,
128  .txEndToXpaOff = 0,
129  .txEndToRxOn = 0x2,
130  .txFrameToXpaOn = 0xe,
131  .thresh62 = 28,
132  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
134  .xlna_bias_strength = 0,
135  .futureModal = {
136  0, 0, 0, 0, 0, 0, 0,
137  },
138  },
139  .base_ext1 = {
140  .ant_div_control = 0,
141  .future = {0, 0, 0},
142  .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
143  },
144  .calFreqPier2G = {
145  FREQ2FBIN(2412, 1),
146  FREQ2FBIN(2437, 1),
147  FREQ2FBIN(2472, 1),
148  },
149  /* ar9300_cal_data_per_freq_op_loop 2g */
150  .calPierData2G = {
151  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
152  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
153  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
154  },
155  .calTarget_freqbin_Cck = {
156  FREQ2FBIN(2412, 1),
157  FREQ2FBIN(2484, 1),
158  },
159  .calTarget_freqbin_2G = {
160  FREQ2FBIN(2412, 1),
161  FREQ2FBIN(2437, 1),
162  FREQ2FBIN(2472, 1)
163  },
164  .calTarget_freqbin_2GHT20 = {
165  FREQ2FBIN(2412, 1),
166  FREQ2FBIN(2437, 1),
167  FREQ2FBIN(2472, 1)
168  },
169  .calTarget_freqbin_2GHT40 = {
170  FREQ2FBIN(2412, 1),
171  FREQ2FBIN(2437, 1),
172  FREQ2FBIN(2472, 1)
173  },
174  .calTargetPowerCck = {
175  /* 1L-5L,5S,11L,11S */
176  { {36, 36, 36, 36} },
177  { {36, 36, 36, 36} },
178  },
179  .calTargetPower2G = {
180  /* 6-24,36,48,54 */
181  { {32, 32, 28, 24} },
182  { {32, 32, 28, 24} },
183  { {32, 32, 28, 24} },
184  },
185  .calTargetPower2GHT20 = {
186  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
187  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
188  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
189  },
190  .calTargetPower2GHT40 = {
191  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
192  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
193  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
194  },
195  .ctlIndex_2G = {
196  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
197  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
198  },
199  .ctl_freqbin_2G = {
200  {
201  FREQ2FBIN(2412, 1),
202  FREQ2FBIN(2417, 1),
203  FREQ2FBIN(2457, 1),
204  FREQ2FBIN(2462, 1)
205  },
206  {
207  FREQ2FBIN(2412, 1),
208  FREQ2FBIN(2417, 1),
209  FREQ2FBIN(2462, 1),
210  0xFF,
211  },
212 
213  {
214  FREQ2FBIN(2412, 1),
215  FREQ2FBIN(2417, 1),
216  FREQ2FBIN(2462, 1),
217  0xFF,
218  },
219  {
220  FREQ2FBIN(2422, 1),
221  FREQ2FBIN(2427, 1),
222  FREQ2FBIN(2447, 1),
223  FREQ2FBIN(2452, 1)
224  },
225 
226  {
227  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
228  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
229  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
230  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
231  },
232 
233  {
234  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
235  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
236  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
237  0,
238  },
239 
240  {
241  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
242  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
243  FREQ2FBIN(2472, 1),
244  0,
245  },
246 
247  {
248  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
249  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
250  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
251  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
252  },
253 
254  {
255  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
256  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
257  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
258  },
259 
260  {
261  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
262  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
263  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
264  0
265  },
266 
267  {
268  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
269  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
270  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
271  0
272  },
273 
274  {
275  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
276  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
277  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
278  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
279  }
280  },
281  .ctlPowerData_2G = {
282  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
283  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
284  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
285 
286  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
287  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
288  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
289 
290  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
291  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
292  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 
294  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
295  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
296  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
297  },
298  .modalHeader5G = {
299  /* 4 idle,t1,t2,b (4 bits per setting) */
300  .antCtrlCommon = LE32(0x110),
301  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
302  .antCtrlCommon2 = LE32(0x22222),
303  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
304  .antCtrlChain = {
305  LE16(0x000), LE16(0x000), LE16(0x000),
306  },
307  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
308  .xatten1DB = {0, 0, 0},
309 
310  /*
311  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
312  * for merlin (0xa20c/b20c 16:12
313  */
314  .xatten1Margin = {0, 0, 0},
315  .tempSlope = 68,
316  .voltSlope = 0,
317  /* spurChans spur channels in usual fbin coding format */
318  .spurChans = {0, 0, 0, 0, 0},
319  /* noiseFloorThreshCh Check if the register is per chain */
320  .noiseFloorThreshCh = {-1, 0, 0},
321  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
322  .quick_drop = 0,
323  .xpaBiasLvl = 0,
324  .txFrameToDataStart = 0x0e,
325  .txFrameToPaOn = 0x0e,
326  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
327  .antennaGain = 0,
328  .switchSettling = 0x2d,
329  .adcDesiredSize = -30,
330  .txEndToXpaOff = 0,
331  .txEndToRxOn = 0x2,
332  .txFrameToXpaOn = 0xe,
333  .thresh62 = 28,
334  .papdRateMaskHt20 = LE32(0x0c80c080),
335  .papdRateMaskHt40 = LE32(0x0080c080),
336  .xlna_bias_strength = 0,
337  .futureModal = {
338  0, 0, 0, 0, 0, 0, 0,
339  },
340  },
341  .base_ext2 = {
342  .tempSlopeLow = 0,
343  .tempSlopeHigh = 0,
344  .xatten1DBLow = {0, 0, 0},
345  .xatten1MarginLow = {0, 0, 0},
346  .xatten1DBHigh = {0, 0, 0},
347  .xatten1MarginHigh = {0, 0, 0}
348  },
349  .calFreqPier5G = {
350  FREQ2FBIN(5180, 0),
351  FREQ2FBIN(5220, 0),
352  FREQ2FBIN(5320, 0),
353  FREQ2FBIN(5400, 0),
354  FREQ2FBIN(5500, 0),
355  FREQ2FBIN(5600, 0),
356  FREQ2FBIN(5725, 0),
357  FREQ2FBIN(5825, 0)
358  },
359  .calPierData5G = {
360  {
361  {0, 0, 0, 0, 0},
362  {0, 0, 0, 0, 0},
363  {0, 0, 0, 0, 0},
364  {0, 0, 0, 0, 0},
365  {0, 0, 0, 0, 0},
366  {0, 0, 0, 0, 0},
367  {0, 0, 0, 0, 0},
368  {0, 0, 0, 0, 0},
369  },
370  {
371  {0, 0, 0, 0, 0},
372  {0, 0, 0, 0, 0},
373  {0, 0, 0, 0, 0},
374  {0, 0, 0, 0, 0},
375  {0, 0, 0, 0, 0},
376  {0, 0, 0, 0, 0},
377  {0, 0, 0, 0, 0},
378  {0, 0, 0, 0, 0},
379  },
380  {
381  {0, 0, 0, 0, 0},
382  {0, 0, 0, 0, 0},
383  {0, 0, 0, 0, 0},
384  {0, 0, 0, 0, 0},
385  {0, 0, 0, 0, 0},
386  {0, 0, 0, 0, 0},
387  {0, 0, 0, 0, 0},
388  {0, 0, 0, 0, 0},
389  },
390 
391  },
392  .calTarget_freqbin_5G = {
393  FREQ2FBIN(5180, 0),
394  FREQ2FBIN(5220, 0),
395  FREQ2FBIN(5320, 0),
396  FREQ2FBIN(5400, 0),
397  FREQ2FBIN(5500, 0),
398  FREQ2FBIN(5600, 0),
399  FREQ2FBIN(5725, 0),
400  FREQ2FBIN(5825, 0)
401  },
402  .calTarget_freqbin_5GHT20 = {
403  FREQ2FBIN(5180, 0),
404  FREQ2FBIN(5240, 0),
405  FREQ2FBIN(5320, 0),
406  FREQ2FBIN(5500, 0),
407  FREQ2FBIN(5700, 0),
408  FREQ2FBIN(5745, 0),
409  FREQ2FBIN(5725, 0),
410  FREQ2FBIN(5825, 0)
411  },
412  .calTarget_freqbin_5GHT40 = {
413  FREQ2FBIN(5180, 0),
414  FREQ2FBIN(5240, 0),
415  FREQ2FBIN(5320, 0),
416  FREQ2FBIN(5500, 0),
417  FREQ2FBIN(5700, 0),
418  FREQ2FBIN(5745, 0),
419  FREQ2FBIN(5725, 0),
420  FREQ2FBIN(5825, 0)
421  },
422  .calTargetPower5G = {
423  /* 6-24,36,48,54 */
424  { {20, 20, 20, 10} },
425  { {20, 20, 20, 10} },
426  { {20, 20, 20, 10} },
427  { {20, 20, 20, 10} },
428  { {20, 20, 20, 10} },
429  { {20, 20, 20, 10} },
430  { {20, 20, 20, 10} },
431  { {20, 20, 20, 10} },
432  },
433  .calTargetPower5GHT20 = {
434  /*
435  * 0_8_16,1-3_9-11_17-19,
436  * 4,5,6,7,12,13,14,15,20,21,22,23
437  */
438  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
443  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
444  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
445  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
446  },
447  .calTargetPower5GHT40 = {
448  /*
449  * 0_8_16,1-3_9-11_17-19,
450  * 4,5,6,7,12,13,14,15,20,21,22,23
451  */
452  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460  },
461  .ctlIndex_5G = {
462  0x10, 0x16, 0x18, 0x40, 0x46,
463  0x48, 0x30, 0x36, 0x38
464  },
465  .ctl_freqbin_5G = {
466  {
467  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
468  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
469  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
470  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
471  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
472  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
473  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
474  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
475  },
476  {
477  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
478  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
479  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
480  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
481  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
482  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
483  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
484  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
485  },
486 
487  {
488  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
489  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
490  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
491  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
492  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
493  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
494  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
495  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
496  },
497 
498  {
499  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
500  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
501  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
502  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
503  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
504  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
505  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
506  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
507  },
508 
509  {
510  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
511  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
512  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
513  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
514  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
515  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
516  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
517  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
518  },
519 
520  {
521  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
522  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
523  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
524  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
525  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
526  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
527  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
528  /* Data[5].ctlEdges[7].bChannel */ 0xFF
529  },
530 
531  {
532  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
533  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
534  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
535  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
536  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
537  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
538  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
539  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
540  },
541 
542  {
543  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
544  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
545  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
546  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
547  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
548  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
549  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
550  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
551  },
552 
553  {
554  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
555  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
556  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
557  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
558  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
559  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
560  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
561  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
562  }
563  },
564  .ctlPowerData_5G = {
565  {
566  {
567  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
568  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
569  }
570  },
571  {
572  {
573  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
574  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
575  }
576  },
577  {
578  {
579  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
580  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
581  }
582  },
583  {
584  {
585  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
586  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
587  }
588  },
589  {
590  {
591  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
592  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
593  }
594  },
595  {
596  {
597  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
598  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
599  }
600  },
601  {
602  {
603  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
604  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
605  }
606  },
607  {
608  {
609  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
610  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
611  }
612  },
613  {
614  {
615  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
616  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
617  }
618  },
619  }
620 };
621 
622 static const struct ar9300_eeprom ar9300_x113 = {
623  .eepromVersion = 2,
624  .templateVersion = 6,
625  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
626  .custData = {"x113-023-f0000"},
627  .baseEepHeader = {
628  .regDmn = { LE16(0), LE16(0x1f) },
629  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
630  .opCapFlags = {
631  .opFlags = AR5416_OPFLAGS_11A,
632  .eepMisc = 0,
633  },
634  .rfSilent = 0,
635  .blueToothOptions = 0,
636  .deviceCap = 0,
637  .deviceType = 5, /* takes lower byte in eeprom location */
638  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
639  .params_for_tuning_caps = {0, 0},
640  .featureEnable = 0x0d,
641  /*
642  * bit0 - enable tx temp comp - disabled
643  * bit1 - enable tx volt comp - disabled
644  * bit2 - enable fastClock - enabled
645  * bit3 - enable doubling - enabled
646  * bit4 - enable internal regulator - disabled
647  * bit5 - enable pa predistortion - disabled
648  */
649  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
650  .eepromWriteEnableGpio = 6,
651  .wlanDisableGpio = 0,
652  .wlanLedGpio = 8,
653  .rxBandSelectGpio = 0xff,
654  .txrxgain = 0x21,
655  .swreg = 0,
656  },
657  .modalHeader2G = {
658  /* ar9300_modal_eep_header 2g */
659  /* 4 idle,t1,t2,b(4 bits per setting) */
660  .antCtrlCommon = LE32(0x110),
661  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
662  .antCtrlCommon2 = LE32(0x44444),
663 
664  /*
665  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
666  * rx1, rx12, b (2 bits each)
667  */
668  .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
669 
670  /*
671  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
672  * for ar9280 (0xa20c/b20c 5:0)
673  */
674  .xatten1DB = {0, 0, 0},
675 
676  /*
677  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
678  * for ar9280 (0xa20c/b20c 16:12
679  */
680  .xatten1Margin = {0, 0, 0},
681  .tempSlope = 25,
682  .voltSlope = 0,
683 
684  /*
685  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
686  * channels in usual fbin coding format
687  */
688  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
689 
690  /*
691  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
692  * if the register is per chain
693  */
694  .noiseFloorThreshCh = {-1, 0, 0},
695  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
696  .quick_drop = 0,
697  .xpaBiasLvl = 0,
698  .txFrameToDataStart = 0x0e,
699  .txFrameToPaOn = 0x0e,
700  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
701  .antennaGain = 0,
702  .switchSettling = 0x2c,
703  .adcDesiredSize = -30,
704  .txEndToXpaOff = 0,
705  .txEndToRxOn = 0x2,
706  .txFrameToXpaOn = 0xe,
707  .thresh62 = 28,
708  .papdRateMaskHt20 = LE32(0x0c80c080),
709  .papdRateMaskHt40 = LE32(0x0080c080),
710  .xlna_bias_strength = 0,
711  .futureModal = {
712  0, 0, 0, 0, 0, 0, 0,
713  },
714  },
715  .base_ext1 = {
716  .ant_div_control = 0,
717  .future = {0, 0, 0},
718  .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
719  },
720  .calFreqPier2G = {
721  FREQ2FBIN(2412, 1),
722  FREQ2FBIN(2437, 1),
723  FREQ2FBIN(2472, 1),
724  },
725  /* ar9300_cal_data_per_freq_op_loop 2g */
726  .calPierData2G = {
727  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
728  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
729  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
730  },
731  .calTarget_freqbin_Cck = {
732  FREQ2FBIN(2412, 1),
733  FREQ2FBIN(2472, 1),
734  },
735  .calTarget_freqbin_2G = {
736  FREQ2FBIN(2412, 1),
737  FREQ2FBIN(2437, 1),
738  FREQ2FBIN(2472, 1)
739  },
740  .calTarget_freqbin_2GHT20 = {
741  FREQ2FBIN(2412, 1),
742  FREQ2FBIN(2437, 1),
743  FREQ2FBIN(2472, 1)
744  },
745  .calTarget_freqbin_2GHT40 = {
746  FREQ2FBIN(2412, 1),
747  FREQ2FBIN(2437, 1),
748  FREQ2FBIN(2472, 1)
749  },
750  .calTargetPowerCck = {
751  /* 1L-5L,5S,11L,11S */
752  { {34, 34, 34, 34} },
753  { {34, 34, 34, 34} },
754  },
755  .calTargetPower2G = {
756  /* 6-24,36,48,54 */
757  { {34, 34, 32, 32} },
758  { {34, 34, 32, 32} },
759  { {34, 34, 32, 32} },
760  },
761  .calTargetPower2GHT20 = {
762  { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
763  { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
764  { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
765  },
766  .calTargetPower2GHT40 = {
767  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
768  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
769  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
770  },
771  .ctlIndex_2G = {
772  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
773  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
774  },
775  .ctl_freqbin_2G = {
776  {
777  FREQ2FBIN(2412, 1),
778  FREQ2FBIN(2417, 1),
779  FREQ2FBIN(2457, 1),
780  FREQ2FBIN(2462, 1)
781  },
782  {
783  FREQ2FBIN(2412, 1),
784  FREQ2FBIN(2417, 1),
785  FREQ2FBIN(2462, 1),
786  0xFF,
787  },
788 
789  {
790  FREQ2FBIN(2412, 1),
791  FREQ2FBIN(2417, 1),
792  FREQ2FBIN(2462, 1),
793  0xFF,
794  },
795  {
796  FREQ2FBIN(2422, 1),
797  FREQ2FBIN(2427, 1),
798  FREQ2FBIN(2447, 1),
799  FREQ2FBIN(2452, 1)
800  },
801 
802  {
803  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
804  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
805  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
806  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
807  },
808 
809  {
810  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
811  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
812  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
813  0,
814  },
815 
816  {
817  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
818  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
819  FREQ2FBIN(2472, 1),
820  0,
821  },
822 
823  {
824  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
825  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
826  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
827  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
828  },
829 
830  {
831  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
832  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
833  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
834  },
835 
836  {
837  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
838  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
839  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
840  0
841  },
842 
843  {
844  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
845  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
846  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
847  0
848  },
849 
850  {
851  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
852  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
853  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
854  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
855  }
856  },
857  .ctlPowerData_2G = {
858  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
859  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
860  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
861 
862  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
863  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
864  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
865 
866  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
867  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
868  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
869 
870  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
871  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
872  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
873  },
874  .modalHeader5G = {
875  /* 4 idle,t1,t2,b (4 bits per setting) */
876  .antCtrlCommon = LE32(0x220),
877  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
878  .antCtrlCommon2 = LE32(0x11111),
879  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
880  .antCtrlChain = {
881  LE16(0x150), LE16(0x150), LE16(0x150),
882  },
883  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
884  .xatten1DB = {0, 0, 0},
885 
886  /*
887  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
888  * for merlin (0xa20c/b20c 16:12
889  */
890  .xatten1Margin = {0, 0, 0},
891  .tempSlope = 68,
892  .voltSlope = 0,
893  /* spurChans spur channels in usual fbin coding format */
894  .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
895  /* noiseFloorThreshCh Check if the register is per chain */
896  .noiseFloorThreshCh = {-1, 0, 0},
897  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
898  .quick_drop = 0,
899  .xpaBiasLvl = 0xf,
900  .txFrameToDataStart = 0x0e,
901  .txFrameToPaOn = 0x0e,
902  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
903  .antennaGain = 0,
904  .switchSettling = 0x2d,
905  .adcDesiredSize = -30,
906  .txEndToXpaOff = 0,
907  .txEndToRxOn = 0x2,
908  .txFrameToXpaOn = 0xe,
909  .thresh62 = 28,
910  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
911  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
912  .xlna_bias_strength = 0,
913  .futureModal = {
914  0, 0, 0, 0, 0, 0, 0,
915  },
916  },
917  .base_ext2 = {
918  .tempSlopeLow = 72,
919  .tempSlopeHigh = 105,
920  .xatten1DBLow = {0, 0, 0},
921  .xatten1MarginLow = {0, 0, 0},
922  .xatten1DBHigh = {0, 0, 0},
923  .xatten1MarginHigh = {0, 0, 0}
924  },
925  .calFreqPier5G = {
926  FREQ2FBIN(5180, 0),
927  FREQ2FBIN(5240, 0),
928  FREQ2FBIN(5320, 0),
929  FREQ2FBIN(5400, 0),
930  FREQ2FBIN(5500, 0),
931  FREQ2FBIN(5600, 0),
932  FREQ2FBIN(5745, 0),
933  FREQ2FBIN(5785, 0)
934  },
935  .calPierData5G = {
936  {
937  {0, 0, 0, 0, 0},
938  {0, 0, 0, 0, 0},
939  {0, 0, 0, 0, 0},
940  {0, 0, 0, 0, 0},
941  {0, 0, 0, 0, 0},
942  {0, 0, 0, 0, 0},
943  {0, 0, 0, 0, 0},
944  {0, 0, 0, 0, 0},
945  },
946  {
947  {0, 0, 0, 0, 0},
948  {0, 0, 0, 0, 0},
949  {0, 0, 0, 0, 0},
950  {0, 0, 0, 0, 0},
951  {0, 0, 0, 0, 0},
952  {0, 0, 0, 0, 0},
953  {0, 0, 0, 0, 0},
954  {0, 0, 0, 0, 0},
955  },
956  {
957  {0, 0, 0, 0, 0},
958  {0, 0, 0, 0, 0},
959  {0, 0, 0, 0, 0},
960  {0, 0, 0, 0, 0},
961  {0, 0, 0, 0, 0},
962  {0, 0, 0, 0, 0},
963  {0, 0, 0, 0, 0},
964  {0, 0, 0, 0, 0},
965  },
966 
967  },
968  .calTarget_freqbin_5G = {
969  FREQ2FBIN(5180, 0),
970  FREQ2FBIN(5220, 0),
971  FREQ2FBIN(5320, 0),
972  FREQ2FBIN(5400, 0),
973  FREQ2FBIN(5500, 0),
974  FREQ2FBIN(5600, 0),
975  FREQ2FBIN(5745, 0),
976  FREQ2FBIN(5785, 0)
977  },
978  .calTarget_freqbin_5GHT20 = {
979  FREQ2FBIN(5180, 0),
980  FREQ2FBIN(5240, 0),
981  FREQ2FBIN(5320, 0),
982  FREQ2FBIN(5400, 0),
983  FREQ2FBIN(5500, 0),
984  FREQ2FBIN(5700, 0),
985  FREQ2FBIN(5745, 0),
986  FREQ2FBIN(5825, 0)
987  },
988  .calTarget_freqbin_5GHT40 = {
989  FREQ2FBIN(5190, 0),
990  FREQ2FBIN(5230, 0),
991  FREQ2FBIN(5320, 0),
992  FREQ2FBIN(5410, 0),
993  FREQ2FBIN(5510, 0),
994  FREQ2FBIN(5670, 0),
995  FREQ2FBIN(5755, 0),
996  FREQ2FBIN(5825, 0)
997  },
998  .calTargetPower5G = {
999  /* 6-24,36,48,54 */
1000  { {42, 40, 40, 34} },
1001  { {42, 40, 40, 34} },
1002  { {42, 40, 40, 34} },
1003  { {42, 40, 40, 34} },
1004  { {42, 40, 40, 34} },
1005  { {42, 40, 40, 34} },
1006  { {42, 40, 40, 34} },
1007  { {42, 40, 40, 34} },
1008  },
1009  .calTargetPower5GHT20 = {
1010  /*
1011  * 0_8_16,1-3_9-11_17-19,
1012  * 4,5,6,7,12,13,14,15,20,21,22,23
1013  */
1014  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1015  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1016  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1017  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1018  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1019  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1020  { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1021  { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1022  },
1023  .calTargetPower5GHT40 = {
1024  /*
1025  * 0_8_16,1-3_9-11_17-19,
1026  * 4,5,6,7,12,13,14,15,20,21,22,23
1027  */
1028  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1029  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1030  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1031  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1032  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1033  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1034  { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1035  { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1036  },
1037  .ctlIndex_5G = {
1038  0x10, 0x16, 0x18, 0x40, 0x46,
1039  0x48, 0x30, 0x36, 0x38
1040  },
1041  .ctl_freqbin_5G = {
1042  {
1043  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1044  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1045  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1046  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1047  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1048  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1049  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1050  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1051  },
1052  {
1053  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1054  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1055  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1056  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1057  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1058  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1059  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1060  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1061  },
1062 
1063  {
1064  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1065  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1066  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1067  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1068  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1069  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1070  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1071  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1072  },
1073 
1074  {
1075  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1076  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1077  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1078  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1079  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1080  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1081  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1082  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1083  },
1084 
1085  {
1086  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1087  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1088  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1089  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1090  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1091  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1092  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1093  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1094  },
1095 
1096  {
1097  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1098  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1099  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1100  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1101  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1102  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1103  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1104  /* Data[5].ctlEdges[7].bChannel */ 0xFF
1105  },
1106 
1107  {
1108  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1109  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1110  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1111  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1112  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1113  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1114  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1115  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1116  },
1117 
1118  {
1119  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1120  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1121  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1122  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1123  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1124  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1125  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1126  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1127  },
1128 
1129  {
1130  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1131  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1132  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1133  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1134  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1135  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1136  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1137  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1138  }
1139  },
1140  .ctlPowerData_5G = {
1141  {
1142  {
1143  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1145  }
1146  },
1147  {
1148  {
1149  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1150  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1151  }
1152  },
1153  {
1154  {
1155  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1156  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1157  }
1158  },
1159  {
1160  {
1161  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1163  }
1164  },
1165  {
1166  {
1167  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1168  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1169  }
1170  },
1171  {
1172  {
1173  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1175  }
1176  },
1177  {
1178  {
1179  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1180  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1181  }
1182  },
1183  {
1184  {
1185  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1186  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1187  }
1188  },
1189  {
1190  {
1191  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1192  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1193  }
1194  },
1195  }
1196 };
1197 
1198 
1199 static const struct ar9300_eeprom ar9300_h112 = {
1200  .eepromVersion = 2,
1201  .templateVersion = 3,
1202  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1203  .custData = {"h112-241-f0000"},
1204  .baseEepHeader = {
1205  .regDmn = { LE16(0), LE16(0x1f) },
1206  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1207  .opCapFlags = {
1208  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1209  .eepMisc = 0,
1210  },
1211  .rfSilent = 0,
1212  .blueToothOptions = 0,
1213  .deviceCap = 0,
1214  .deviceType = 5, /* takes lower byte in eeprom location */
1215  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1216  .params_for_tuning_caps = {0, 0},
1217  .featureEnable = 0x0d,
1218  /*
1219  * bit0 - enable tx temp comp - disabled
1220  * bit1 - enable tx volt comp - disabled
1221  * bit2 - enable fastClock - enabled
1222  * bit3 - enable doubling - enabled
1223  * bit4 - enable internal regulator - disabled
1224  * bit5 - enable pa predistortion - disabled
1225  */
1226  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1227  .eepromWriteEnableGpio = 6,
1228  .wlanDisableGpio = 0,
1229  .wlanLedGpio = 8,
1230  .rxBandSelectGpio = 0xff,
1231  .txrxgain = 0x10,
1232  .swreg = 0,
1233  },
1234  .modalHeader2G = {
1235  /* ar9300_modal_eep_header 2g */
1236  /* 4 idle,t1,t2,b(4 bits per setting) */
1237  .antCtrlCommon = LE32(0x110),
1238  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1239  .antCtrlCommon2 = LE32(0x44444),
1240 
1241  /*
1242  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1243  * rx1, rx12, b (2 bits each)
1244  */
1245  .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1246 
1247  /*
1248  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1249  * for ar9280 (0xa20c/b20c 5:0)
1250  */
1251  .xatten1DB = {0, 0, 0},
1252 
1253  /*
1254  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1255  * for ar9280 (0xa20c/b20c 16:12
1256  */
1257  .xatten1Margin = {0, 0, 0},
1258  .tempSlope = 25,
1259  .voltSlope = 0,
1260 
1261  /*
1262  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1263  * channels in usual fbin coding format
1264  */
1265  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1266 
1267  /*
1268  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1269  * if the register is per chain
1270  */
1271  .noiseFloorThreshCh = {-1, 0, 0},
1272  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1273  .quick_drop = 0,
1274  .xpaBiasLvl = 0,
1275  .txFrameToDataStart = 0x0e,
1276  .txFrameToPaOn = 0x0e,
1277  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1278  .antennaGain = 0,
1279  .switchSettling = 0x2c,
1280  .adcDesiredSize = -30,
1281  .txEndToXpaOff = 0,
1282  .txEndToRxOn = 0x2,
1283  .txFrameToXpaOn = 0xe,
1284  .thresh62 = 28,
1285  .papdRateMaskHt20 = LE32(0x0c80c080),
1286  .papdRateMaskHt40 = LE32(0x0080c080),
1287  .xlna_bias_strength = 0,
1288  .futureModal = {
1289  0, 0, 0, 0, 0, 0, 0,
1290  },
1291  },
1292  .base_ext1 = {
1293  .ant_div_control = 0,
1294  .future = {0, 0, 0},
1295  .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
1296  },
1297  .calFreqPier2G = {
1298  FREQ2FBIN(2412, 1),
1299  FREQ2FBIN(2437, 1),
1300  FREQ2FBIN(2462, 1),
1301  },
1302  /* ar9300_cal_data_per_freq_op_loop 2g */
1303  .calPierData2G = {
1304  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1305  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1306  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1307  },
1308  .calTarget_freqbin_Cck = {
1309  FREQ2FBIN(2412, 1),
1310  FREQ2FBIN(2472, 1),
1311  },
1312  .calTarget_freqbin_2G = {
1313  FREQ2FBIN(2412, 1),
1314  FREQ2FBIN(2437, 1),
1315  FREQ2FBIN(2472, 1)
1316  },
1317  .calTarget_freqbin_2GHT20 = {
1318  FREQ2FBIN(2412, 1),
1319  FREQ2FBIN(2437, 1),
1320  FREQ2FBIN(2472, 1)
1321  },
1322  .calTarget_freqbin_2GHT40 = {
1323  FREQ2FBIN(2412, 1),
1324  FREQ2FBIN(2437, 1),
1325  FREQ2FBIN(2472, 1)
1326  },
1327  .calTargetPowerCck = {
1328  /* 1L-5L,5S,11L,11S */
1329  { {34, 34, 34, 34} },
1330  { {34, 34, 34, 34} },
1331  },
1332  .calTargetPower2G = {
1333  /* 6-24,36,48,54 */
1334  { {34, 34, 32, 32} },
1335  { {34, 34, 32, 32} },
1336  { {34, 34, 32, 32} },
1337  },
1338  .calTargetPower2GHT20 = {
1339  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1340  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1341  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1342  },
1343  .calTargetPower2GHT40 = {
1344  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1345  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1346  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1347  },
1348  .ctlIndex_2G = {
1349  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1350  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1351  },
1352  .ctl_freqbin_2G = {
1353  {
1354  FREQ2FBIN(2412, 1),
1355  FREQ2FBIN(2417, 1),
1356  FREQ2FBIN(2457, 1),
1357  FREQ2FBIN(2462, 1)
1358  },
1359  {
1360  FREQ2FBIN(2412, 1),
1361  FREQ2FBIN(2417, 1),
1362  FREQ2FBIN(2462, 1),
1363  0xFF,
1364  },
1365 
1366  {
1367  FREQ2FBIN(2412, 1),
1368  FREQ2FBIN(2417, 1),
1369  FREQ2FBIN(2462, 1),
1370  0xFF,
1371  },
1372  {
1373  FREQ2FBIN(2422, 1),
1374  FREQ2FBIN(2427, 1),
1375  FREQ2FBIN(2447, 1),
1376  FREQ2FBIN(2452, 1)
1377  },
1378 
1379  {
1380  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1381  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1382  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1383  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1384  },
1385 
1386  {
1387  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1388  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1389  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1390  0,
1391  },
1392 
1393  {
1394  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1395  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1396  FREQ2FBIN(2472, 1),
1397  0,
1398  },
1399 
1400  {
1401  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1402  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1403  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1404  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1405  },
1406 
1407  {
1408  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1409  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1410  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1411  },
1412 
1413  {
1414  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1415  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1416  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1417  0
1418  },
1419 
1420  {
1421  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1422  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1423  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1424  0
1425  },
1426 
1427  {
1428  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1429  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1430  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1431  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1432  }
1433  },
1434  .ctlPowerData_2G = {
1435  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1436  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1438 
1439  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1440  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1441  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1442 
1443  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1444  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1445  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1446 
1447  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1448  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1449  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1450  },
1451  .modalHeader5G = {
1452  /* 4 idle,t1,t2,b (4 bits per setting) */
1453  .antCtrlCommon = LE32(0x220),
1454  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1455  .antCtrlCommon2 = LE32(0x44444),
1456  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1457  .antCtrlChain = {
1458  LE16(0x150), LE16(0x150), LE16(0x150),
1459  },
1460  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1461  .xatten1DB = {0, 0, 0},
1462 
1463  /*
1464  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1465  * for merlin (0xa20c/b20c 16:12
1466  */
1467  .xatten1Margin = {0, 0, 0},
1468  .tempSlope = 45,
1469  .voltSlope = 0,
1470  /* spurChans spur channels in usual fbin coding format */
1471  .spurChans = {0, 0, 0, 0, 0},
1472  /* noiseFloorThreshCh Check if the register is per chain */
1473  .noiseFloorThreshCh = {-1, 0, 0},
1474  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1475  .quick_drop = 0,
1476  .xpaBiasLvl = 0,
1477  .txFrameToDataStart = 0x0e,
1478  .txFrameToPaOn = 0x0e,
1479  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1480  .antennaGain = 0,
1481  .switchSettling = 0x2d,
1482  .adcDesiredSize = -30,
1483  .txEndToXpaOff = 0,
1484  .txEndToRxOn = 0x2,
1485  .txFrameToXpaOn = 0xe,
1486  .thresh62 = 28,
1487  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1488  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1489  .xlna_bias_strength = 0,
1490  .futureModal = {
1491  0, 0, 0, 0, 0, 0, 0,
1492  },
1493  },
1494  .base_ext2 = {
1495  .tempSlopeLow = 40,
1496  .tempSlopeHigh = 50,
1497  .xatten1DBLow = {0, 0, 0},
1498  .xatten1MarginLow = {0, 0, 0},
1499  .xatten1DBHigh = {0, 0, 0},
1500  .xatten1MarginHigh = {0, 0, 0}
1501  },
1502  .calFreqPier5G = {
1503  FREQ2FBIN(5180, 0),
1504  FREQ2FBIN(5220, 0),
1505  FREQ2FBIN(5320, 0),
1506  FREQ2FBIN(5400, 0),
1507  FREQ2FBIN(5500, 0),
1508  FREQ2FBIN(5600, 0),
1509  FREQ2FBIN(5700, 0),
1510  FREQ2FBIN(5785, 0)
1511  },
1512  .calPierData5G = {
1513  {
1514  {0, 0, 0, 0, 0},
1515  {0, 0, 0, 0, 0},
1516  {0, 0, 0, 0, 0},
1517  {0, 0, 0, 0, 0},
1518  {0, 0, 0, 0, 0},
1519  {0, 0, 0, 0, 0},
1520  {0, 0, 0, 0, 0},
1521  {0, 0, 0, 0, 0},
1522  },
1523  {
1524  {0, 0, 0, 0, 0},
1525  {0, 0, 0, 0, 0},
1526  {0, 0, 0, 0, 0},
1527  {0, 0, 0, 0, 0},
1528  {0, 0, 0, 0, 0},
1529  {0, 0, 0, 0, 0},
1530  {0, 0, 0, 0, 0},
1531  {0, 0, 0, 0, 0},
1532  },
1533  {
1534  {0, 0, 0, 0, 0},
1535  {0, 0, 0, 0, 0},
1536  {0, 0, 0, 0, 0},
1537  {0, 0, 0, 0, 0},
1538  {0, 0, 0, 0, 0},
1539  {0, 0, 0, 0, 0},
1540  {0, 0, 0, 0, 0},
1541  {0, 0, 0, 0, 0},
1542  },
1543 
1544  },
1545  .calTarget_freqbin_5G = {
1546  FREQ2FBIN(5180, 0),
1547  FREQ2FBIN(5240, 0),
1548  FREQ2FBIN(5320, 0),
1549  FREQ2FBIN(5400, 0),
1550  FREQ2FBIN(5500, 0),
1551  FREQ2FBIN(5600, 0),
1552  FREQ2FBIN(5700, 0),
1553  FREQ2FBIN(5825, 0)
1554  },
1555  .calTarget_freqbin_5GHT20 = {
1556  FREQ2FBIN(5180, 0),
1557  FREQ2FBIN(5240, 0),
1558  FREQ2FBIN(5320, 0),
1559  FREQ2FBIN(5400, 0),
1560  FREQ2FBIN(5500, 0),
1561  FREQ2FBIN(5700, 0),
1562  FREQ2FBIN(5745, 0),
1563  FREQ2FBIN(5825, 0)
1564  },
1565  .calTarget_freqbin_5GHT40 = {
1566  FREQ2FBIN(5180, 0),
1567  FREQ2FBIN(5240, 0),
1568  FREQ2FBIN(5320, 0),
1569  FREQ2FBIN(5400, 0),
1570  FREQ2FBIN(5500, 0),
1571  FREQ2FBIN(5700, 0),
1572  FREQ2FBIN(5745, 0),
1573  FREQ2FBIN(5825, 0)
1574  },
1575  .calTargetPower5G = {
1576  /* 6-24,36,48,54 */
1577  { {30, 30, 28, 24} },
1578  { {30, 30, 28, 24} },
1579  { {30, 30, 28, 24} },
1580  { {30, 30, 28, 24} },
1581  { {30, 30, 28, 24} },
1582  { {30, 30, 28, 24} },
1583  { {30, 30, 28, 24} },
1584  { {30, 30, 28, 24} },
1585  },
1586  .calTargetPower5GHT20 = {
1587  /*
1588  * 0_8_16,1-3_9-11_17-19,
1589  * 4,5,6,7,12,13,14,15,20,21,22,23
1590  */
1591  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1592  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1593  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1594  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1595  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1596  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1597  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1598  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1599  },
1600  .calTargetPower5GHT40 = {
1601  /*
1602  * 0_8_16,1-3_9-11_17-19,
1603  * 4,5,6,7,12,13,14,15,20,21,22,23
1604  */
1605  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1606  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1607  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1608  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1609  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1610  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1611  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1612  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1613  },
1614  .ctlIndex_5G = {
1615  0x10, 0x16, 0x18, 0x40, 0x46,
1616  0x48, 0x30, 0x36, 0x38
1617  },
1618  .ctl_freqbin_5G = {
1619  {
1620  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1621  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1622  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1623  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1624  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1625  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1626  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1627  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1628  },
1629  {
1630  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1631  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1632  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1633  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1634  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1635  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1636  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1637  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1638  },
1639 
1640  {
1641  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1642  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1643  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1644  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1645  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1646  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1647  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1648  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1649  },
1650 
1651  {
1652  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1653  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1654  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1655  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1656  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1657  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1658  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1659  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1660  },
1661 
1662  {
1663  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1664  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1665  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1666  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1667  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1668  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1669  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1670  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1671  },
1672 
1673  {
1674  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1675  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1676  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1677  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1678  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1679  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1680  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1681  /* Data[5].ctlEdges[7].bChannel */ 0xFF
1682  },
1683 
1684  {
1685  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1686  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1687  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1688  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1689  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1690  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1691  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1692  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1693  },
1694 
1695  {
1696  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1697  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1698  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1699  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1700  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1701  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1702  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1703  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1704  },
1705 
1706  {
1707  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1708  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1709  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1710  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1711  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1712  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1713  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1714  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1715  }
1716  },
1717  .ctlPowerData_5G = {
1718  {
1719  {
1720  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1721  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1722  }
1723  },
1724  {
1725  {
1726  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1727  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1728  }
1729  },
1730  {
1731  {
1732  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1733  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1734  }
1735  },
1736  {
1737  {
1738  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1739  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1740  }
1741  },
1742  {
1743  {
1744  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1745  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1746  }
1747  },
1748  {
1749  {
1750  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1751  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1752  }
1753  },
1754  {
1755  {
1756  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1757  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1758  }
1759  },
1760  {
1761  {
1762  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1763  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1764  }
1765  },
1766  {
1767  {
1768  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1769  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1770  }
1771  },
1772  }
1773 };
1774 
1775 
1776 static const struct ar9300_eeprom ar9300_x112 = {
1777  .eepromVersion = 2,
1778  .templateVersion = 5,
1779  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1780  .custData = {"x112-041-f0000"},
1781  .baseEepHeader = {
1782  .regDmn = { LE16(0), LE16(0x1f) },
1783  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1784  .opCapFlags = {
1785  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1786  .eepMisc = 0,
1787  },
1788  .rfSilent = 0,
1789  .blueToothOptions = 0,
1790  .deviceCap = 0,
1791  .deviceType = 5, /* takes lower byte in eeprom location */
1792  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1793  .params_for_tuning_caps = {0, 0},
1794  .featureEnable = 0x0d,
1795  /*
1796  * bit0 - enable tx temp comp - disabled
1797  * bit1 - enable tx volt comp - disabled
1798  * bit2 - enable fastclock - enabled
1799  * bit3 - enable doubling - enabled
1800  * bit4 - enable internal regulator - disabled
1801  * bit5 - enable pa predistortion - disabled
1802  */
1803  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1804  .eepromWriteEnableGpio = 6,
1805  .wlanDisableGpio = 0,
1806  .wlanLedGpio = 8,
1807  .rxBandSelectGpio = 0xff,
1808  .txrxgain = 0x0,
1809  .swreg = 0,
1810  },
1811  .modalHeader2G = {
1812  /* ar9300_modal_eep_header 2g */
1813  /* 4 idle,t1,t2,b(4 bits per setting) */
1814  .antCtrlCommon = LE32(0x110),
1815  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1816  .antCtrlCommon2 = LE32(0x22222),
1817 
1818  /*
1819  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1820  * rx1, rx12, b (2 bits each)
1821  */
1822  .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1823 
1824  /*
1825  * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1826  * for ar9280 (0xa20c/b20c 5:0)
1827  */
1828  .xatten1DB = {0x1b, 0x1b, 0x1b},
1829 
1830  /*
1831  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1832  * for ar9280 (0xa20c/b20c 16:12
1833  */
1834  .xatten1Margin = {0x15, 0x15, 0x15},
1835  .tempSlope = 50,
1836  .voltSlope = 0,
1837 
1838  /*
1839  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1840  * channels in usual fbin coding format
1841  */
1842  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1843 
1844  /*
1845  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1846  * if the register is per chain
1847  */
1848  .noiseFloorThreshCh = {-1, 0, 0},
1849  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1850  .quick_drop = 0,
1851  .xpaBiasLvl = 0,
1852  .txFrameToDataStart = 0x0e,
1853  .txFrameToPaOn = 0x0e,
1854  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1855  .antennaGain = 0,
1856  .switchSettling = 0x2c,
1857  .adcDesiredSize = -30,
1858  .txEndToXpaOff = 0,
1859  .txEndToRxOn = 0x2,
1860  .txFrameToXpaOn = 0xe,
1861  .thresh62 = 28,
1862  .papdRateMaskHt20 = LE32(0x0c80c080),
1863  .papdRateMaskHt40 = LE32(0x0080c080),
1864  .xlna_bias_strength = 0,
1865  .futureModal = {
1866  0, 0, 0, 0, 0, 0, 0,
1867  },
1868  },
1869  .base_ext1 = {
1870  .ant_div_control = 0,
1871  .future = {0, 0, 0},
1872  .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
1873  },
1874  .calFreqPier2G = {
1875  FREQ2FBIN(2412, 1),
1876  FREQ2FBIN(2437, 1),
1877  FREQ2FBIN(2472, 1),
1878  },
1879  /* ar9300_cal_data_per_freq_op_loop 2g */
1880  .calPierData2G = {
1881  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1882  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1883  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1884  },
1885  .calTarget_freqbin_Cck = {
1886  FREQ2FBIN(2412, 1),
1887  FREQ2FBIN(2472, 1),
1888  },
1889  .calTarget_freqbin_2G = {
1890  FREQ2FBIN(2412, 1),
1891  FREQ2FBIN(2437, 1),
1892  FREQ2FBIN(2472, 1)
1893  },
1894  .calTarget_freqbin_2GHT20 = {
1895  FREQ2FBIN(2412, 1),
1896  FREQ2FBIN(2437, 1),
1897  FREQ2FBIN(2472, 1)
1898  },
1899  .calTarget_freqbin_2GHT40 = {
1900  FREQ2FBIN(2412, 1),
1901  FREQ2FBIN(2437, 1),
1902  FREQ2FBIN(2472, 1)
1903  },
1904  .calTargetPowerCck = {
1905  /* 1L-5L,5S,11L,11s */
1906  { {38, 38, 38, 38} },
1907  { {38, 38, 38, 38} },
1908  },
1909  .calTargetPower2G = {
1910  /* 6-24,36,48,54 */
1911  { {38, 38, 36, 34} },
1912  { {38, 38, 36, 34} },
1913  { {38, 38, 34, 32} },
1914  },
1915  .calTargetPower2GHT20 = {
1916  { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1917  { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1918  { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1919  },
1920  .calTargetPower2GHT40 = {
1921  { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1922  { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1923  { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1924  },
1925  .ctlIndex_2G = {
1926  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1927  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1928  },
1929  .ctl_freqbin_2G = {
1930  {
1931  FREQ2FBIN(2412, 1),
1932  FREQ2FBIN(2417, 1),
1933  FREQ2FBIN(2457, 1),
1934  FREQ2FBIN(2462, 1)
1935  },
1936  {
1937  FREQ2FBIN(2412, 1),
1938  FREQ2FBIN(2417, 1),
1939  FREQ2FBIN(2462, 1),
1940  0xFF,
1941  },
1942 
1943  {
1944  FREQ2FBIN(2412, 1),
1945  FREQ2FBIN(2417, 1),
1946  FREQ2FBIN(2462, 1),
1947  0xFF,
1948  },
1949  {
1950  FREQ2FBIN(2422, 1),
1951  FREQ2FBIN(2427, 1),
1952  FREQ2FBIN(2447, 1),
1953  FREQ2FBIN(2452, 1)
1954  },
1955 
1956  {
1957  /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1958  /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1959  /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1960  /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1961  },
1962 
1963  {
1964  /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1965  /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1966  /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1967  0,
1968  },
1969 
1970  {
1971  /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1972  /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1973  FREQ2FBIN(2472, 1),
1974  0,
1975  },
1976 
1977  {
1978  /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1979  /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1980  /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1981  /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1982  },
1983 
1984  {
1985  /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1986  /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1987  /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1988  },
1989 
1990  {
1991  /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992  /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993  /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994  0
1995  },
1996 
1997  {
1998  /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999  /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000  /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2001  0
2002  },
2003 
2004  {
2005  /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2006  /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2007  /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2008  /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2009  }
2010  },
2011  .ctlPowerData_2G = {
2012  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2013  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2015 
2016  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2017  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2018  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2019 
2020  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2021  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2022  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2023 
2024  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2025  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2026  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2027  },
2028  .modalHeader5G = {
2029  /* 4 idle,t1,t2,b (4 bits per setting) */
2030  .antCtrlCommon = LE32(0x110),
2031  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2032  .antCtrlCommon2 = LE32(0x22222),
2033  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2034  .antCtrlChain = {
2035  LE16(0x0), LE16(0x0), LE16(0x0),
2036  },
2037  /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2038  .xatten1DB = {0x13, 0x19, 0x17},
2039 
2040  /*
2041  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2042  * for merlin (0xa20c/b20c 16:12
2043  */
2044  .xatten1Margin = {0x19, 0x19, 0x19},
2045  .tempSlope = 70,
2046  .voltSlope = 15,
2047  /* spurChans spur channels in usual fbin coding format */
2048  .spurChans = {0, 0, 0, 0, 0},
2049  /* noiseFloorThreshch check if the register is per chain */
2050  .noiseFloorThreshCh = {-1, 0, 0},
2051  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2052  .quick_drop = 0,
2053  .xpaBiasLvl = 0,
2054  .txFrameToDataStart = 0x0e,
2055  .txFrameToPaOn = 0x0e,
2056  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2057  .antennaGain = 0,
2058  .switchSettling = 0x2d,
2059  .adcDesiredSize = -30,
2060  .txEndToXpaOff = 0,
2061  .txEndToRxOn = 0x2,
2062  .txFrameToXpaOn = 0xe,
2063  .thresh62 = 28,
2064  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2065  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2066  .xlna_bias_strength = 0,
2067  .futureModal = {
2068  0, 0, 0, 0, 0, 0, 0,
2069  },
2070  },
2071  .base_ext2 = {
2072  .tempSlopeLow = 72,
2073  .tempSlopeHigh = 105,
2074  .xatten1DBLow = {0x10, 0x14, 0x10},
2075  .xatten1MarginLow = {0x19, 0x19 , 0x19},
2076  .xatten1DBHigh = {0x1d, 0x20, 0x24},
2077  .xatten1MarginHigh = {0x10, 0x10, 0x10}
2078  },
2079  .calFreqPier5G = {
2080  FREQ2FBIN(5180, 0),
2081  FREQ2FBIN(5220, 0),
2082  FREQ2FBIN(5320, 0),
2083  FREQ2FBIN(5400, 0),
2084  FREQ2FBIN(5500, 0),
2085  FREQ2FBIN(5600, 0),
2086  FREQ2FBIN(5700, 0),
2087  FREQ2FBIN(5785, 0)
2088  },
2089  .calPierData5G = {
2090  {
2091  {0, 0, 0, 0, 0},
2092  {0, 0, 0, 0, 0},
2093  {0, 0, 0, 0, 0},
2094  {0, 0, 0, 0, 0},
2095  {0, 0, 0, 0, 0},
2096  {0, 0, 0, 0, 0},
2097  {0, 0, 0, 0, 0},
2098  {0, 0, 0, 0, 0},
2099  },
2100  {
2101  {0, 0, 0, 0, 0},
2102  {0, 0, 0, 0, 0},
2103  {0, 0, 0, 0, 0},
2104  {0, 0, 0, 0, 0},
2105  {0, 0, 0, 0, 0},
2106  {0, 0, 0, 0, 0},
2107  {0, 0, 0, 0, 0},
2108  {0, 0, 0, 0, 0},
2109  },
2110  {
2111  {0, 0, 0, 0, 0},
2112  {0, 0, 0, 0, 0},
2113  {0, 0, 0, 0, 0},
2114  {0, 0, 0, 0, 0},
2115  {0, 0, 0, 0, 0},
2116  {0, 0, 0, 0, 0},
2117  {0, 0, 0, 0, 0},
2118  {0, 0, 0, 0, 0},
2119  },
2120 
2121  },
2122  .calTarget_freqbin_5G = {
2123  FREQ2FBIN(5180, 0),
2124  FREQ2FBIN(5220, 0),
2125  FREQ2FBIN(5320, 0),
2126  FREQ2FBIN(5400, 0),
2127  FREQ2FBIN(5500, 0),
2128  FREQ2FBIN(5600, 0),
2129  FREQ2FBIN(5725, 0),
2130  FREQ2FBIN(5825, 0)
2131  },
2132  .calTarget_freqbin_5GHT20 = {
2133  FREQ2FBIN(5180, 0),
2134  FREQ2FBIN(5220, 0),
2135  FREQ2FBIN(5320, 0),
2136  FREQ2FBIN(5400, 0),
2137  FREQ2FBIN(5500, 0),
2138  FREQ2FBIN(5600, 0),
2139  FREQ2FBIN(5725, 0),
2140  FREQ2FBIN(5825, 0)
2141  },
2142  .calTarget_freqbin_5GHT40 = {
2143  FREQ2FBIN(5180, 0),
2144  FREQ2FBIN(5220, 0),
2145  FREQ2FBIN(5320, 0),
2146  FREQ2FBIN(5400, 0),
2147  FREQ2FBIN(5500, 0),
2148  FREQ2FBIN(5600, 0),
2149  FREQ2FBIN(5725, 0),
2150  FREQ2FBIN(5825, 0)
2151  },
2152  .calTargetPower5G = {
2153  /* 6-24,36,48,54 */
2154  { {32, 32, 28, 26} },
2155  { {32, 32, 28, 26} },
2156  { {32, 32, 28, 26} },
2157  { {32, 32, 26, 24} },
2158  { {32, 32, 26, 24} },
2159  { {32, 32, 24, 22} },
2160  { {30, 30, 24, 22} },
2161  { {30, 30, 24, 22} },
2162  },
2163  .calTargetPower5GHT20 = {
2164  /*
2165  * 0_8_16,1-3_9-11_17-19,
2166  * 4,5,6,7,12,13,14,15,20,21,22,23
2167  */
2168  { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2169  { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2170  { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2171  { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2172  { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2173  { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2174  { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2175  { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2176  },
2177  .calTargetPower5GHT40 = {
2178  /*
2179  * 0_8_16,1-3_9-11_17-19,
2180  * 4,5,6,7,12,13,14,15,20,21,22,23
2181  */
2182  { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2183  { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2184  { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2185  { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2186  { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2187  { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2188  { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2189  { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2190  },
2191  .ctlIndex_5G = {
2192  0x10, 0x16, 0x18, 0x40, 0x46,
2193  0x48, 0x30, 0x36, 0x38
2194  },
2195  .ctl_freqbin_5G = {
2196  {
2197  /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2198  /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2199  /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2200  /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2201  /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2202  /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2203  /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2204  /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2205  },
2206  {
2207  /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2208  /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2209  /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2210  /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2211  /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2212  /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2213  /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2214  /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2215  },
2216 
2217  {
2218  /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2219  /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2220  /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2221  /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2222  /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2223  /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2224  /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2225  /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2226  },
2227 
2228  {
2229  /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2230  /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2231  /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2232  /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2233  /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2234  /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2235  /* Data[3].ctledges[6].bchannel */ 0xFF,
2236  /* Data[3].ctledges[7].bchannel */ 0xFF,
2237  },
2238 
2239  {
2240  /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2241  /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2242  /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2243  /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2244  /* Data[4].ctledges[4].bchannel */ 0xFF,
2245  /* Data[4].ctledges[5].bchannel */ 0xFF,
2246  /* Data[4].ctledges[6].bchannel */ 0xFF,
2247  /* Data[4].ctledges[7].bchannel */ 0xFF,
2248  },
2249 
2250  {
2251  /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2252  /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2253  /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2254  /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2255  /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2256  /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2257  /* Data[5].ctledges[6].bchannel */ 0xFF,
2258  /* Data[5].ctledges[7].bchannel */ 0xFF
2259  },
2260 
2261  {
2262  /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2263  /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2264  /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2265  /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2266  /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2267  /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2268  /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2269  /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2270  },
2271 
2272  {
2273  /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2274  /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2275  /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2276  /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2277  /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2278  /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2279  /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2280  /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2281  },
2282 
2283  {
2284  /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2285  /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2286  /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2287  /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2288  /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2289  /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2290  /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2291  /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2292  }
2293  },
2294  .ctlPowerData_5G = {
2295  {
2296  {
2297  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2298  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2299  }
2300  },
2301  {
2302  {
2303  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2304  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2305  }
2306  },
2307  {
2308  {
2309  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2310  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2311  }
2312  },
2313  {
2314  {
2315  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2316  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2317  }
2318  },
2319  {
2320  {
2321  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2322  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2323  }
2324  },
2325  {
2326  {
2327  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2328  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2329  }
2330  },
2331  {
2332  {
2333  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2334  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2335  }
2336  },
2337  {
2338  {
2339  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2340  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2341  }
2342  },
2343  {
2344  {
2345  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2346  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2347  }
2348  },
2349  }
2350 };
2351 
2352 static const struct ar9300_eeprom ar9300_h116 = {
2353  .eepromVersion = 2,
2354  .templateVersion = 4,
2355  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2356  .custData = {"h116-041-f0000"},
2357  .baseEepHeader = {
2358  .regDmn = { LE16(0), LE16(0x1f) },
2359  .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2360  .opCapFlags = {
2361  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2362  .eepMisc = 0,
2363  },
2364  .rfSilent = 0,
2365  .blueToothOptions = 0,
2366  .deviceCap = 0,
2367  .deviceType = 5, /* takes lower byte in eeprom location */
2368  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2369  .params_for_tuning_caps = {0, 0},
2370  .featureEnable = 0x0d,
2371  /*
2372  * bit0 - enable tx temp comp - disabled
2373  * bit1 - enable tx volt comp - disabled
2374  * bit2 - enable fastClock - enabled
2375  * bit3 - enable doubling - enabled
2376  * bit4 - enable internal regulator - disabled
2377  * bit5 - enable pa predistortion - disabled
2378  */
2379  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2380  .eepromWriteEnableGpio = 6,
2381  .wlanDisableGpio = 0,
2382  .wlanLedGpio = 8,
2383  .rxBandSelectGpio = 0xff,
2384  .txrxgain = 0x10,
2385  .swreg = 0,
2386  },
2387  .modalHeader2G = {
2388  /* ar9300_modal_eep_header 2g */
2389  /* 4 idle,t1,t2,b(4 bits per setting) */
2390  .antCtrlCommon = LE32(0x110),
2391  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2392  .antCtrlCommon2 = LE32(0x44444),
2393 
2394  /*
2395  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2396  * rx1, rx12, b (2 bits each)
2397  */
2398  .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2399 
2400  /*
2401  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2402  * for ar9280 (0xa20c/b20c 5:0)
2403  */
2404  .xatten1DB = {0x1f, 0x1f, 0x1f},
2405 
2406  /*
2407  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2408  * for ar9280 (0xa20c/b20c 16:12
2409  */
2410  .xatten1Margin = {0x12, 0x12, 0x12},
2411  .tempSlope = 25,
2412  .voltSlope = 0,
2413 
2414  /*
2415  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2416  * channels in usual fbin coding format
2417  */
2418  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2419 
2420  /*
2421  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2422  * if the register is per chain
2423  */
2424  .noiseFloorThreshCh = {-1, 0, 0},
2425  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2426  .quick_drop = 0,
2427  .xpaBiasLvl = 0,
2428  .txFrameToDataStart = 0x0e,
2429  .txFrameToPaOn = 0x0e,
2430  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2431  .antennaGain = 0,
2432  .switchSettling = 0x2c,
2433  .adcDesiredSize = -30,
2434  .txEndToXpaOff = 0,
2435  .txEndToRxOn = 0x2,
2436  .txFrameToXpaOn = 0xe,
2437  .thresh62 = 28,
2438  .papdRateMaskHt20 = LE32(0x0c80C080),
2439  .papdRateMaskHt40 = LE32(0x0080C080),
2440  .xlna_bias_strength = 0,
2441  .futureModal = {
2442  0, 0, 0, 0, 0, 0, 0,
2443  },
2444  },
2445  .base_ext1 = {
2446  .ant_div_control = 0,
2447  .future = {0, 0, 0},
2448  .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
2449  },
2450  .calFreqPier2G = {
2451  FREQ2FBIN(2412, 1),
2452  FREQ2FBIN(2437, 1),
2453  FREQ2FBIN(2462, 1),
2454  },
2455  /* ar9300_cal_data_per_freq_op_loop 2g */
2456  .calPierData2G = {
2457  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2458  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2459  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2460  },
2461  .calTarget_freqbin_Cck = {
2462  FREQ2FBIN(2412, 1),
2463  FREQ2FBIN(2472, 1),
2464  },
2465  .calTarget_freqbin_2G = {
2466  FREQ2FBIN(2412, 1),
2467  FREQ2FBIN(2437, 1),
2468  FREQ2FBIN(2472, 1)
2469  },
2470  .calTarget_freqbin_2GHT20 = {
2471  FREQ2FBIN(2412, 1),
2472  FREQ2FBIN(2437, 1),
2473  FREQ2FBIN(2472, 1)
2474  },
2475  .calTarget_freqbin_2GHT40 = {
2476  FREQ2FBIN(2412, 1),
2477  FREQ2FBIN(2437, 1),
2478  FREQ2FBIN(2472, 1)
2479  },
2480  .calTargetPowerCck = {
2481  /* 1L-5L,5S,11L,11S */
2482  { {34, 34, 34, 34} },
2483  { {34, 34, 34, 34} },
2484  },
2485  .calTargetPower2G = {
2486  /* 6-24,36,48,54 */
2487  { {34, 34, 32, 32} },
2488  { {34, 34, 32, 32} },
2489  { {34, 34, 32, 32} },
2490  },
2491  .calTargetPower2GHT20 = {
2492  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2493  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2494  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2495  },
2496  .calTargetPower2GHT40 = {
2497  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2498  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2499  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2500  },
2501  .ctlIndex_2G = {
2502  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2503  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2504  },
2505  .ctl_freqbin_2G = {
2506  {
2507  FREQ2FBIN(2412, 1),
2508  FREQ2FBIN(2417, 1),
2509  FREQ2FBIN(2457, 1),
2510  FREQ2FBIN(2462, 1)
2511  },
2512  {
2513  FREQ2FBIN(2412, 1),
2514  FREQ2FBIN(2417, 1),
2515  FREQ2FBIN(2462, 1),
2516  0xFF,
2517  },
2518 
2519  {
2520  FREQ2FBIN(2412, 1),
2521  FREQ2FBIN(2417, 1),
2522  FREQ2FBIN(2462, 1),
2523  0xFF,
2524  },
2525  {
2526  FREQ2FBIN(2422, 1),
2527  FREQ2FBIN(2427, 1),
2528  FREQ2FBIN(2447, 1),
2529  FREQ2FBIN(2452, 1)
2530  },
2531 
2532  {
2533  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2535  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2536  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2537  },
2538 
2539  {
2540  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2541  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2542  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2543  0,
2544  },
2545 
2546  {
2547  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549  FREQ2FBIN(2472, 1),
2550  0,
2551  },
2552 
2553  {
2554  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2555  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2556  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2557  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2558  },
2559 
2560  {
2561  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564  },
2565 
2566  {
2567  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2568  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2569  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2570  0
2571  },
2572 
2573  {
2574  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2575  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2576  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2577  0
2578  },
2579 
2580  {
2581  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2582  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2583  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2584  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2585  }
2586  },
2587  .ctlPowerData_2G = {
2588  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2589  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2590  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2591 
2592  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2593  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2594  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2595 
2596  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2597  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2598  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2599 
2600  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2601  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2602  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2603  },
2604  .modalHeader5G = {
2605  /* 4 idle,t1,t2,b (4 bits per setting) */
2606  .antCtrlCommon = LE32(0x220),
2607  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2608  .antCtrlCommon2 = LE32(0x44444),
2609  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2610  .antCtrlChain = {
2611  LE16(0x150), LE16(0x150), LE16(0x150),
2612  },
2613  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2614  .xatten1DB = {0x19, 0x19, 0x19},
2615 
2616  /*
2617  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2618  * for merlin (0xa20c/b20c 16:12
2619  */
2620  .xatten1Margin = {0x14, 0x14, 0x14},
2621  .tempSlope = 70,
2622  .voltSlope = 0,
2623  /* spurChans spur channels in usual fbin coding format */
2624  .spurChans = {0, 0, 0, 0, 0},
2625  /* noiseFloorThreshCh Check if the register is per chain */
2626  .noiseFloorThreshCh = {-1, 0, 0},
2627  .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2628  .quick_drop = 0,
2629  .xpaBiasLvl = 0,
2630  .txFrameToDataStart = 0x0e,
2631  .txFrameToPaOn = 0x0e,
2632  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2633  .antennaGain = 0,
2634  .switchSettling = 0x2d,
2635  .adcDesiredSize = -30,
2636  .txEndToXpaOff = 0,
2637  .txEndToRxOn = 0x2,
2638  .txFrameToXpaOn = 0xe,
2639  .thresh62 = 28,
2640  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2641  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2642  .xlna_bias_strength = 0,
2643  .futureModal = {
2644  0, 0, 0, 0, 0, 0, 0,
2645  },
2646  },
2647  .base_ext2 = {
2648  .tempSlopeLow = 35,
2649  .tempSlopeHigh = 50,
2650  .xatten1DBLow = {0, 0, 0},
2651  .xatten1MarginLow = {0, 0, 0},
2652  .xatten1DBHigh = {0, 0, 0},
2653  .xatten1MarginHigh = {0, 0, 0}
2654  },
2655  .calFreqPier5G = {
2656  FREQ2FBIN(5160, 0),
2657  FREQ2FBIN(5220, 0),
2658  FREQ2FBIN(5320, 0),
2659  FREQ2FBIN(5400, 0),
2660  FREQ2FBIN(5500, 0),
2661  FREQ2FBIN(5600, 0),
2662  FREQ2FBIN(5700, 0),
2663  FREQ2FBIN(5785, 0)
2664  },
2665  .calPierData5G = {
2666  {
2667  {0, 0, 0, 0, 0},
2668  {0, 0, 0, 0, 0},
2669  {0, 0, 0, 0, 0},
2670  {0, 0, 0, 0, 0},
2671  {0, 0, 0, 0, 0},
2672  {0, 0, 0, 0, 0},
2673  {0, 0, 0, 0, 0},
2674  {0, 0, 0, 0, 0},
2675  },
2676  {
2677  {0, 0, 0, 0, 0},
2678  {0, 0, 0, 0, 0},
2679  {0, 0, 0, 0, 0},
2680  {0, 0, 0, 0, 0},
2681  {0, 0, 0, 0, 0},
2682  {0, 0, 0, 0, 0},
2683  {0, 0, 0, 0, 0},
2684  {0, 0, 0, 0, 0},
2685  },
2686  {
2687  {0, 0, 0, 0, 0},
2688  {0, 0, 0, 0, 0},
2689  {0, 0, 0, 0, 0},
2690  {0, 0, 0, 0, 0},
2691  {0, 0, 0, 0, 0},
2692  {0, 0, 0, 0, 0},
2693  {0, 0, 0, 0, 0},
2694  {0, 0, 0, 0, 0},
2695  },
2696 
2697  },
2698  .calTarget_freqbin_5G = {
2699  FREQ2FBIN(5180, 0),
2700  FREQ2FBIN(5240, 0),
2701  FREQ2FBIN(5320, 0),
2702  FREQ2FBIN(5400, 0),
2703  FREQ2FBIN(5500, 0),
2704  FREQ2FBIN(5600, 0),
2705  FREQ2FBIN(5700, 0),
2706  FREQ2FBIN(5825, 0)
2707  },
2708  .calTarget_freqbin_5GHT20 = {
2709  FREQ2FBIN(5180, 0),
2710  FREQ2FBIN(5240, 0),
2711  FREQ2FBIN(5320, 0),
2712  FREQ2FBIN(5400, 0),
2713  FREQ2FBIN(5500, 0),
2714  FREQ2FBIN(5700, 0),
2715  FREQ2FBIN(5745, 0),
2716  FREQ2FBIN(5825, 0)
2717  },
2718  .calTarget_freqbin_5GHT40 = {
2719  FREQ2FBIN(5180, 0),
2720  FREQ2FBIN(5240, 0),
2721  FREQ2FBIN(5320, 0),
2722  FREQ2FBIN(5400, 0),
2723  FREQ2FBIN(5500, 0),
2724  FREQ2FBIN(5700, 0),
2725  FREQ2FBIN(5745, 0),
2726  FREQ2FBIN(5825, 0)
2727  },
2728  .calTargetPower5G = {
2729  /* 6-24,36,48,54 */
2730  { {30, 30, 28, 24} },
2731  { {30, 30, 28, 24} },
2732  { {30, 30, 28, 24} },
2733  { {30, 30, 28, 24} },
2734  { {30, 30, 28, 24} },
2735  { {30, 30, 28, 24} },
2736  { {30, 30, 28, 24} },
2737  { {30, 30, 28, 24} },
2738  },
2739  .calTargetPower5GHT20 = {
2740  /*
2741  * 0_8_16,1-3_9-11_17-19,
2742  * 4,5,6,7,12,13,14,15,20,21,22,23
2743  */
2744  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2745  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2746  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2747  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2748  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2749  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2750  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2751  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2752  },
2753  .calTargetPower5GHT40 = {
2754  /*
2755  * 0_8_16,1-3_9-11_17-19,
2756  * 4,5,6,7,12,13,14,15,20,21,22,23
2757  */
2758  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2759  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2760  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2761  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2762  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2763  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2764  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2765  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2766  },
2767  .ctlIndex_5G = {
2768  0x10, 0x16, 0x18, 0x40, 0x46,
2769  0x48, 0x30, 0x36, 0x38
2770  },
2771  .ctl_freqbin_5G = {
2772  {
2773  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2774  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2775  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2776  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2777  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2778  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2779  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2780  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2781  },
2782  {
2783  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2784  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2785  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2786  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2787  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2788  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2789  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2790  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2791  },
2792 
2793  {
2794  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2795  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2796  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2797  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2798  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2799  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2800  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2801  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2802  },
2803 
2804  {
2805  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2807  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2808  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2809  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2810  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2812  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2813  },
2814 
2815  {
2816  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2817  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2818  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2819  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2820  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2821  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2822  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2823  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2824  },
2825 
2826  {
2827  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2828  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2829  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2830  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2831  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2832  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2833  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2834  /* Data[5].ctlEdges[7].bChannel */ 0xFF
2835  },
2836 
2837  {
2838  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2840  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2841  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2842  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2843  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2844  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2845  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2846  },
2847 
2848  {
2849  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2850  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2851  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2852  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2853  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2854  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2855  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2856  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2857  },
2858 
2859  {
2860  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2861  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2862  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2863  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2864  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2865  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2866  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2867  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2868  }
2869  },
2870  .ctlPowerData_5G = {
2871  {
2872  {
2873  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2874  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2875  }
2876  },
2877  {
2878  {
2879  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2880  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2881  }
2882  },
2883  {
2884  {
2885  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2886  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2887  }
2888  },
2889  {
2890  {
2891  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2892  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2893  }
2894  },
2895  {
2896  {
2897  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2898  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2899  }
2900  },
2901  {
2902  {
2903  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2904  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2905  }
2906  },
2907  {
2908  {
2909  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2910  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2911  }
2912  },
2913  {
2914  {
2915  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2916  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2917  }
2918  },
2919  {
2920  {
2921  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2922  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2923  }
2924  },
2925  }
2926 };
2927 
2928 
2929 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2930  &ar9300_default,
2931  &ar9300_x112,
2932  &ar9300_h116,
2933  &ar9300_h112,
2934  &ar9300_x113,
2935 };
2936 
2937 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2938 {
2939 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2940  int it;
2941 
2942  for (it = 0; it < N_LOOP; it++)
2943  if (ar9300_eep_templates[it]->templateVersion == id)
2944  return ar9300_eep_templates[it];
2945  return NULL;
2946 #undef N_LOOP
2947 }
2948 
2949 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2950 {
2951  return 0;
2952 }
2953 
2954 static int interpolate(int x, int xa, int xb, int ya, int yb)
2955 {
2956  int bf, factor, plus;
2957 
2958  bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2959  factor = bf / 2;
2960  plus = bf % 2;
2961  return ya + factor + plus;
2962 }
2963 
2964 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2965  enum eeprom_param param)
2966 {
2967  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2968  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2969 
2970  switch (param) {
2971  case EEP_MAC_LSW:
2972  return get_unaligned_be16(eep->macAddr);
2973  case EEP_MAC_MID:
2974  return get_unaligned_be16(eep->macAddr + 2);
2975  case EEP_MAC_MSW:
2976  return get_unaligned_be16(eep->macAddr + 4);
2977  case EEP_REG_0:
2978  return le16_to_cpu(pBase->regDmn[0]);
2979  case EEP_OP_CAP:
2980  return pBase->deviceCap;
2981  case EEP_OP_MODE:
2982  return pBase->opCapFlags.opFlags;
2983  case EEP_RF_SILENT:
2984  return pBase->rfSilent;
2985  case EEP_TX_MASK:
2986  return (pBase->txrxMask >> 4) & 0xf;
2987  case EEP_RX_MASK:
2988  return pBase->txrxMask & 0xf;
2989  case EEP_PAPRD:
2990  if (AR_SREV_9462(ah))
2991  return false;
2992  if (!ah->config.enable_paprd);
2993  return false;
2994  return !!(pBase->featureEnable & BIT(5));
2995  case EEP_CHAIN_MASK_REDUCE:
2996  return (pBase->miscConfiguration >> 0x3) & 0x1;
2997  case EEP_ANT_DIV_CTL1:
2998  return eep->base_ext1.ant_div_control;
2999  case EEP_ANTENNA_GAIN_5G:
3000  return eep->modalHeader5G.antennaGain;
3001  case EEP_ANTENNA_GAIN_2G:
3002  return eep->modalHeader2G.antennaGain;
3003  default:
3004  return 0;
3005  }
3006 }
3007 
3008 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3009  u8 *buffer)
3010 {
3011  u16 val;
3012 
3013  if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3014  return false;
3015 
3016  *buffer = (val >> (8 * (address % 2))) & 0xff;
3017  return true;
3018 }
3019 
3020 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3021  u8 *buffer)
3022 {
3023  u16 val;
3024 
3025  if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3026  return false;
3027 
3028  buffer[0] = val >> 8;
3029  buffer[1] = val & 0xff;
3030 
3031  return true;
3032 }
3033 
3034 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3035  int count)
3036 {
3037  struct ath_common *common = ath9k_hw_common(ah);
3038  int i;
3039 
3040  if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3041  ath_dbg(common, EEPROM, "eeprom address not in range\n");
3042  return false;
3043  }
3044 
3045  /*
3046  * Since we're reading the bytes in reverse order from a little-endian
3047  * word stream, an even address means we only use the lower half of
3048  * the 16-bit word at that address
3049  */
3050  if (address % 2 == 0) {
3051  if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3052  goto error;
3053 
3054  count--;
3055  }
3056 
3057  for (i = 0; i < count / 2; i++) {
3058  if (!ar9300_eeprom_read_word(common, address, buffer))
3059  goto error;
3060 
3061  address -= 2;
3062  buffer += 2;
3063  }
3064 
3065  if (count % 2)
3066  if (!ar9300_eeprom_read_byte(common, address, buffer))
3067  goto error;
3068 
3069  return true;
3070 
3071 error:
3072  ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3073  address);
3074  return false;
3075 }
3076 
3077 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3078 {
3079  REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3080 
3081  if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3082  AR9300_OTP_STATUS_VALID, 1000))
3083  return false;
3084 
3085  *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3086  return true;
3087 }
3088 
3089 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3090  int count)
3091 {
3092  u32 data;
3093  int i;
3094 
3095  for (i = 0; i < count; i++) {
3096  int offset = 8 * ((address - i) % 4);
3097  if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3098  return false;
3099 
3100  buffer[i] = (data >> offset) & 0xff;
3101  }
3102 
3103  return true;
3104 }
3105 
3106 
3107 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3108  int *length, int *major, int *minor)
3109 {
3110  unsigned long value[4];
3111 
3112  value[0] = best[0];
3113  value[1] = best[1];
3114  value[2] = best[2];
3115  value[3] = best[3];
3116  *code = ((value[0] >> 5) & 0x0007);
3117  *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3118  *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3119  *major = (value[2] & 0x000f);
3120  *minor = (value[3] & 0x00ff);
3121 }
3122 
3123 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3124 {
3125  int it, checksum = 0;
3126 
3127  for (it = 0; it < dsize; it++) {
3128  checksum += data[it];
3129  checksum &= 0xffff;
3130  }
3131 
3132  return checksum;
3133 }
3134 
3135 static bool ar9300_uncompress_block(struct ath_hw *ah,
3136  u8 *mptr,
3137  int mdataSize,
3138  u8 *block,
3139  int size)
3140 {
3141  int it;
3142  int spot;
3143  int offset;
3144  int length;
3145  struct ath_common *common = ath9k_hw_common(ah);
3146 
3147  spot = 0;
3148 
3149  for (it = 0; it < size; it += (length+2)) {
3150  offset = block[it];
3151  offset &= 0xff;
3152  spot += offset;
3153  length = block[it+1];
3154  length &= 0xff;
3155 
3156  if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3157  ath_dbg(common, EEPROM,
3158  "Restore at %d: spot=%d offset=%d length=%d\n",
3159  it, spot, offset, length);
3160  memcpy(&mptr[spot], &block[it+2], length);
3161  spot += length;
3162  } else if (length > 0) {
3163  ath_dbg(common, EEPROM,
3164  "Bad restore at %d: spot=%d offset=%d length=%d\n",
3165  it, spot, offset, length);
3166  return false;
3167  }
3168  }
3169  return true;
3170 }
3171 
3172 static int ar9300_compress_decision(struct ath_hw *ah,
3173  int it,
3174  int code,
3175  int reference,
3176  u8 *mptr,
3177  u8 *word, int length, int mdata_size)
3178 {
3179  struct ath_common *common = ath9k_hw_common(ah);
3180  const struct ar9300_eeprom *eep = NULL;
3181 
3182  switch (code) {
3183  case _CompressNone:
3184  if (length != mdata_size) {
3185  ath_dbg(common, EEPROM,
3186  "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3187  mdata_size, length);
3188  return -1;
3189  }
3190  memcpy(mptr, word + COMP_HDR_LEN, length);
3191  ath_dbg(common, EEPROM,
3192  "restored eeprom %d: uncompressed, length %d\n",
3193  it, length);
3194  break;
3195  case _CompressBlock:
3196  if (reference == 0) {
3197  } else {
3198  eep = ar9003_eeprom_struct_find_by_id(reference);
3199  if (eep == NULL) {
3200  ath_dbg(common, EEPROM,
3201  "can't find reference eeprom struct %d\n",
3202  reference);
3203  return -1;
3204  }
3205  memcpy(mptr, eep, mdata_size);
3206  }
3207  ath_dbg(common, EEPROM,
3208  "restore eeprom %d: block, reference %d, length %d\n",
3209  it, reference, length);
3210  ar9300_uncompress_block(ah, mptr, mdata_size,
3211  (word + COMP_HDR_LEN), length);
3212  break;
3213  default:
3214  ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3215  return -1;
3216  }
3217  return 0;
3218 }
3219 
3220 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3221  int count);
3222 
3223 static bool ar9300_check_header(void *data)
3224 {
3225  u32 *word = data;
3226  return !(*word == 0 || *word == ~0);
3227 }
3228 
3229 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3230  int base_addr)
3231 {
3232  u8 header[4];
3233 
3234  if (!read(ah, base_addr, header, 4))
3235  return false;
3236 
3237  return ar9300_check_header(header);
3238 }
3239 
3240 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3241  int mdata_size)
3242 {
3243  struct ath_common *common = ath9k_hw_common(ah);
3244  u16 *data = (u16 *) mptr;
3245  int i;
3246 
3247  for (i = 0; i < mdata_size / 2; i++, data++)
3248  ath9k_hw_nvram_read(common, i, data);
3249 
3250  return 0;
3251 }
3252 /*
3253  * Read the configuration data from the eeprom.
3254  * The data can be put in any specified memory buffer.
3255  *
3256  * Returns -1 on error.
3257  * Returns address of next memory location on success.
3258  */
3259 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3260  u8 *mptr, int mdata_size)
3261 {
3262 #define MDEFAULT 15
3263 #define MSTATE 100
3264  int cptr;
3265  u8 *word;
3266  int code;
3267  int reference, length, major, minor;
3268  int osize;
3269  int it;
3270  u16 checksum, mchecksum;
3271  struct ath_common *common = ath9k_hw_common(ah);
3272  struct ar9300_eeprom *eep;
3273  eeprom_read_op read;
3274 
3275  if (ath9k_hw_use_flash(ah)) {
3276  u8 txrx;
3277 
3278  ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3279 
3280  /* check if eeprom contains valid data */
3281  eep = (struct ar9300_eeprom *) mptr;
3282  txrx = eep->baseEepHeader.txrxMask;
3283  if (txrx != 0 && txrx != 0xff)
3284  return 0;
3285  }
3286 
3287  word = kzalloc(2048, GFP_KERNEL);
3288  if (!word)
3289  return -ENOMEM;
3290 
3291  memcpy(mptr, &ar9300_default, mdata_size);
3292 
3293  read = ar9300_read_eeprom;
3294  if (AR_SREV_9485(ah))
3295  cptr = AR9300_BASE_ADDR_4K;
3296  else if (AR_SREV_9330(ah))
3297  cptr = AR9300_BASE_ADDR_512;
3298  else
3299  cptr = AR9300_BASE_ADDR;
3300  ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3301  cptr);
3302  if (ar9300_check_eeprom_header(ah, read, cptr))
3303  goto found;
3304 
3305  cptr = AR9300_BASE_ADDR_512;
3306  ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3307  cptr);
3308  if (ar9300_check_eeprom_header(ah, read, cptr))
3309  goto found;
3310 
3311  read = ar9300_read_otp;
3312  cptr = AR9300_BASE_ADDR;
3313  ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3314  if (ar9300_check_eeprom_header(ah, read, cptr))
3315  goto found;
3316 
3317  cptr = AR9300_BASE_ADDR_512;
3318  ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3319  if (ar9300_check_eeprom_header(ah, read, cptr))
3320  goto found;
3321 
3322  goto fail;
3323 
3324 found:
3325  ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3326 
3327  for (it = 0; it < MSTATE; it++) {
3328  if (!read(ah, cptr, word, COMP_HDR_LEN))
3329  goto fail;
3330 
3331  if (!ar9300_check_header(word))
3332  break;
3333 
3334  ar9300_comp_hdr_unpack(word, &code, &reference,
3335  &length, &major, &minor);
3336  ath_dbg(common, EEPROM,
3337  "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3338  cptr, code, reference, length, major, minor);
3339  if ((!AR_SREV_9485(ah) && length >= 1024) ||
3340  (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3341  ath_dbg(common, EEPROM, "Skipping bad header\n");
3342  cptr -= COMP_HDR_LEN;
3343  continue;
3344  }
3345 
3346  osize = length;
3347  read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3348  checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3349  mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3350  ath_dbg(common, EEPROM, "checksum %x %x\n",
3351  checksum, mchecksum);
3352  if (checksum == mchecksum) {
3353  ar9300_compress_decision(ah, it, code, reference, mptr,
3354  word, length, mdata_size);
3355  } else {
3356  ath_dbg(common, EEPROM,
3357  "skipping block with bad checksum\n");
3358  }
3359  cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3360  }
3361 
3362  kfree(word);
3363  return cptr;
3364 
3365 fail:
3366  kfree(word);
3367  return -1;
3368 }
3369 
3370 /*
3371  * Restore the configuration structure by reading the eeprom.
3372  * This function destroys any existing in-memory structure
3373  * content.
3374  */
3375 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3376 {
3377  u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3378 
3379  if (ar9300_eeprom_restore_internal(ah, mptr,
3380  sizeof(struct ar9300_eeprom)) < 0)
3381  return false;
3382 
3383  return true;
3384 }
3385 
3386 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3387 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3388  struct ar9300_modal_eep_header *modal_hdr)
3389 {
3390  PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3391  PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3392  PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3393  PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3394  PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3395  PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3396  PR_EEP("Switch Settle", modal_hdr->switchSettling);
3397  PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3398  PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3399  PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3400  PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3401  PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3402  PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3403  PR_EEP("Temp Slope", modal_hdr->tempSlope);
3404  PR_EEP("Volt Slope", modal_hdr->voltSlope);
3405  PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3406  PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3407  PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3408  PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3409  PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3410  PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3411  PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3412  PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3413  PR_EEP("Quick Drop", modal_hdr->quick_drop);
3414  PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3415  PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3416  PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3417  PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3418  PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3419  PR_EEP("txClip", modal_hdr->txClip);
3420  PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3421 
3422  return len;
3423 }
3424 
3425 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3426  u8 *buf, u32 len, u32 size)
3427 {
3428  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3429  struct ar9300_base_eep_hdr *pBase;
3430 
3431  if (!dump_base_hdr) {
3432  len += snprintf(buf + len, size - len,
3433  "%20s :\n", "2GHz modal Header");
3434  len = ar9003_dump_modal_eeprom(buf, len, size,
3435  &eep->modalHeader2G);
3436  len += snprintf(buf + len, size - len,
3437  "%20s :\n", "5GHz modal Header");
3438  len = ar9003_dump_modal_eeprom(buf, len, size,
3439  &eep->modalHeader5G);
3440  goto out;
3441  }
3442 
3443  pBase = &eep->baseEepHeader;
3444 
3445  PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3446  PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3447  PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3448  PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3449  PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3450  PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3451  AR5416_OPFLAGS_11A));
3452  PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3453  AR5416_OPFLAGS_11G));
3454  PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3455  AR5416_OPFLAGS_N_2G_HT20));
3456  PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3457  AR5416_OPFLAGS_N_2G_HT40));
3458  PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3459  AR5416_OPFLAGS_N_5G_HT20));
3460  PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3461  AR5416_OPFLAGS_N_5G_HT40));
3462  PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3463  PR_EEP("RF Silent", pBase->rfSilent);
3464  PR_EEP("BT option", pBase->blueToothOptions);
3465  PR_EEP("Device Cap", pBase->deviceCap);
3466  PR_EEP("Device Type", pBase->deviceType);
3467  PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3468  PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3469  PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3470  PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3471  PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3472  PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3473  PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3474  PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3475  PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3476  PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3477  PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3478  PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3479  PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3480  PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3481  PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3482  PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3483  PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3484  PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3485  PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3486 
3487  len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3488  ah->eeprom.ar9300_eep.macAddr);
3489 out:
3490  if (len > size)
3491  len = size;
3492 
3493  return len;
3494 }
3495 #else
3496 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3497  u8 *buf, u32 len, u32 size)
3498 {
3499  return 0;
3500 }
3501 #endif
3502 
3503 /* XXX: review hardware docs */
3504 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3505 {
3506  return ah->eeprom.ar9300_eep.eepromVersion;
3507 }
3508 
3509 /* XXX: could be read from the eepromVersion, not sure yet */
3510 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3511 {
3512  return 0;
3513 }
3514 
3515 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3516  bool is2ghz)
3517 {
3518  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3519 
3520  if (is2ghz)
3521  return &eep->modalHeader2G;
3522  else
3523  return &eep->modalHeader5G;
3524 }
3525 
3526 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3527 {
3528  int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
3529 
3530  if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3531  REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3532  else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
3533  REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3534  else {
3535  REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3536  REG_RMW_FIELD(ah, AR_CH0_THERM,
3537  AR_CH0_THERM_XPABIASLVL_MSB,
3538  bias >> 2);
3539  REG_RMW_FIELD(ah, AR_CH0_THERM,
3540  AR_CH0_THERM_XPASHORT2GND, 1);
3541  }
3542 }
3543 
3544 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
3545 {
3546  return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
3547 }
3548 
3549 
3550 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3551 {
3552  return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
3553 }
3554 
3555 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3556 {
3557  return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
3558 }
3559 
3560 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3561  bool is2ghz)
3562 {
3563  __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
3564  return le16_to_cpu(val);
3565 }
3566 
3567 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3568 {
3569  struct ath9k_hw_capabilities *pCap = &ah->caps;
3570  int chain;
3571  u32 regval;
3572  static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3573  AR_PHY_SWITCH_CHAIN_0,
3574  AR_PHY_SWITCH_CHAIN_1,
3575  AR_PHY_SWITCH_CHAIN_2,
3576  };
3577 
3578  u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3579 
3580  if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3581  REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3582  AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3583  } else if (AR_SREV_9550(ah)) {
3584  REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3585  AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3586  } else
3587  REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3588  AR_SWITCH_TABLE_COM_ALL, value);
3589 
3590 
3591  /*
3592  * AR9462 defines new switch table for BT/WLAN,
3593  * here's new field name in XXX.ref for both 2G and 5G.
3594  * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3595  * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3596  * SWITCH_TABLE_COM_SPDT_WLAN_RX
3597  *
3598  * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3599  * SWITCH_TABLE_COM_SPDT_WLAN_TX
3600  *
3601  * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3602  * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3603  */
3604  if (AR_SREV_9462_20_OR_LATER(ah)) {
3605  value = ar9003_switch_com_spdt_get(ah, is2ghz);
3606  REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3607  AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3608  REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3609  }
3610 
3611  value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3612  REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3613 
3614  for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3615  if ((ah->rxchainmask & BIT(chain)) ||
3616  (ah->txchainmask & BIT(chain))) {
3617  value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3618  is2ghz);
3619  REG_RMW_FIELD(ah, switch_chain_reg[chain],
3620  AR_SWITCH_TABLE_ALL, value);
3621  }
3622  }
3623 
3624  if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3625  value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3626  /*
3627  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3628  * are the fields present
3629  */
3630  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3631  regval &= (~AR_ANT_DIV_CTRL_ALL);
3632  regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3633  /* enable_lnadiv */
3634  regval &= (~AR_PHY_ANT_DIV_LNADIV);
3635  regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
3636 
3637  if (AR_SREV_9565(ah)) {
3638  if (ah->shared_chain_lnadiv) {
3639  regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);
3640  } else {
3641  regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);
3642  regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);
3643  }
3644  }
3645 
3646  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3647 
3648  /*enable fast_div */
3649  regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3650  regval &= (~AR_FAST_DIV_ENABLE);
3651  regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
3652  REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3653 
3654  if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
3655  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3656  /*
3657  * clear bits 25-30 main_lnaconf, alt_lnaconf,
3658  * main_tb, alt_tb
3659  */
3660  regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
3661  AR_PHY_ANT_DIV_ALT_LNACONF |
3662  AR_PHY_ANT_DIV_ALT_GAINTB |
3663  AR_PHY_ANT_DIV_MAIN_GAINTB));
3664  /* by default use LNA1 for the main antenna */
3665  regval |= (AR_PHY_ANT_DIV_LNA1 <<
3666  AR_PHY_ANT_DIV_MAIN_LNACONF_S);
3667  regval |= (AR_PHY_ANT_DIV_LNA2 <<
3668  AR_PHY_ANT_DIV_ALT_LNACONF_S);
3669  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3670  }
3671  }
3672 }
3673 
3674 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3675 {
3676  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3677  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3678  int drive_strength;
3679  unsigned long reg;
3680 
3681  drive_strength = pBase->miscConfiguration & BIT(0);
3682  if (!drive_strength)
3683  return;
3684 
3685  reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3686  reg &= ~0x00ffffc0;
3687  reg |= 0x5 << 21;
3688  reg |= 0x5 << 18;
3689  reg |= 0x5 << 15;
3690  reg |= 0x5 << 12;
3691  reg |= 0x5 << 9;
3692  reg |= 0x5 << 6;
3693  REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3694 
3695  reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3696  reg &= ~0xffffffe0;
3697  reg |= 0x5 << 29;
3698  reg |= 0x5 << 26;
3699  reg |= 0x5 << 23;
3700  reg |= 0x5 << 20;
3701  reg |= 0x5 << 17;
3702  reg |= 0x5 << 14;
3703  reg |= 0x5 << 11;
3704  reg |= 0x5 << 8;
3705  reg |= 0x5 << 5;
3706  REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3707 
3708  reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3709  reg &= ~0xff800000;
3710  reg |= 0x5 << 29;
3711  reg |= 0x5 << 26;
3712  reg |= 0x5 << 23;
3713  REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3714 }
3715 
3716 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3717  struct ath9k_channel *chan)
3718 {
3719  int f[3], t[3];
3720  u16 value;
3721  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3722 
3723  if (chain >= 0 && chain < 3) {
3724  if (IS_CHAN_2GHZ(chan))
3725  return eep->modalHeader2G.xatten1DB[chain];
3726  else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3727  t[0] = eep->base_ext2.xatten1DBLow[chain];
3728  f[0] = 5180;
3729  t[1] = eep->modalHeader5G.xatten1DB[chain];
3730  f[1] = 5500;
3731  t[2] = eep->base_ext2.xatten1DBHigh[chain];
3732  f[2] = 5785;
3733  value = ar9003_hw_power_interpolate((s32) chan->channel,
3734  f, t, 3);
3735  return value;
3736  } else
3737  return eep->modalHeader5G.xatten1DB[chain];
3738  }
3739 
3740  return 0;
3741 }
3742 
3743 
3744 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3745  struct ath9k_channel *chan)
3746 {
3747  int f[3], t[3];
3748  u16 value;
3749  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3750 
3751  if (chain >= 0 && chain < 3) {
3752  if (IS_CHAN_2GHZ(chan))
3753  return eep->modalHeader2G.xatten1Margin[chain];
3754  else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3755  t[0] = eep->base_ext2.xatten1MarginLow[chain];
3756  f[0] = 5180;
3757  t[1] = eep->modalHeader5G.xatten1Margin[chain];
3758  f[1] = 5500;
3759  t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3760  f[2] = 5785;
3761  value = ar9003_hw_power_interpolate((s32) chan->channel,
3762  f, t, 3);
3763  return value;
3764  } else
3765  return eep->modalHeader5G.xatten1Margin[chain];
3766  }
3767 
3768  return 0;
3769 }
3770 
3771 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3772 {
3773  int i;
3774  u16 value;
3775  unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3776  AR_PHY_EXT_ATTEN_CTL_1,
3777  AR_PHY_EXT_ATTEN_CTL_2,
3778  };
3779 
3780  /* Test value. if 0 then attenuation is unused. Don't load anything. */
3781  for (i = 0; i < 3; i++) {
3782  if (ah->txchainmask & BIT(i)) {
3783  value = ar9003_hw_atten_chain_get(ah, i, chan);
3784  REG_RMW_FIELD(ah, ext_atten_reg[i],
3785  AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3786 
3787  value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3788  REG_RMW_FIELD(ah, ext_atten_reg[i],
3789  AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3790  value);
3791  }
3792  }
3793 }
3794 
3795 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3796 {
3797  int timeout = 100;
3798 
3799  while (pmu_set != REG_READ(ah, pmu_reg)) {
3800  if (timeout-- == 0)
3801  return false;
3802  REG_WRITE(ah, pmu_reg, pmu_set);
3803  udelay(10);
3804  }
3805 
3806  return true;
3807 }
3808 
3809 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3810 {
3811  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3812  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3813  u32 reg_val;
3814 
3815  if (pBase->featureEnable & BIT(4)) {
3816  if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3817  int reg_pmu_set;
3818 
3819  reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3820  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3821  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3822  return;
3823 
3824  if (AR_SREV_9330(ah)) {
3825  if (ah->is_clk_25mhz) {
3826  reg_pmu_set = (3 << 1) | (8 << 4) |
3827  (3 << 8) | (1 << 14) |
3828  (6 << 17) | (1 << 20) |
3829  (3 << 24);
3830  } else {
3831  reg_pmu_set = (4 << 1) | (7 << 4) |
3832  (3 << 8) | (1 << 14) |
3833  (6 << 17) | (1 << 20) |
3834  (3 << 24);
3835  }
3836  } else {
3837  reg_pmu_set = (5 << 1) | (7 << 4) |
3838  (2 << 8) | (2 << 14) |
3839  (6 << 17) | (1 << 20) |
3840  (3 << 24) | (1 << 28);
3841  }
3842 
3843  REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3844  if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3845  return;
3846 
3847  reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3848  | (4 << 26);
3849  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3850  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3851  return;
3852 
3853  reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3854  | (1 << 21);
3855  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3856  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3857  return;
3858  } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3859  reg_val = le32_to_cpu(pBase->swreg);
3860  REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3861  } else {
3862  /* Internal regulator is ON. Write swreg register. */
3863  reg_val = le32_to_cpu(pBase->swreg);
3864  REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3865  REG_READ(ah, AR_RTC_REG_CONTROL1) &
3866  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3867  REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3868  /* Set REG_CONTROL1.SWREG_PROGRAM */
3869  REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3870  REG_READ(ah,
3871  AR_RTC_REG_CONTROL1) |
3872  AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3873  }
3874  } else {
3875  if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3876  REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3877  while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3878  AR_PHY_PMU2_PGM))
3879  udelay(10);
3880 
3881  REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3882  while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3883  AR_PHY_PMU1_PWD))
3884  udelay(10);
3885  REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3886  while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3887  AR_PHY_PMU2_PGM))
3888  udelay(10);
3889  } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
3890  REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3891  else {
3892  reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3893  AR_RTC_FORCE_SWREG_PRD;
3894  REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3895  }
3896  }
3897 
3898 }
3899 
3900 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3901 {
3902  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3903  u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3904 
3905  if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3906  return;
3907 
3908  if (eep->baseEepHeader.featureEnable & 0x40) {
3909  tuning_caps_param &= 0x7f;
3910  REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3911  tuning_caps_param);
3912  REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3913  tuning_caps_param);
3914  }
3915 }
3916 
3917 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3918 {
3919  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3920  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3921  int quick_drop;
3922  s32 t[3], f[3] = {5180, 5500, 5785};
3923 
3924  if (!(pBase->miscConfiguration & BIT(1)))
3925  return;
3926 
3927  if (freq < 4000)
3928  quick_drop = eep->modalHeader2G.quick_drop;
3929  else {
3930  t[0] = eep->base_ext1.quick_drop_low;
3931  t[1] = eep->modalHeader5G.quick_drop;
3932  t[2] = eep->base_ext1.quick_drop_high;
3933  quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3934  }
3935  REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3936 }
3937 
3938 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
3939 {
3940  u32 value;
3941 
3942  value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
3943 
3944  REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3945  AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3946  REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3947  AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3948 }
3949 
3950 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
3951 {
3952  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3953  u8 xpa_ctl;
3954 
3955  if (!(eep->baseEepHeader.featureEnable & 0x80))
3956  return;
3957 
3958  if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
3959  return;
3960 
3961  xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
3962  if (is2ghz)
3963  REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3964  AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
3965  else
3966  REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3967  AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
3968 }
3969 
3970 static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
3971 {
3972  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3973  u8 bias;
3974 
3975  if (!(eep->baseEepHeader.featureEnable & 0x40))
3976  return;
3977 
3978  if (!AR_SREV_9300(ah))
3979  return;
3980 
3981  bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
3982  REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3983  bias & 0x3);
3984  bias >>= 2;
3985  REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3986  bias & 0x3);
3987  bias >>= 2;
3988  REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3989  bias & 0x3);
3990 }
3991 
3992 static int ar9003_hw_get_thermometer(struct ath_hw *ah)
3993 {
3994  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3995  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3996  int thermometer = (pBase->miscConfiguration >> 1) & 0x3;
3997 
3998  return --thermometer;
3999 }
4000 
4001 static void ar9003_hw_thermometer_apply(struct ath_hw *ah)
4002 {
4003  int thermometer = ar9003_hw_get_thermometer(ah);
4004  u8 therm_on = (thermometer < 0) ? 0 : 1;
4005 
4006  REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4007  AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4008  if (ah->caps.tx_chainmask & BIT(1))
4009  REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4010  AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4011  if (ah->caps.tx_chainmask & BIT(2))
4012  REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4013  AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4014 
4015  therm_on = (thermometer < 0) ? 0 : (thermometer == 0);
4016  REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4017  AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4018  if (ah->caps.tx_chainmask & BIT(1)) {
4019  therm_on = (thermometer < 0) ? 0 : (thermometer == 1);
4020  REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4021  AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4022  }
4023  if (ah->caps.tx_chainmask & BIT(2)) {
4024  therm_on = (thermometer < 0) ? 0 : (thermometer == 2);
4025  REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4026  AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4027  }
4028 }
4029 
4030 static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
4031 {
4032  u32 data, ko, kg;
4033 
4034  if (!AR_SREV_9462_20(ah))
4035  return;
4036  ar9300_otp_read_word(ah, 1, &data);
4037  ko = data & 0xff;
4038  kg = (data >> 8) & 0xff;
4039  if (ko || kg) {
4040  REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4041  AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko);
4042  REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4043  AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN,
4044  kg + 256);
4045  }
4046 }
4047 
4048 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
4049  struct ath9k_channel *chan)
4050 {
4051  bool is2ghz = IS_CHAN_2GHZ(chan);
4052  ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
4053  ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
4054  ar9003_hw_ant_ctrl_apply(ah, is2ghz);
4055  ar9003_hw_drive_strength_apply(ah);
4056  ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
4057  ar9003_hw_atten_apply(ah, chan);
4058  ar9003_hw_quick_drop_apply(ah, chan->channel);
4059  if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
4060  ar9003_hw_internal_regulator_apply(ah);
4061  ar9003_hw_apply_tuning_caps(ah);
4062  ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
4063  ar9003_hw_thermometer_apply(ah);
4064  ar9003_hw_thermo_cal_apply(ah);
4065 }
4066 
4067 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
4068  struct ath9k_channel *chan)
4069 {
4070 }
4071 
4072 /*
4073  * Returns the interpolated y value corresponding to the specified x value
4074  * from the np ordered pairs of data (px,py).
4075  * The pairs do not have to be in any order.
4076  * If the specified x value is less than any of the px,
4077  * the returned y value is equal to the py for the lowest px.
4078  * If the specified x value is greater than any of the px,
4079  * the returned y value is equal to the py for the highest px.
4080  */
4081 static int ar9003_hw_power_interpolate(int32_t x,
4082  int32_t *px, int32_t *py, u_int16_t np)
4083 {
4084  int ip = 0;
4085  int lx = 0, ly = 0, lhave = 0;
4086  int hx = 0, hy = 0, hhave = 0;
4087  int dx = 0;
4088  int y = 0;
4089 
4090  lhave = 0;
4091  hhave = 0;
4092 
4093  /* identify best lower and higher x calibration measurement */
4094  for (ip = 0; ip < np; ip++) {
4095  dx = x - px[ip];
4096 
4097  /* this measurement is higher than our desired x */
4098  if (dx <= 0) {
4099  if (!hhave || dx > (x - hx)) {
4100  /* new best higher x measurement */
4101  hx = px[ip];
4102  hy = py[ip];
4103  hhave = 1;
4104  }
4105  }
4106  /* this measurement is lower than our desired x */
4107  if (dx >= 0) {
4108  if (!lhave || dx < (x - lx)) {
4109  /* new best lower x measurement */
4110  lx = px[ip];
4111  ly = py[ip];
4112  lhave = 1;
4113  }
4114  }
4115  }
4116 
4117  /* the low x is good */
4118  if (lhave) {
4119  /* so is the high x */
4120  if (hhave) {
4121  /* they're the same, so just pick one */
4122  if (hx == lx)
4123  y = ly;
4124  else /* interpolate */
4125  y = interpolate(x, lx, hx, ly, hy);
4126  } else /* only low is good, use it */
4127  y = ly;
4128  } else if (hhave) /* only high is good, use it */
4129  y = hy;
4130  else /* nothing is good,this should never happen unless np=0, ???? */
4131  y = -(1 << 30);
4132  return y;
4133 }
4134 
4135 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4136  u16 rateIndex, u16 freq, bool is2GHz)
4137 {
4138  u16 numPiers, i;
4139  s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4140  s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4141  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4142  struct cal_tgt_pow_legacy *pEepromTargetPwr;
4143  u8 *pFreqBin;
4144 
4145  if (is2GHz) {
4146  numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4147  pEepromTargetPwr = eep->calTargetPower2G;
4148  pFreqBin = eep->calTarget_freqbin_2G;
4149  } else {
4150  numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4151  pEepromTargetPwr = eep->calTargetPower5G;
4152  pFreqBin = eep->calTarget_freqbin_5G;
4153  }
4154 
4155  /*
4156  * create array of channels and targetpower from
4157  * targetpower piers stored on eeprom
4158  */
4159  for (i = 0; i < numPiers; i++) {
4160  freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4161  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4162  }
4163 
4164  /* interpolate to get target power for given frequency */
4165  return (u8) ar9003_hw_power_interpolate((s32) freq,
4166  freqArray,
4167  targetPowerArray, numPiers);
4168 }
4169 
4170 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4171  u16 rateIndex,
4172  u16 freq, bool is2GHz)
4173 {
4174  u16 numPiers, i;
4175  s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4176  s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4177  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4178  struct cal_tgt_pow_ht *pEepromTargetPwr;
4179  u8 *pFreqBin;
4180 
4181  if (is2GHz) {
4182  numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4183  pEepromTargetPwr = eep->calTargetPower2GHT20;
4184  pFreqBin = eep->calTarget_freqbin_2GHT20;
4185  } else {
4186  numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4187  pEepromTargetPwr = eep->calTargetPower5GHT20;
4188  pFreqBin = eep->calTarget_freqbin_5GHT20;
4189  }
4190 
4191  /*
4192  * create array of channels and targetpower
4193  * from targetpower piers stored on eeprom
4194  */
4195  for (i = 0; i < numPiers; i++) {
4196  freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4197  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4198  }
4199 
4200  /* interpolate to get target power for given frequency */
4201  return (u8) ar9003_hw_power_interpolate((s32) freq,
4202  freqArray,
4203  targetPowerArray, numPiers);
4204 }
4205 
4206 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4207  u16 rateIndex,
4208  u16 freq, bool is2GHz)
4209 {
4210  u16 numPiers, i;
4211  s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4212  s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4213  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4214  struct cal_tgt_pow_ht *pEepromTargetPwr;
4215  u8 *pFreqBin;
4216 
4217  if (is2GHz) {
4218  numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4219  pEepromTargetPwr = eep->calTargetPower2GHT40;
4220  pFreqBin = eep->calTarget_freqbin_2GHT40;
4221  } else {
4222  numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4223  pEepromTargetPwr = eep->calTargetPower5GHT40;
4224  pFreqBin = eep->calTarget_freqbin_5GHT40;
4225  }
4226 
4227  /*
4228  * create array of channels and targetpower from
4229  * targetpower piers stored on eeprom
4230  */
4231  for (i = 0; i < numPiers; i++) {
4232  freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4233  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4234  }
4235 
4236  /* interpolate to get target power for given frequency */
4237  return (u8) ar9003_hw_power_interpolate((s32) freq,
4238  freqArray,
4239  targetPowerArray, numPiers);
4240 }
4241 
4242 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4243  u16 rateIndex, u16 freq)
4244 {
4245  u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4246  s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4247  s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4248  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4249  struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4250  u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4251 
4252  /*
4253  * create array of channels and targetpower from
4254  * targetpower piers stored on eeprom
4255  */
4256  for (i = 0; i < numPiers; i++) {
4257  freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4258  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4259  }
4260 
4261  /* interpolate to get target power for given frequency */
4262  return (u8) ar9003_hw_power_interpolate((s32) freq,
4263  freqArray,
4264  targetPowerArray, numPiers);
4265 }
4266 
4267 /* Set tx power registers to array of values passed in */
4268 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4269 {
4270 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4271  /* make sure forced gain is not set */
4272  REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4273 
4274  /* Write the OFDM power per rate set */
4275 
4276  /* 6 (LSB), 9, 12, 18 (MSB) */
4277  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4278  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4279  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4280  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4281  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4282 
4283  /* 24 (LSB), 36, 48, 54 (MSB) */
4284  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4285  POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4286  POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4287  POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4288  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4289 
4290  /* Write the CCK power per rate set */
4291 
4292  /* 1L (LSB), reserved, 2L, 2S (MSB) */
4293  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4294  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4295  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4296  /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4297  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4298 
4299  /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4300  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4301  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4302  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4303  POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4304  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4305  );
4306 
4307  /* Write the power for duplicated frames - HT40 */
4308 
4309  /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4310  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4311  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4312  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4313  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4314  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4315  );
4316 
4317  /* Write the HT20 power per rate set */
4318 
4319  /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4320  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4321  POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4322  POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4323  POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4324  POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4325  );
4326 
4327  /* 6 (LSB), 7, 12, 13 (MSB) */
4328  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4329  POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4330  POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4331  POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4332  POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4333  );
4334 
4335  /* 14 (LSB), 15, 20, 21 */
4336  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4337  POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4338  POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4339  POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4340  POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4341  );
4342 
4343  /* Mixed HT20 and HT40 rates */
4344 
4345  /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4346  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4347  POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4348  POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4349  POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4350  POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4351  );
4352 
4353  /*
4354  * Write the HT40 power per rate set
4355  * correct PAR difference between HT40 and HT20/LEGACY
4356  * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4357  */
4358  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4359  POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4360  POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4361  POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4362  POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4363  );
4364 
4365  /* 6 (LSB), 7, 12, 13 (MSB) */
4366  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4367  POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4368  POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4369  POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4370  POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4371  );
4372 
4373  /* 14 (LSB), 15, 20, 21 */
4374  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4375  POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4376  POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4377  POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4378  POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4379  );
4380 
4381  return 0;
4382 #undef POW_SM
4383 }
4384 
4385 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4386  u8 *targetPowerValT2,
4387  bool is2GHz)
4388 {
4389  targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4390  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4391  is2GHz);
4392  targetPowerValT2[ALL_TARGET_LEGACY_36] =
4393  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4394  is2GHz);
4395  targetPowerValT2[ALL_TARGET_LEGACY_48] =
4396  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4397  is2GHz);
4398  targetPowerValT2[ALL_TARGET_LEGACY_54] =
4399  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4400  is2GHz);
4401 }
4402 
4403 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4404  u8 *targetPowerValT2)
4405 {
4406  targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4407  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4408  freq);
4409  targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4410  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4411  targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4412  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4413  targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4414  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4415 }
4416 
4417 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4418  u8 *targetPowerValT2, bool is2GHz)
4419 {
4420  targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4421  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4422  is2GHz);
4423  targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4424  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4425  freq, is2GHz);
4426  targetPowerValT2[ALL_TARGET_HT20_4] =
4427  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4428  is2GHz);
4429  targetPowerValT2[ALL_TARGET_HT20_5] =
4430  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4431  is2GHz);
4432  targetPowerValT2[ALL_TARGET_HT20_6] =
4433  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4434  is2GHz);
4435  targetPowerValT2[ALL_TARGET_HT20_7] =
4436  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4437  is2GHz);
4438  targetPowerValT2[ALL_TARGET_HT20_12] =
4439  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4440  is2GHz);
4441  targetPowerValT2[ALL_TARGET_HT20_13] =
4442  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4443  is2GHz);
4444  targetPowerValT2[ALL_TARGET_HT20_14] =
4445  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4446  is2GHz);
4447  targetPowerValT2[ALL_TARGET_HT20_15] =
4448  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4449  is2GHz);
4450  targetPowerValT2[ALL_TARGET_HT20_20] =
4451  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4452  is2GHz);
4453  targetPowerValT2[ALL_TARGET_HT20_21] =
4454  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4455  is2GHz);
4456  targetPowerValT2[ALL_TARGET_HT20_22] =
4457  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4458  is2GHz);
4459  targetPowerValT2[ALL_TARGET_HT20_23] =
4460  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4461  is2GHz);
4462 }
4463 
4464 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4465  u16 freq,
4466  u8 *targetPowerValT2,
4467  bool is2GHz)
4468 {
4469  /* XXX: hard code for now, need to get from eeprom struct */
4470  u8 ht40PowerIncForPdadc = 0;
4471 
4472  targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4473  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4474  is2GHz) + ht40PowerIncForPdadc;
4475  targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4476  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4477  freq,
4478  is2GHz) + ht40PowerIncForPdadc;
4479  targetPowerValT2[ALL_TARGET_HT40_4] =
4480  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4481  is2GHz) + ht40PowerIncForPdadc;
4482  targetPowerValT2[ALL_TARGET_HT40_5] =
4483  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4484  is2GHz) + ht40PowerIncForPdadc;
4485  targetPowerValT2[ALL_TARGET_HT40_6] =
4486  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4487  is2GHz) + ht40PowerIncForPdadc;
4488  targetPowerValT2[ALL_TARGET_HT40_7] =
4489  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4490  is2GHz) + ht40PowerIncForPdadc;
4491  targetPowerValT2[ALL_TARGET_HT40_12] =
4492  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4493  is2GHz) + ht40PowerIncForPdadc;
4494  targetPowerValT2[ALL_TARGET_HT40_13] =
4495  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4496  is2GHz) + ht40PowerIncForPdadc;
4497  targetPowerValT2[ALL_TARGET_HT40_14] =
4498  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4499  is2GHz) + ht40PowerIncForPdadc;
4500  targetPowerValT2[ALL_TARGET_HT40_15] =
4501  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4502  is2GHz) + ht40PowerIncForPdadc;
4503  targetPowerValT2[ALL_TARGET_HT40_20] =
4504  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4505  is2GHz) + ht40PowerIncForPdadc;
4506  targetPowerValT2[ALL_TARGET_HT40_21] =
4507  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4508  is2GHz) + ht40PowerIncForPdadc;
4509  targetPowerValT2[ALL_TARGET_HT40_22] =
4510  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4511  is2GHz) + ht40PowerIncForPdadc;
4512  targetPowerValT2[ALL_TARGET_HT40_23] =
4513  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4514  is2GHz) + ht40PowerIncForPdadc;
4515 }
4516 
4517 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4518  struct ath9k_channel *chan,
4519  u8 *targetPowerValT2)
4520 {
4521  bool is2GHz = IS_CHAN_2GHZ(chan);
4522  unsigned int i = 0;
4523  struct ath_common *common = ath9k_hw_common(ah);
4524  u16 freq = chan->channel;
4525 
4526  if (is2GHz)
4527  ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4528 
4529  ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4530  ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4531 
4532  if (IS_CHAN_HT40(chan))
4533  ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4534  is2GHz);
4535 
4536  for (i = 0; i < ar9300RateSize; i++) {
4537  ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4538  i, targetPowerValT2[i]);
4539  }
4540 }
4541 
4542 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4543  int mode,
4544  int ipier,
4545  int ichain,
4546  int *pfrequency,
4547  int *pcorrection,
4548  int *ptemperature, int *pvoltage)
4549 {
4550  u8 *pCalPier;
4551  struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4552  int is2GHz;
4553  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4554  struct ath_common *common = ath9k_hw_common(ah);
4555 
4556  if (ichain >= AR9300_MAX_CHAINS) {
4557  ath_dbg(common, EEPROM,
4558  "Invalid chain index, must be less than %d\n",
4559  AR9300_MAX_CHAINS);
4560  return -1;
4561  }
4562 
4563  if (mode) { /* 5GHz */
4564  if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4565  ath_dbg(common, EEPROM,
4566  "Invalid 5GHz cal pier index, must be less than %d\n",
4567  AR9300_NUM_5G_CAL_PIERS);
4568  return -1;
4569  }
4570  pCalPier = &(eep->calFreqPier5G[ipier]);
4571  pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4572  is2GHz = 0;
4573  } else {
4574  if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4575  ath_dbg(common, EEPROM,
4576  "Invalid 2GHz cal pier index, must be less than %d\n",
4577  AR9300_NUM_2G_CAL_PIERS);
4578  return -1;
4579  }
4580 
4581  pCalPier = &(eep->calFreqPier2G[ipier]);
4582  pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4583  is2GHz = 1;
4584  }
4585 
4586  *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
4587  *pcorrection = pCalPierStruct->refPower;
4588  *ptemperature = pCalPierStruct->tempMeas;
4589  *pvoltage = pCalPierStruct->voltMeas;
4590 
4591  return 0;
4592 }
4593 
4594 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4595  int frequency,
4596  int *correction,
4597  int *voltage, int *temperature)
4598 {
4599  int tempSlope = 0;
4600  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4601  int f[8], t[8], i;
4602 
4603  REG_RMW(ah, AR_PHY_TPC_11_B0,
4604  (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4605  AR_PHY_TPC_OLPC_GAIN_DELTA);
4606  if (ah->caps.tx_chainmask & BIT(1))
4607  REG_RMW(ah, AR_PHY_TPC_11_B1,
4608  (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4609  AR_PHY_TPC_OLPC_GAIN_DELTA);
4610  if (ah->caps.tx_chainmask & BIT(2))
4611  REG_RMW(ah, AR_PHY_TPC_11_B2,
4612  (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4613  AR_PHY_TPC_OLPC_GAIN_DELTA);
4614 
4615  /* enable open loop power control on chip */
4616  REG_RMW(ah, AR_PHY_TPC_6_B0,
4617  (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4618  AR_PHY_TPC_6_ERROR_EST_MODE);
4619  if (ah->caps.tx_chainmask & BIT(1))
4620  REG_RMW(ah, AR_PHY_TPC_6_B1,
4621  (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4622  AR_PHY_TPC_6_ERROR_EST_MODE);
4623  if (ah->caps.tx_chainmask & BIT(2))
4624  REG_RMW(ah, AR_PHY_TPC_6_B2,
4625  (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4626  AR_PHY_TPC_6_ERROR_EST_MODE);
4627 
4628  /*
4629  * enable temperature compensation
4630  * Need to use register names
4631  */
4632  if (frequency < 4000)
4633  tempSlope = eep->modalHeader2G.tempSlope;
4634  else if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
4635  for (i = 0; i < 8; i++) {
4636  t[i] = eep->base_ext1.tempslopextension[i];
4637  f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
4638  }
4639  tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4640  f, t, 8);
4641  } else if (eep->base_ext2.tempSlopeLow != 0) {
4642  t[0] = eep->base_ext2.tempSlopeLow;
4643  f[0] = 5180;
4644  t[1] = eep->modalHeader5G.tempSlope;
4645  f[1] = 5500;
4646  t[2] = eep->base_ext2.tempSlopeHigh;
4647  f[2] = 5785;
4648  tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4649  f, t, 3);
4650  } else
4651  tempSlope = eep->modalHeader5G.tempSlope;
4652 
4653  REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4654 
4655  if (AR_SREV_9462_20(ah))
4656  REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4657  AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4658 
4659 
4660  REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4661  temperature[0]);
4662 
4663  return 0;
4664 }
4665 
4666 /* Apply the recorded correction values. */
4667 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4668 {
4669  int ichain, ipier, npier;
4670  int mode;
4671  int lfrequency[AR9300_MAX_CHAINS],
4672  lcorrection[AR9300_MAX_CHAINS],
4673  ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4674  int hfrequency[AR9300_MAX_CHAINS],
4675  hcorrection[AR9300_MAX_CHAINS],
4676  htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4677  int fdiff;
4678  int correction[AR9300_MAX_CHAINS],
4679  voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4680  int pfrequency, pcorrection, ptemperature, pvoltage;
4681  struct ath_common *common = ath9k_hw_common(ah);
4682 
4683  mode = (frequency >= 4000);
4684  if (mode)
4685  npier = AR9300_NUM_5G_CAL_PIERS;
4686  else
4687  npier = AR9300_NUM_2G_CAL_PIERS;
4688 
4689  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4690  lfrequency[ichain] = 0;
4691  hfrequency[ichain] = 100000;
4692  }
4693  /* identify best lower and higher frequency calibration measurement */
4694  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4695  for (ipier = 0; ipier < npier; ipier++) {
4696  if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4697  &pfrequency, &pcorrection,
4698  &ptemperature, &pvoltage)) {
4699  fdiff = frequency - pfrequency;
4700 
4701  /*
4702  * this measurement is higher than
4703  * our desired frequency
4704  */
4705  if (fdiff <= 0) {
4706  if (hfrequency[ichain] <= 0 ||
4707  hfrequency[ichain] >= 100000 ||
4708  fdiff >
4709  (frequency - hfrequency[ichain])) {
4710  /*
4711  * new best higher
4712  * frequency measurement
4713  */
4714  hfrequency[ichain] = pfrequency;
4715  hcorrection[ichain] =
4716  pcorrection;
4717  htemperature[ichain] =
4718  ptemperature;
4719  hvoltage[ichain] = pvoltage;
4720  }
4721  }
4722  if (fdiff >= 0) {
4723  if (lfrequency[ichain] <= 0
4724  || fdiff <
4725  (frequency - lfrequency[ichain])) {
4726  /*
4727  * new best lower
4728  * frequency measurement
4729  */
4730  lfrequency[ichain] = pfrequency;
4731  lcorrection[ichain] =
4732  pcorrection;
4733  ltemperature[ichain] =
4734  ptemperature;
4735  lvoltage[ichain] = pvoltage;
4736  }
4737  }
4738  }
4739  }
4740  }
4741 
4742  /* interpolate */
4743  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4744  ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4745  ichain, frequency, lfrequency[ichain],
4746  lcorrection[ichain], hfrequency[ichain],
4747  hcorrection[ichain]);
4748  /* they're the same, so just pick one */
4749  if (hfrequency[ichain] == lfrequency[ichain]) {
4750  correction[ichain] = lcorrection[ichain];
4751  voltage[ichain] = lvoltage[ichain];
4752  temperature[ichain] = ltemperature[ichain];
4753  }
4754  /* the low frequency is good */
4755  else if (frequency - lfrequency[ichain] < 1000) {
4756  /* so is the high frequency, interpolate */
4757  if (hfrequency[ichain] - frequency < 1000) {
4758 
4759  correction[ichain] = interpolate(frequency,
4760  lfrequency[ichain],
4761  hfrequency[ichain],
4762  lcorrection[ichain],
4763  hcorrection[ichain]);
4764 
4765  temperature[ichain] = interpolate(frequency,
4766  lfrequency[ichain],
4767  hfrequency[ichain],
4768  ltemperature[ichain],
4769  htemperature[ichain]);
4770 
4771  voltage[ichain] = interpolate(frequency,
4772  lfrequency[ichain],
4773  hfrequency[ichain],
4774  lvoltage[ichain],
4775  hvoltage[ichain]);
4776  }
4777  /* only low is good, use it */
4778  else {
4779  correction[ichain] = lcorrection[ichain];
4780  temperature[ichain] = ltemperature[ichain];
4781  voltage[ichain] = lvoltage[ichain];
4782  }
4783  }
4784  /* only high is good, use it */
4785  else if (hfrequency[ichain] - frequency < 1000) {
4786  correction[ichain] = hcorrection[ichain];
4787  temperature[ichain] = htemperature[ichain];
4788  voltage[ichain] = hvoltage[ichain];
4789  } else { /* nothing is good, presume 0???? */
4790  correction[ichain] = 0;
4791  temperature[ichain] = 0;
4792  voltage[ichain] = 0;
4793  }
4794  }
4795 
4796  ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4797  temperature);
4798 
4799  ath_dbg(common, EEPROM,
4800  "for frequency=%d, calibration correction = %d %d %d\n",
4801  frequency, correction[0], correction[1], correction[2]);
4802 
4803  return 0;
4804 }
4805 
4806 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4807  int idx,
4808  int edge,
4809  bool is2GHz)
4810 {
4811  struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4812  struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4813 
4814  if (is2GHz)
4815  return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4816  else
4817  return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4818 }
4819 
4820 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4821  int idx,
4822  unsigned int edge,
4823  u16 freq,
4824  bool is2GHz)
4825 {
4826  struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4827  struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4828 
4829  u8 *ctl_freqbin = is2GHz ?
4830  &eep->ctl_freqbin_2G[idx][0] :
4831  &eep->ctl_freqbin_5G[idx][0];
4832 
4833  if (is2GHz) {
4834  if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4835  CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4836  return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4837  } else {
4838  if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4839  CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4840  return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4841  }
4842 
4843  return MAX_RATE_POWER;
4844 }
4845 
4846 /*
4847  * Find the maximum conformance test limit for the given channel and CTL info
4848  */
4849 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4850  u16 freq, int idx, bool is2GHz)
4851 {
4852  u16 twiceMaxEdgePower = MAX_RATE_POWER;
4853  u8 *ctl_freqbin = is2GHz ?
4854  &eep->ctl_freqbin_2G[idx][0] :
4855  &eep->ctl_freqbin_5G[idx][0];
4856  u16 num_edges = is2GHz ?
4857  AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4858  unsigned int edge;
4859 
4860  /* Get the edge power */
4861  for (edge = 0;
4862  (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4863  edge++) {
4864  /*
4865  * If there's an exact channel match or an inband flag set
4866  * on the lower channel use the given rdEdgePower
4867  */
4868  if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4869  twiceMaxEdgePower =
4870  ar9003_hw_get_direct_edge_power(eep, idx,
4871  edge, is2GHz);
4872  break;
4873  } else if ((edge > 0) &&
4874  (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4875  is2GHz))) {
4876  twiceMaxEdgePower =
4877  ar9003_hw_get_indirect_edge_power(eep, idx,
4878  edge, freq,
4879  is2GHz);
4880  /*
4881  * Leave loop - no more affecting edges possible in
4882  * this monotonic increasing list
4883  */
4884  break;
4885  }
4886  }
4887  return twiceMaxEdgePower;
4888 }
4889 
4890 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4891  struct ath9k_channel *chan,
4892  u8 *pPwrArray, u16 cfgCtl,
4893  u8 antenna_reduction,
4894  u16 powerLimit)
4895 {
4896  struct ath_common *common = ath9k_hw_common(ah);
4897  struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4898  u16 twiceMaxEdgePower;
4899  int i;
4900  u16 scaledPower = 0, minCtlPower;
4901  static const u16 ctlModesFor11a[] = {
4902  CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4903  };
4904  static const u16 ctlModesFor11g[] = {
4905  CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4906  CTL_11G_EXT, CTL_2GHT40
4907  };
4908  u16 numCtlModes;
4909  const u16 *pCtlMode;
4910  u16 ctlMode, freq;
4911  struct chan_centers centers;
4912  u8 *ctlIndex;
4913  u8 ctlNum;
4914  u16 twiceMinEdgePower;
4915  bool is2ghz = IS_CHAN_2GHZ(chan);
4916 
4917  ath9k_hw_get_channel_centers(ah, chan, &centers);
4918  scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4919  antenna_reduction);
4920 
4921  if (is2ghz) {
4922  /* Setup for CTL modes */
4923  /* CTL_11B, CTL_11G, CTL_2GHT20 */
4924  numCtlModes =
4925  ARRAY_SIZE(ctlModesFor11g) -
4926  SUB_NUM_CTL_MODES_AT_2G_40;
4927  pCtlMode = ctlModesFor11g;
4928  if (IS_CHAN_HT40(chan))
4929  /* All 2G CTL's */
4930  numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4931  } else {
4932  /* Setup for CTL modes */
4933  /* CTL_11A, CTL_5GHT20 */
4934  numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4935  SUB_NUM_CTL_MODES_AT_5G_40;
4936  pCtlMode = ctlModesFor11a;
4937  if (IS_CHAN_HT40(chan))
4938  /* All 5G CTL's */
4939  numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4940  }
4941 
4942  /*
4943  * For MIMO, need to apply regulatory caps individually across
4944  * dynamically running modes: CCK, OFDM, HT20, HT40
4945  *
4946  * The outer loop walks through each possible applicable runtime mode.
4947  * The inner loop walks through each ctlIndex entry in EEPROM.
4948  * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4949  */
4950  for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4951  bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4952  (pCtlMode[ctlMode] == CTL_2GHT40);
4953  if (isHt40CtlMode)
4954  freq = centers.synth_center;
4955  else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4956  freq = centers.ext_center;
4957  else
4958  freq = centers.ctl_center;
4959 
4960  ath_dbg(common, REGULATORY,
4961  "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4962  ctlMode, numCtlModes, isHt40CtlMode,
4963  (pCtlMode[ctlMode] & EXT_ADDITIVE));
4964 
4965  /* walk through each CTL index stored in EEPROM */
4966  if (is2ghz) {
4967  ctlIndex = pEepData->ctlIndex_2G;
4968  ctlNum = AR9300_NUM_CTLS_2G;
4969  } else {
4970  ctlIndex = pEepData->ctlIndex_5G;
4971  ctlNum = AR9300_NUM_CTLS_5G;
4972  }
4973 
4974  twiceMaxEdgePower = MAX_RATE_POWER;
4975  for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4976  ath_dbg(common, REGULATORY,
4977  "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4978  i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4979  chan->channel);
4980 
4981  /*
4982  * compare test group from regulatory
4983  * channel list with test mode from pCtlMode
4984  * list
4985  */
4986  if ((((cfgCtl & ~CTL_MODE_M) |
4987  (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4988  ctlIndex[i]) ||
4989  (((cfgCtl & ~CTL_MODE_M) |
4990  (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4991  ((ctlIndex[i] & CTL_MODE_M) |
4992  SD_NO_CTL))) {
4993  twiceMinEdgePower =
4994  ar9003_hw_get_max_edge_power(pEepData,
4995  freq, i,
4996  is2ghz);
4997 
4998  if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4999  /*
5000  * Find the minimum of all CTL
5001  * edge powers that apply to
5002  * this channel
5003  */
5004  twiceMaxEdgePower =
5005  min(twiceMaxEdgePower,
5006  twiceMinEdgePower);
5007  else {
5008  /* specific */
5009  twiceMaxEdgePower = twiceMinEdgePower;
5010  break;
5011  }
5012  }
5013  }
5014 
5015  minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
5016 
5017  ath_dbg(common, REGULATORY,
5018  "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
5019  ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
5020  scaledPower, minCtlPower);
5021 
5022  /* Apply ctl mode to correct target power set */
5023  switch (pCtlMode[ctlMode]) {
5024  case CTL_11B:
5025  for (i = ALL_TARGET_LEGACY_1L_5L;
5026  i <= ALL_TARGET_LEGACY_11S; i++)
5027  pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5028  minCtlPower);
5029  break;
5030  case CTL_11A:
5031  case CTL_11G:
5032  for (i = ALL_TARGET_LEGACY_6_24;
5033  i <= ALL_TARGET_LEGACY_54; i++)
5034  pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5035  minCtlPower);
5036  break;
5037  case CTL_5GHT20:
5038  case CTL_2GHT20:
5039  for (i = ALL_TARGET_HT20_0_8_16;
5040  i <= ALL_TARGET_HT20_23; i++)
5041  pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5042  minCtlPower);
5043  break;
5044  case CTL_5GHT40:
5045  case CTL_2GHT40:
5046  for (i = ALL_TARGET_HT40_0_8_16;
5047  i <= ALL_TARGET_HT40_23; i++)
5048  pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5049  minCtlPower);
5050  break;
5051  default:
5052  break;
5053  }
5054  } /* end ctl mode checking */
5055 }
5056 
5057 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
5058 {
5059  u8 mod_idx = mcs_idx % 8;
5060 
5061  if (mod_idx <= 3)
5062  return mod_idx ? (base_pwridx + 1) : base_pwridx;
5063  else
5064  return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
5065 }
5066 
5067 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5068  struct ath9k_channel *chan, u16 cfgCtl,
5069  u8 twiceAntennaReduction,
5070  u8 powerLimit, bool test)
5071 {
5072  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5073  struct ath_common *common = ath9k_hw_common(ah);
5074  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5075  struct ar9300_modal_eep_header *modal_hdr;
5076  u8 targetPowerValT2[ar9300RateSize];
5077  u8 target_power_val_t2_eep[ar9300RateSize];
5078  unsigned int i = 0, paprd_scale_factor = 0;
5079  u8 pwr_idx, min_pwridx = 0;
5080 
5081  memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
5082 
5083  /*
5084  * Get target powers from EEPROM - our baseline for TX Power
5085  */
5086  ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
5087 
5088  if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5089  if (IS_CHAN_2GHZ(chan))
5090  modal_hdr = &eep->modalHeader2G;
5091  else
5092  modal_hdr = &eep->modalHeader5G;
5093 
5094  ah->paprd_ratemask =
5095  le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5096  AR9300_PAPRD_RATE_MASK;
5097 
5098  ah->paprd_ratemask_ht40 =
5099  le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5100  AR9300_PAPRD_RATE_MASK;
5101 
5102  paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5103  min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5104  ALL_TARGET_HT20_0_8_16;
5105 
5106  if (!ah->paprd_table_write_done) {
5107  memcpy(target_power_val_t2_eep, targetPowerValT2,
5108  sizeof(targetPowerValT2));
5109  for (i = 0; i < 24; i++) {
5110  pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5111  if (ah->paprd_ratemask & (1 << i)) {
5112  if (targetPowerValT2[pwr_idx] &&
5113  targetPowerValT2[pwr_idx] ==
5114  target_power_val_t2_eep[pwr_idx])
5115  targetPowerValT2[pwr_idx] -=
5116  paprd_scale_factor;
5117  }
5118  }
5119  }
5120  memcpy(target_power_val_t2_eep, targetPowerValT2,
5121  sizeof(targetPowerValT2));
5122  }
5123 
5124  ar9003_hw_set_power_per_rate_table(ah, chan,
5125  targetPowerValT2, cfgCtl,
5126  twiceAntennaReduction,
5127  powerLimit);
5128 
5129  if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5130  for (i = 0; i < ar9300RateSize; i++) {
5131  if ((ah->paprd_ratemask & (1 << i)) &&
5132  (abs(targetPowerValT2[i] -
5133  target_power_val_t2_eep[i]) >
5134  paprd_scale_factor)) {
5135  ah->paprd_ratemask &= ~(1 << i);
5136  ath_dbg(common, EEPROM,
5137  "paprd disabled for mcs %d\n", i);
5138  }
5139  }
5140  }
5141 
5142  regulatory->max_power_level = 0;
5143  for (i = 0; i < ar9300RateSize; i++) {
5144  if (targetPowerValT2[i] > regulatory->max_power_level)
5145  regulatory->max_power_level = targetPowerValT2[i];
5146  }
5147 
5148  ath9k_hw_update_regulatory_maxpower(ah);
5149 
5150  if (test)
5151  return;
5152 
5153  for (i = 0; i < ar9300RateSize; i++) {
5154  ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5155  i, targetPowerValT2[i]);
5156  }
5157 
5158  /* Write target power array to registers */
5159  ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5160  ar9003_hw_calibration_apply(ah, chan->channel);
5161 
5162  if (IS_CHAN_2GHZ(chan)) {
5163  if (IS_CHAN_HT40(chan))
5164  i = ALL_TARGET_HT40_0_8_16;
5165  else
5166  i = ALL_TARGET_HT20_0_8_16;
5167  } else {
5168  if (IS_CHAN_HT40(chan))
5169  i = ALL_TARGET_HT40_7;
5170  else
5171  i = ALL_TARGET_HT20_7;
5172  }
5173  ah->paprd_target_power = targetPowerValT2[i];
5174 }
5175 
5176 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5177  u16 i, bool is2GHz)
5178 {
5179  return AR_NO_SPUR;
5180 }
5181 
5182 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5183 {
5184  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5185 
5186  return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5187 }
5188 
5189 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5190 {
5191  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5192 
5193  return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5194 }
5195 
5196 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
5197 {
5198  return ar9003_modal_header(ah, is2ghz)->spurChans;
5199 }
5200 
5201 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5202  struct ath9k_channel *chan)
5203 {
5204  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5205 
5206  if (IS_CHAN_2GHZ(chan))
5207  return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5208  AR9300_PAPRD_SCALE_1);
5209  else {
5210  if (chan->channel >= 5700)
5211  return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5212  AR9300_PAPRD_SCALE_1);
5213  else if (chan->channel >= 5400)
5214  return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5215  AR9300_PAPRD_SCALE_2);
5216  else
5217  return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5218  AR9300_PAPRD_SCALE_1);
5219  }
5220 }
5221 
5222 const struct eeprom_ops eep_ar9300_ops = {
5223  .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5224  .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5225  .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5226  .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5227  .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5228  .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5229  .set_board_values = ath9k_hw_ar9300_set_board_values,
5230  .set_addac = ath9k_hw_ar9300_set_addac,
5231  .set_txpower = ath9k_hw_ar9300_set_txpower,
5232  .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5233 };
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