pmu.h

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/*
 *  linux/arch/arm/include/asm/pmu.h
 *
 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ARM_PMU_H__
#define __ARM_PMU_H__

#include <linux/interrupt.h>
#include <linux/perf_event.h>

/*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
 * @handle_irq: an optional handler which will be called from the
 *  interrupt and passed the address of the low level handler,
 *  and can be used to implement any platform specific handling
 *  before or after calling it.
 * @runtime_resume: an optional handler which will be called by the
 *  runtime PM framework following a call to pm_runtime_get().
 *  Note that if pm_runtime_get() is called more than once in
 *  succession this handler will only be called once.
 * @runtime_suspend: an optional handler which will be called by the
 *  runtime PM framework following a call to pm_runtime_put().
 *  Note that if pm_runtime_get() is called more than once in
 *  succession this handler will only be called following the
 *  final call to pm_runtime_put() that actually disables the
 *  hardware.
 */
struct arm_pmu_platdata {
    irqreturn_t (*handle_irq)(int irq, void *dev,
                  irq_handler_t pmu_handler);
    int (*runtime_resume)(struct device *dev);
    int (*runtime_suspend)(struct device *dev);
};

#ifdef CONFIG_HW_PERF_EVENTS

/* The events for a given PMU register set. */
struct pmu_hw_events {
    /*
     * The events that are active on the PMU for the given index.
     */
    struct perf_event   **events;

    /*
     * A 1 bit for an index indicates that the counter is being used for
     * an event. A 0 means that the counter can be used.
     */
    unsigned long           *used_mask;

    /*
     * Hardware lock to serialize accesses to PMU registers. Needed for the
     * read/modify/write sequences.
     */
    raw_spinlock_t      pmu_lock;
};

struct arm_pmu {
    struct pmu  pmu;
    cpumask_t   active_irqs;
    char        *name;
    irqreturn_t (*handle_irq)(int irq_num, void *dev);
    void        (*enable)(struct hw_perf_event *evt, int idx);
    void        (*disable)(struct hw_perf_event *evt, int idx);
    int     (*get_event_idx)(struct pmu_hw_events *hw_events,
                     struct hw_perf_event *hwc);
    int     (*set_event_filter)(struct hw_perf_event *evt,
                        struct perf_event_attr *attr);
    u32     (*read_counter)(int idx);
    void        (*write_counter)(int idx, u32 val);
    void        (*start)(void);
    void        (*stop)(void);
    void        (*reset)(void *);
    int     (*request_irq)(irq_handler_t handler);
    void        (*free_irq)(void);
    int     (*map_event)(struct perf_event *event);
    int     num_events;
    atomic_t    active_events;
    struct mutex    reserve_mutex;
    u64     max_period;
    struct platform_device  *plat_device;
    struct pmu_hw_events    *(*get_hw_events)(void);
};

#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))

extern const struct dev_pm_ops armpmu_dev_pm_ops;

int armpmu_register(struct arm_pmu *armpmu, char *name, int type);

u64 armpmu_event_update(struct perf_event *event,
            struct hw_perf_event *hwc,
            int idx);

int armpmu_event_set_period(struct perf_event *event,
                struct hw_perf_event *hwc,
                int idx);

int armpmu_map_event(struct perf_event *event,
             const unsigned (*event_map)[PERF_COUNT_HW_MAX],
             const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
                        [PERF_COUNT_HW_CACHE_OP_MAX]
                        [PERF_COUNT_HW_CACHE_RESULT_MAX],
             u32 raw_event_mask);

#endif /* CONFIG_HW_PERF_EVENTS */

#endif /* __ARM_PMU_H__ */