Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
gpio.c
Go to the documentation of this file.
1 /*
2  * linux/arch/arm/mach-at91/gpio.c
3  *
4  * Copyright (C) 2005 HP Labs
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/kernel.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/io.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_gpio.h>
28 
29 #include <asm/mach/irq.h>
30 
31 #include <mach/hardware.h>
32 #include <mach/at91_pio.h>
33 
34 #include "generic.h"
35 
37  struct gpio_chip chip;
38  struct at91_gpio_chip *next; /* Bank sharing same clock */
39  int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40  int pioc_virq; /* PIO bank Linux virtual interrupt */
41  int pioc_idx; /* PIO bank index */
42  void __iomem *regbase; /* PIO bank virtual address */
43  struct clk *clock; /* associated clock */
44  struct irq_domain *domain; /* associated irq domain */
45 };
46 
47 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
48 
49 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
50 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
51 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
52 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
53  unsigned offset, int val);
54 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
55  unsigned offset);
56 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
57 
58 #define AT91_GPIO_CHIP(name, nr_gpio) \
59  { \
60  .chip = { \
61  .label = name, \
62  .direction_input = at91_gpiolib_direction_input, \
63  .direction_output = at91_gpiolib_direction_output, \
64  .get = at91_gpiolib_get, \
65  .set = at91_gpiolib_set, \
66  .dbg_show = at91_gpiolib_dbg_show, \
67  .to_irq = at91_gpiolib_to_irq, \
68  .ngpio = nr_gpio, \
69  }, \
70  }
71 
72 static struct at91_gpio_chip gpio_chip[] = {
73  AT91_GPIO_CHIP("pioA", 32),
74  AT91_GPIO_CHIP("pioB", 32),
75  AT91_GPIO_CHIP("pioC", 32),
76  AT91_GPIO_CHIP("pioD", 32),
77  AT91_GPIO_CHIP("pioE", 32),
78 };
79 
80 static int gpio_banks;
81 static unsigned long at91_gpio_caps;
82 
83 /* All PIO controllers support PIO3 features */
84 #define AT91_GPIO_CAP_PIO3 (1 << 0)
85 
86 #define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
87 
88 /*--------------------------------------------------------------------------*/
89 
90 static inline void __iomem *pin_to_controller(unsigned pin)
91 {
92  pin /= 32;
93  if (likely(pin < gpio_banks))
94  return gpio_chip[pin].regbase;
95 
96  return NULL;
97 }
98 
99 static inline unsigned pin_to_mask(unsigned pin)
100 {
101  return 1 << (pin % 32);
102 }
103 
104 
105 static char peripheral_function(void __iomem *pio, unsigned mask)
106 {
107  char ret = 'X';
108  u8 select;
109 
110  if (pio) {
111  if (has_pio3()) {
112  select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
113  select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
114  ret = 'A' + select;
115  } else {
116  ret = __raw_readl(pio + PIO_ABSR) & mask ?
117  'B' : 'A';
118  }
119  }
120 
121  return ret;
122 }
123 
124 /*--------------------------------------------------------------------------*/
125 
126 /* Not all hardware capabilities are exposed through these calls; they
127  * only encapsulate the most common features and modes. (So if you
128  * want to change signals in groups, do it directly.)
129  *
130  * Bootloaders will usually handle some of the pin multiplexing setup.
131  * The intent is certainly that by the time Linux is fully booted, all
132  * pins should have been fully initialized. These setup calls should
133  * only be used by board setup routines, or possibly in driver probe().
134  *
135  * For bootloaders doing all that setup, these calls could be inlined
136  * as NOPs so Linux won't duplicate any setup code
137  */
138 
139 
140 /*
141  * mux the pin to the "GPIO" peripheral role.
142  */
143 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
144 {
145  void __iomem *pio = pin_to_controller(pin);
146  unsigned mask = pin_to_mask(pin);
147 
148  if (!pio)
149  return -EINVAL;
150  __raw_writel(mask, pio + PIO_IDR);
151  __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
152  __raw_writel(mask, pio + PIO_PER);
153  return 0;
154 }
156 
157 
158 /*
159  * mux the pin to the "A" internal peripheral role.
160  */
161 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
162 {
163  void __iomem *pio = pin_to_controller(pin);
164  unsigned mask = pin_to_mask(pin);
165 
166  if (!pio)
167  return -EINVAL;
168 
169  __raw_writel(mask, pio + PIO_IDR);
170  __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
171  if (has_pio3()) {
172  __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
173  pio + PIO_ABCDSR1);
174  __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
175  pio + PIO_ABCDSR2);
176  } else {
177  __raw_writel(mask, pio + PIO_ASR);
178  }
179  __raw_writel(mask, pio + PIO_PDR);
180  return 0;
181 }
183 
184 
185 /*
186  * mux the pin to the "B" internal peripheral role.
187  */
188 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
189 {
190  void __iomem *pio = pin_to_controller(pin);
191  unsigned mask = pin_to_mask(pin);
192 
193  if (!pio)
194  return -EINVAL;
195 
196  __raw_writel(mask, pio + PIO_IDR);
197  __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
198  if (has_pio3()) {
199  __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
200  pio + PIO_ABCDSR1);
201  __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
202  pio + PIO_ABCDSR2);
203  } else {
204  __raw_writel(mask, pio + PIO_BSR);
205  }
206  __raw_writel(mask, pio + PIO_PDR);
207  return 0;
208 }
210 
211 
212 /*
213  * mux the pin to the "C" internal peripheral role.
214  */
215 int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
216 {
217  void __iomem *pio = pin_to_controller(pin);
218  unsigned mask = pin_to_mask(pin);
219 
220  if (!pio || !has_pio3())
221  return -EINVAL;
222 
223  __raw_writel(mask, pio + PIO_IDR);
224  __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
225  __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
226  __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
227  __raw_writel(mask, pio + PIO_PDR);
228  return 0;
229 }
231 
232 
233 /*
234  * mux the pin to the "D" internal peripheral role.
235  */
236 int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
237 {
238  void __iomem *pio = pin_to_controller(pin);
239  unsigned mask = pin_to_mask(pin);
240 
241  if (!pio || !has_pio3())
242  return -EINVAL;
243 
244  __raw_writel(mask, pio + PIO_IDR);
245  __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
246  __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
247  __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
248  __raw_writel(mask, pio + PIO_PDR);
249  return 0;
250 }
252 
253 
254 /*
255  * mux the pin to the gpio controller (instead of "A", "B", "C"
256  * or "D" peripheral), and configure it for an input.
257  */
258 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
259 {
260  void __iomem *pio = pin_to_controller(pin);
261  unsigned mask = pin_to_mask(pin);
262 
263  if (!pio)
264  return -EINVAL;
265 
266  __raw_writel(mask, pio + PIO_IDR);
267  __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
268  __raw_writel(mask, pio + PIO_ODR);
269  __raw_writel(mask, pio + PIO_PER);
270  return 0;
271 }
273 
274 
275 /*
276  * mux the pin to the gpio controller (instead of "A", "B", "C"
277  * or "D" peripheral), and configure it for an output.
278  */
280 {
281  void __iomem *pio = pin_to_controller(pin);
282  unsigned mask = pin_to_mask(pin);
283 
284  if (!pio)
285  return -EINVAL;
286 
287  __raw_writel(mask, pio + PIO_IDR);
288  __raw_writel(mask, pio + PIO_PUDR);
289  __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
290  __raw_writel(mask, pio + PIO_OER);
291  __raw_writel(mask, pio + PIO_PER);
292  return 0;
293 }
295 
296 
297 /*
298  * enable/disable the glitch filter; mostly used with IRQ handling.
299  */
300 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
301 {
302  void __iomem *pio = pin_to_controller(pin);
303  unsigned mask = pin_to_mask(pin);
304 
305  if (!pio)
306  return -EINVAL;
307 
308  if (has_pio3() && is_on)
309  __raw_writel(mask, pio + PIO_IFSCDR);
310  __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
311  return 0;
312 }
314 
315 /*
316  * enable/disable the debounce filter;
317  */
318 int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
319 {
320  void __iomem *pio = pin_to_controller(pin);
321  unsigned mask = pin_to_mask(pin);
322 
323  if (!pio || !has_pio3())
324  return -EINVAL;
325 
326  if (is_on) {
327  __raw_writel(mask, pio + PIO_IFSCER);
328  __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
329  __raw_writel(mask, pio + PIO_IFER);
330  } else {
331  __raw_writel(mask, pio + PIO_IFDR);
332  }
333  return 0;
334 }
336 
337 /*
338  * enable/disable the multi-driver; This is only valid for output and
339  * allows the output pin to run as an open collector output.
340  */
341 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
342 {
343  void __iomem *pio = pin_to_controller(pin);
344  unsigned mask = pin_to_mask(pin);
345 
346  if (!pio)
347  return -EINVAL;
348 
349  __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
350  return 0;
351 }
353 
354 /*
355  * enable/disable the pull-down.
356  * If pull-up already enabled while calling the function, we disable it.
357  */
358 int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
359 {
360  void __iomem *pio = pin_to_controller(pin);
361  unsigned mask = pin_to_mask(pin);
362 
363  if (!pio || !has_pio3())
364  return -EINVAL;
365 
366  /* Disable pull-up anyway */
367  __raw_writel(mask, pio + PIO_PUDR);
368  __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
369  return 0;
370 }
372 
373 /*
374  * disable Schmitt trigger
375  */
377 {
378  void __iomem *pio = pin_to_controller(pin);
379  unsigned mask = pin_to_mask(pin);
380 
381  if (!pio || !has_pio3())
382  return -EINVAL;
383 
384  __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
385  return 0;
386 }
388 
389 /*
390  * assuming the pin is muxed as a gpio output, set its value.
391  */
392 int at91_set_gpio_value(unsigned pin, int value)
393 {
394  void __iomem *pio = pin_to_controller(pin);
395  unsigned mask = pin_to_mask(pin);
396 
397  if (!pio)
398  return -EINVAL;
399  __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
400  return 0;
401 }
403 
404 
405 /*
406  * read the pin's value (works even if it's not muxed as a gpio).
407  */
409 {
410  void __iomem *pio = pin_to_controller(pin);
411  unsigned mask = pin_to_mask(pin);
412  u32 pdsr;
413 
414  if (!pio)
415  return -EINVAL;
416  pdsr = __raw_readl(pio + PIO_PDSR);
417  return (pdsr & mask) != 0;
418 }
420 
421 /*--------------------------------------------------------------------------*/
422 
423 #ifdef CONFIG_PM
424 
425 static u32 wakeups[MAX_GPIO_BANKS];
426 static u32 backups[MAX_GPIO_BANKS];
427 
428 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
429 {
430  struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
431  unsigned mask = 1 << d->hwirq;
432  unsigned bank = at91_gpio->pioc_idx;
433 
434  if (unlikely(bank >= MAX_GPIO_BANKS))
435  return -EINVAL;
436 
437  if (state)
438  wakeups[bank] |= mask;
439  else
440  wakeups[bank] &= ~mask;
441 
442  irq_set_irq_wake(at91_gpio->pioc_virq, state);
443 
444  return 0;
445 }
446 
447 void at91_gpio_suspend(void)
448 {
449  int i;
450 
451  for (i = 0; i < gpio_banks; i++) {
452  void __iomem *pio = gpio_chip[i].regbase;
453 
454  backups[i] = __raw_readl(pio + PIO_IMR);
455  __raw_writel(backups[i], pio + PIO_IDR);
456  __raw_writel(wakeups[i], pio + PIO_IER);
457 
458  if (!wakeups[i]) {
459  clk_unprepare(gpio_chip[i].clock);
460  clk_disable(gpio_chip[i].clock);
461  } else {
462 #ifdef CONFIG_PM_DEBUG
463  printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
464 #endif
465  }
466  }
467 }
468 
469 void at91_gpio_resume(void)
470 {
471  int i;
472 
473  for (i = 0; i < gpio_banks; i++) {
474  void __iomem *pio = gpio_chip[i].regbase;
475 
476  if (!wakeups[i]) {
477  if (clk_prepare(gpio_chip[i].clock) == 0)
478  clk_enable(gpio_chip[i].clock);
479  }
480 
481  __raw_writel(wakeups[i], pio + PIO_IDR);
482  __raw_writel(backups[i], pio + PIO_IER);
483  }
484 }
485 
486 #else
487 #define gpio_irq_set_wake NULL
488 #endif
489 
490 
491 /* Several AIC controller irqs are dispatched through this GPIO handler.
492  * To use any AT91_PIN_* as an externally triggered IRQ, first call
493  * at91_set_gpio_input() then maybe enable its glitch filter.
494  * Then just request_irq() with the pin ID; it works like any ARM IRQ
495  * handler.
496  * First implementation always triggers on rising and falling edges
497  * whereas the newer PIO3 can be additionally configured to trigger on
498  * level, edge with any polarity.
499  *
500  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
501  * configuring them with at91_set_a_periph() or at91_set_b_periph().
502  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
503  */
504 
505 static void gpio_irq_mask(struct irq_data *d)
506 {
507  struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
508  void __iomem *pio = at91_gpio->regbase;
509  unsigned mask = 1 << d->hwirq;
510 
511  if (pio)
512  __raw_writel(mask, pio + PIO_IDR);
513 }
514 
515 static void gpio_irq_unmask(struct irq_data *d)
516 {
517  struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
518  void __iomem *pio = at91_gpio->regbase;
519  unsigned mask = 1 << d->hwirq;
520 
521  if (pio)
522  __raw_writel(mask, pio + PIO_IER);
523 }
524 
525 static int gpio_irq_type(struct irq_data *d, unsigned type)
526 {
527  switch (type) {
528  case IRQ_TYPE_NONE:
529  case IRQ_TYPE_EDGE_BOTH:
530  return 0;
531  default:
532  return -EINVAL;
533  }
534 }
535 
536 /* Alternate irq type for PIO3 support */
537 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
538 {
539  struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
540  void __iomem *pio = at91_gpio->regbase;
541  unsigned mask = 1 << d->hwirq;
542 
543  switch (type) {
545  __raw_writel(mask, pio + PIO_ESR);
546  __raw_writel(mask, pio + PIO_REHLSR);
547  break;
549  __raw_writel(mask, pio + PIO_ESR);
550  __raw_writel(mask, pio + PIO_FELLSR);
551  break;
552  case IRQ_TYPE_LEVEL_LOW:
553  __raw_writel(mask, pio + PIO_LSR);
554  __raw_writel(mask, pio + PIO_FELLSR);
555  break;
556  case IRQ_TYPE_LEVEL_HIGH:
557  __raw_writel(mask, pio + PIO_LSR);
558  __raw_writel(mask, pio + PIO_REHLSR);
559  break;
560  case IRQ_TYPE_EDGE_BOTH:
561  /*
562  * disable additional interrupt modes:
563  * fall back to default behavior
564  */
565  __raw_writel(mask, pio + PIO_AIMDR);
566  return 0;
567  case IRQ_TYPE_NONE:
568  default:
569  pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
570  return -EINVAL;
571  }
572 
573  /* enable additional interrupt modes */
574  __raw_writel(mask, pio + PIO_AIMER);
575 
576  return 0;
577 }
578 
579 static struct irq_chip gpio_irqchip = {
580  .name = "GPIO",
581  .irq_disable = gpio_irq_mask,
582  .irq_mask = gpio_irq_mask,
583  .irq_unmask = gpio_irq_unmask,
584  /* .irq_set_type is set dynamically */
585  .irq_set_wake = gpio_irq_set_wake,
586 };
587 
588 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
589 {
590  struct irq_chip *chip = irq_desc_get_chip(desc);
591  struct irq_data *idata = irq_desc_get_irq_data(desc);
592  struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
593  void __iomem *pio = at91_gpio->regbase;
594  unsigned long isr;
595  int n;
596 
597  chained_irq_enter(chip, desc);
598  for (;;) {
599  /* Reading ISR acks pending (edge triggered) GPIO interrupts.
600  * When there none are pending, we're finished unless we need
601  * to process multiple banks (like ID_PIOCDE on sam9263).
602  */
603  isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
604  if (!isr) {
605  if (!at91_gpio->next)
606  break;
607  at91_gpio = at91_gpio->next;
608  pio = at91_gpio->regbase;
609  continue;
610  }
611 
612  n = find_first_bit(&isr, BITS_PER_LONG);
613  while (n < BITS_PER_LONG) {
615  n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
616  }
617  }
618  chained_irq_exit(chip, desc);
619  /* now it may re-trigger */
620 }
621 
622 /*--------------------------------------------------------------------------*/
623 
624 #ifdef CONFIG_DEBUG_FS
625 
626 static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
627 {
628  char *trigger = NULL;
629  char *polarity = NULL;
630 
631  if (__raw_readl(pio + PIO_IMR) & mask) {
632  if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
633  trigger = "edge";
634  polarity = "both";
635  } else {
636  if (__raw_readl(pio + PIO_ELSR) & mask) {
637  trigger = "level";
638  polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
639  "high" : "low";
640  } else {
641  trigger = "edge";
642  polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
643  "rising" : "falling";
644  }
645  }
646  seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
647  } else {
648  seq_printf(s, "GPIO:%s\t\t",
649  __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
650  }
651 }
652 
653 static int at91_gpio_show(struct seq_file *s, void *unused)
654 {
655  int bank, j;
656 
657  /* print heading */
658  seq_printf(s, "Pin\t");
659  for (bank = 0; bank < gpio_banks; bank++) {
660  seq_printf(s, "PIO%c\t\t", 'A' + bank);
661  };
662  seq_printf(s, "\n\n");
663 
664  /* print pin status */
665  for (j = 0; j < 32; j++) {
666  seq_printf(s, "%i:\t", j);
667 
668  for (bank = 0; bank < gpio_banks; bank++) {
669  unsigned pin = (32 * bank) + j;
670  void __iomem *pio = pin_to_controller(pin);
671  unsigned mask = pin_to_mask(pin);
672 
673  if (__raw_readl(pio + PIO_PSR) & mask)
674  gpio_printf(s, pio, mask);
675  else
676  seq_printf(s, "%c\t\t",
677  peripheral_function(pio, mask));
678  }
679 
680  seq_printf(s, "\n");
681  }
682 
683  return 0;
684 }
685 
686 static int at91_gpio_open(struct inode *inode, struct file *file)
687 {
688  return single_open(file, at91_gpio_show, NULL);
689 }
690 
691 static const struct file_operations at91_gpio_operations = {
692  .open = at91_gpio_open,
693  .read = seq_read,
694  .llseek = seq_lseek,
695  .release = single_release,
696 };
697 
698 static int __init at91_gpio_debugfs_init(void)
699 {
700  /* /sys/kernel/debug/at91_gpio */
701  (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
702  return 0;
703 }
704 postcore_initcall(at91_gpio_debugfs_init);
705 
706 #endif
707 
708 /*--------------------------------------------------------------------------*/
709 
710 /*
711  * This lock class tells lockdep that GPIO irqs are in a different
712  * category than their parents, so it won't report false recursion.
713  */
714 static struct lock_class_key gpio_lock_class;
715 
716 #if defined(CONFIG_OF)
717 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
719 {
720  struct at91_gpio_chip *at91_gpio = h->host_data;
721 
722  irq_set_lockdep_class(virq, &gpio_lock_class);
723 
724  /*
725  * Can use the "simple" and not "edge" handler since it's
726  * shorter, and the AIC handles interrupts sanely.
727  */
728  irq_set_chip_and_handler(virq, &gpio_irqchip,
730  set_irq_flags(virq, IRQF_VALID);
731  irq_set_chip_data(virq, at91_gpio);
732 
733  return 0;
734 }
735 
736 static struct irq_domain_ops at91_gpio_ops = {
737  .map = at91_gpio_irq_map,
738  .xlate = irq_domain_xlate_twocell,
739 };
740 
742  struct device_node *parent)
743 {
744  struct at91_gpio_chip *prev = NULL;
745  int alias_idx = of_alias_get_id(node, "gpio");
746  struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx];
747 
748  /* Setup proper .irq_set_type function */
749  if (has_pio3())
750  gpio_irqchip.irq_set_type = alt_gpio_irq_type;
751  else
752  gpio_irqchip.irq_set_type = gpio_irq_type;
753 
754  /* Disable irqs of this PIO controller */
755  __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
756 
757  /* Setup irq domain */
758  at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
759  &at91_gpio_ops, at91_gpio);
760  if (!at91_gpio->domain)
761  panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
762  at91_gpio->pioc_idx);
763 
764  /* Setup chained handler */
765  if (at91_gpio->pioc_idx)
766  prev = &gpio_chip[at91_gpio->pioc_idx - 1];
767 
768  /* The toplevel handler handles one bank of GPIOs, except
769  * on some SoC it can handles up to three...
770  * We only set up the handler for the first of the list.
771  */
772  if (prev && prev->next == at91_gpio)
773  return 0;
774 
775  at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
776  at91_gpio->pioc_hwirq);
777  irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
778  irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
779 
780  return 0;
781 }
782 #else
784  struct device_node *parent)
785 {
786  return -EINVAL;
787 }
788 #endif
789 
790 /*
791  * irqdomain initialization: pile up irqdomains on top of AIC range
792  */
793 static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
794 {
795  int irq_base;
796 
797  irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
798  if (irq_base < 0)
799  panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
800  at91_gpio->pioc_idx, irq_base);
801  at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
802  irq_base, 0,
804  if (!at91_gpio->domain)
805  panic("at91_gpio.%d: couldn't allocate irq domain.\n",
806  at91_gpio->pioc_idx);
807 }
808 
809 /*
810  * Called from the processor-specific init to enable GPIO interrupt support.
811  */
813 {
814  unsigned pioc;
815  int gpio_irqnbr = 0;
816  struct at91_gpio_chip *this, *prev;
817 
818  /* Setup proper .irq_set_type function */
819  if (has_pio3())
820  gpio_irqchip.irq_set_type = alt_gpio_irq_type;
821  else
822  gpio_irqchip.irq_set_type = gpio_irq_type;
823 
824  for (pioc = 0, this = gpio_chip, prev = NULL;
825  pioc++ < gpio_banks;
826  prev = this, this++) {
827  int offset;
828 
829  __raw_writel(~0, this->regbase + PIO_IDR);
830 
831  /* setup irq domain for this GPIO controller */
832  at91_gpio_irqdomain(this);
833 
834  for (offset = 0; offset < this->chip.ngpio; offset++) {
835  unsigned int virq = irq_find_mapping(this->domain, offset);
836  irq_set_lockdep_class(virq, &gpio_lock_class);
837 
838  /*
839  * Can use the "simple" and not "edge" handler since it's
840  * shorter, and the AIC handles interrupts sanely.
841  */
842  irq_set_chip_and_handler(virq, &gpio_irqchip,
844  set_irq_flags(virq, IRQF_VALID);
845  irq_set_chip_data(virq, this);
846 
847  gpio_irqnbr++;
848  }
849 
850  /* The toplevel handler handles one bank of GPIOs, except
851  * on some SoC it can handles up to three...
852  * We only set up the handler for the first of the list.
853  */
854  if (prev && prev->next == this)
855  continue;
856 
858  irq_set_chip_data(this->pioc_virq, this);
859  irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
860  }
861  pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
862 }
863 
864 /* gpiolib support */
865 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
866  unsigned offset)
867 {
868  struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
869  void __iomem *pio = at91_gpio->regbase;
870  unsigned mask = 1 << offset;
871 
872  __raw_writel(mask, pio + PIO_ODR);
873  return 0;
874 }
875 
876 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
877  unsigned offset, int val)
878 {
879  struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
880  void __iomem *pio = at91_gpio->regbase;
881  unsigned mask = 1 << offset;
882 
883  __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
884  __raw_writel(mask, pio + PIO_OER);
885  return 0;
886 }
887 
888 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
889 {
890  struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
891  void __iomem *pio = at91_gpio->regbase;
892  unsigned mask = 1 << offset;
893  u32 pdsr;
894 
895  pdsr = __raw_readl(pio + PIO_PDSR);
896  return (pdsr & mask) != 0;
897 }
898 
899 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
900 {
901  struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
902  void __iomem *pio = at91_gpio->regbase;
903  unsigned mask = 1 << offset;
904 
905  __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
906 }
907 
908 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
909 {
910  int i;
911 
912  for (i = 0; i < chip->ngpio; i++) {
913  unsigned pin = chip->base + i;
914  void __iomem *pio = pin_to_controller(pin);
915  unsigned mask = pin_to_mask(pin);
916  const char *gpio_label;
917 
918  gpio_label = gpiochip_is_requested(chip, i);
919  if (gpio_label) {
920  seq_printf(s, "[%s] GPIO%s%d: ",
921  gpio_label, chip->label, i);
922  if (__raw_readl(pio + PIO_PSR) & mask)
923  seq_printf(s, "[gpio] %s\n",
924  at91_get_gpio_value(pin) ?
925  "set" : "clear");
926  else
927  seq_printf(s, "[periph %c]\n",
928  peripheral_function(pio, mask));
929  }
930  }
931 }
932 
933 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
934 {
935  struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
936  int virq;
937 
938  if (offset < chip->ngpio)
939  virq = irq_create_mapping(at91_gpio->domain, offset);
940  else
941  virq = -ENXIO;
942 
943  dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
944  chip->label, offset + chip->base, virq);
945  return virq;
946 }
947 
948 static int __init at91_gpio_setup_clk(int idx)
949 {
950  struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
951 
952  /* retreive PIO controller's clock */
953  at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
954  if (IS_ERR(at91_gpio->clock)) {
955  pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
956  goto err;
957  }
958 
959  if (clk_prepare(at91_gpio->clock))
960  goto clk_prep_err;
961 
962  /* enable PIO controller's clock */
963  if (clk_enable(at91_gpio->clock)) {
964  pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
965  goto clk_err;
966  }
967 
968  return 0;
969 
970 clk_err:
971  clk_unprepare(at91_gpio->clock);
972 clk_prep_err:
973  clk_put(at91_gpio->clock);
974 err:
975  return -EINVAL;
976 }
977 
978 #ifdef CONFIG_OF_GPIO
979 static void __init of_at91_gpio_init_one(struct device_node *np)
980 {
981  int alias_idx;
982  struct at91_gpio_chip *at91_gpio;
983 
984  if (!np)
985  return;
986 
987  alias_idx = of_alias_get_id(np, "gpio");
988  if (alias_idx >= MAX_GPIO_BANKS) {
989  pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
990  alias_idx, MAX_GPIO_BANKS);
991  return;
992  }
993 
994  at91_gpio = &gpio_chip[alias_idx];
995  at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
996 
997  at91_gpio->regbase = of_iomap(np, 0);
998  if (!at91_gpio->regbase) {
999  pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
1000  alias_idx);
1001  return;
1002  }
1003 
1004  /* Get the interrupts property */
1005  if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
1006  pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
1007  alias_idx);
1008  goto ioremap_err;
1009  }
1010 
1011  /* Get capabilities from compatibility property */
1012  if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
1013  at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
1014 
1015  /* Setup clock */
1016  if (at91_gpio_setup_clk(alias_idx))
1017  goto ioremap_err;
1018 
1019  at91_gpio->chip.of_node = np;
1020  gpio_banks = max(gpio_banks, alias_idx + 1);
1021  at91_gpio->pioc_idx = alias_idx;
1022  return;
1023 
1024 ioremap_err:
1025  iounmap(at91_gpio->regbase);
1026 }
1027 
1028 static int __init of_at91_gpio_init(void)
1029 {
1030  struct device_node *np = NULL;
1031 
1032  /*
1033  * This isn't ideal, but it gets things hooked up until this
1034  * driver is converted into a platform_device
1035  */
1036  for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
1037  of_at91_gpio_init_one(np);
1038 
1039  return gpio_banks > 0 ? 0 : -EINVAL;
1040 }
1041 #else
1042 static int __init of_at91_gpio_init(void)
1043 {
1044  return -EINVAL;
1045 }
1046 #endif
1047 
1048 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
1049 {
1050  struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
1051 
1052  at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
1053  at91_gpio->pioc_hwirq = pioc_hwirq;
1054  at91_gpio->pioc_idx = idx;
1055 
1056  at91_gpio->regbase = ioremap(regbase, 512);
1057  if (!at91_gpio->regbase) {
1058  pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
1059  return;
1060  }
1061 
1062  if (at91_gpio_setup_clk(idx))
1063  goto ioremap_err;
1064 
1065  gpio_banks = max(gpio_banks, idx + 1);
1066  return;
1067 
1068 ioremap_err:
1069  iounmap(at91_gpio->regbase);
1070 }
1071 
1072 /*
1073  * Called from the processor-specific init to enable GPIO pin support.
1074  */
1075 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
1076 {
1077  unsigned i;
1078  struct at91_gpio_chip *at91_gpio, *last = NULL;
1079 
1080  BUG_ON(nr_banks > MAX_GPIO_BANKS);
1081 
1082  if (of_at91_gpio_init() < 0) {
1083  /* No GPIO controller found in device tree */
1084  for (i = 0; i < nr_banks; i++)
1085  at91_gpio_init_one(i, data[i].regbase, data[i].id);
1086  }
1087 
1088  for (i = 0; i < gpio_banks; i++) {
1089  at91_gpio = &gpio_chip[i];
1090 
1091  /*
1092  * GPIO controller are grouped on some SoC:
1093  * PIOC, PIOD and PIOE can share the same IRQ line
1094  */
1095  if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
1096  last->next = at91_gpio;
1097  last = at91_gpio;
1098 
1099  gpiochip_add(&at91_gpio->chip);
1100  }
1101 }