|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
#include <linux/kernel.h>#include <linux/init.h>#include <linux/module.h>#include <linux/interrupt.h>#include <linux/platform_device.h>#include <linux/io.h>#include <linux/slab.h>#include <mach/edma.h>Go to the source code of this file.
Data Structures | |
| struct | edma |
| struct | edma::dma_interrupt_data |
Macros | |
| #define | PARM_OPT 0x00 |
| #define | PARM_SRC 0x04 |
| #define | PARM_A_B_CNT 0x08 |
| #define | PARM_DST 0x0c |
| #define | PARM_SRC_DST_BIDX 0x10 |
| #define | PARM_LINK_BCNTRLD 0x14 |
| #define | PARM_SRC_DST_CIDX 0x18 |
| #define | PARM_CCNT 0x1c |
| #define | PARM_SIZE 0x20 |
| #define | SH_ER 0x00 /* 64 bits */ |
| #define | SH_ECR 0x08 /* 64 bits */ |
| #define | SH_ESR 0x10 /* 64 bits */ |
| #define | SH_CER 0x18 /* 64 bits */ |
| #define | SH_EER 0x20 /* 64 bits */ |
| #define | SH_EECR 0x28 /* 64 bits */ |
| #define | SH_EESR 0x30 /* 64 bits */ |
| #define | SH_SER 0x38 /* 64 bits */ |
| #define | SH_SECR 0x40 /* 64 bits */ |
| #define | SH_IER 0x50 /* 64 bits */ |
| #define | SH_IECR 0x58 /* 64 bits */ |
| #define | SH_IESR 0x60 /* 64 bits */ |
| #define | SH_IPR 0x68 /* 64 bits */ |
| #define | SH_ICR 0x70 /* 64 bits */ |
| #define | SH_IEVAL 0x78 |
| #define | SH_QER 0x80 |
| #define | SH_QEER 0x84 |
| #define | SH_QEECR 0x88 |
| #define | SH_QEESR 0x8c |
| #define | SH_QSER 0x90 |
| #define | SH_QSECR 0x94 |
| #define | SH_SIZE 0x200 |
| #define | EDMA_REV 0x0000 |
| #define | EDMA_CCCFG 0x0004 |
| #define | EDMA_QCHMAP 0x0200 /* 8 registers */ |
| #define | EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ |
| #define | EDMA_QDMAQNUM 0x0260 |
| #define | EDMA_QUETCMAP 0x0280 |
| #define | EDMA_QUEPRI 0x0284 |
| #define | EDMA_EMR 0x0300 /* 64 bits */ |
| #define | EDMA_EMCR 0x0308 /* 64 bits */ |
| #define | EDMA_QEMR 0x0310 |
| #define | EDMA_QEMCR 0x0314 |
| #define | EDMA_CCERR 0x0318 |
| #define | EDMA_CCERRCLR 0x031c |
| #define | EDMA_EEVAL 0x0320 |
| #define | EDMA_DRAE 0x0340 /* 4 x 64 bits*/ |
| #define | EDMA_QRAE 0x0380 /* 4 registers */ |
| #define | EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ |
| #define | EDMA_QSTAT 0x0600 /* 2 registers */ |
| #define | EDMA_QWMTHRA 0x0620 |
| #define | EDMA_QWMTHRB 0x0624 |
| #define | EDMA_CCSTAT 0x0640 |
| #define | EDMA_M 0x1000 /* global channel registers */ |
| #define | EDMA_ECR 0x1008 |
| #define | EDMA_ECRH 0x100C |
| #define | EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ |
| #define | EDMA_PARM 0x4000 /* 128 param entries */ |
| #define | PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
| #define | EDMA_DCHMAP 0x0100 /* 64 registers */ |
| #define | CHMAP_EXIST BIT(24) |
| #define | EDMA_MAX_DMACH 64 |
| #define | EDMA_MAX_PARAMENTRY 512 |
| #define | tc_errs_handled false /* disabled as long as they're NOPs */ |
| #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ |
| #define PARM_OFFSET | ( | param_no | ) | (EDMA_PARM + ((param_no) << 5)) |
| arch_initcall | ( | edma_init | ) |
| int edma_alloc_channel | ( | int | channel, |
| void(*)(unsigned channel, u16 ch_status, void *data) | callback, | ||
| void * | data, | ||
| enum dma_event_q | eventq_no | ||
| ) |
edma_alloc_channel - allocate DMA channel and paired parameter RAM : specific channel to allocate; negative for "any unmapped channel" : optional; to be issued on DMA completion or errors : passed to callback : an EVENTQ_* constant, used to choose which Transfer Controller (TC) executes requests using this channel. Use EVENTQ_DEFAULT unless you really need a high priority queue.
This allocates a DMA channel and its associated parameter RAM slot. The parameter RAM is initialized to hold a dummy transfer.
Normal use is to pass a specific channel number as , to make use of hardware events mapped to that channel. When the channel will be used only for software triggering or event chaining, channels not mapped to hardware events (or mapped to unused events) are preferable.
DMA transfers start from a channel using edma_start(), or by chaining. When the transfer described in that channel's parameter RAM slot completes, that slot's data may be reloaded through a link.
DMA errors are only reported to the associated with the channel driving that transfer, but transfer completion callbacks can be sent to another channel under control of the TCC field in the option word of the transfer's parameter RAM set. Drivers must not use DMA transfer completion callbacks for channels they did not allocate. (The same applies to TCC codes used in transfer chaining.)
edma_alloc_cont_slots- alloc contiguous parameter RAM slots The API will return the starting point of a set of contiguous parameter RAM slots that have been requested
: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT : number of contiguous Paramter RAM slots - the start value of Parameter RAM slot that should be passed if id is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of contiguous Parameter RAM slots from parameter RAM 64 in the case of DaVinci SOCs and 32 in the case of DA8xx SOCs.
If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a set of contiguous parameter RAM slots from the "slot" that is passed as an argument to the API.
If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries starts looking for a set of contiguous parameter RAMs from the "slot" that is passed as an argument to the API. On failure the API will try to find a set of contiguous Parameter RAM slots from the remaining Parameter RAM slots
edma_alloc_slot - allocate DMA parameter RAM : specific slot to allocate; negative for "any unused slot"
This allocates a parameter RAM slot, initializing it to hold a dummy transfer. Slots allocated using this routine have not been mapped to a hardware DMA channel, and will normally be used by linking to them from a slot associated with a DMA channel.
Normal use is to pass EDMA_SLOT_ANY as the , but specific slots may be allocated on behalf of DSP firmware.
| void edma_free_channel | ( | unsigned | channel | ) |
edma_free_channel - deallocate DMA channel : dma channel returned from edma_alloc_channel()
This deallocates the DMA channel and associated parameter RAM slot allocated by edma_alloc_channel().
Callers are responsible for ensuring the channel is inactive, and will not be reactivated by linking, chaining, or software calls to edma_start().
edma_free_cont_slots - deallocate DMA parameter RAM slots : first parameter RAM of a set of parameter RAM slots to be freed : the number of contiguous parameter RAM slots to be freed
This deallocates the parameter RAM slots allocated by edma_alloc_cont_slots. Callers/applications need to keep track of sets of contiguous parameter RAM slots that have been allocated using the edma_alloc_cont_slots API. Callers are responsible for ensuring the slots are inactive, and will not be activated.
| void edma_free_slot | ( | unsigned | slot | ) |
edma_free_slot - deallocate DMA parameter RAM : parameter RAM slot returned from edma_alloc_slot()
This deallocates the parameter RAM slot allocated by edma_alloc_slot(). Callers are responsible for ensuring the slot is inactive, and will not be activated.
| void edma_get_position | ( | unsigned | slot, |
| dma_addr_t * | src, | ||
| dma_addr_t * | dst | ||
| ) |
edma_get_position - returns the current transfer points : parameter RAM slot being examined : pointer to source port position : pointer to destination port position
Returns current source and destination addresses for a particular parameter RAM slot. Its channel should not be active when this is called.
| void edma_link | ( | unsigned | from, |
| unsigned | to | ||
| ) |
| void edma_pause | ( | unsigned | channel | ) |
edma_pause - pause dma on a channel : on which edma_start() has been called
This temporarily disables EDMA hardware events on the specified channel, preventing them from triggering new transfers on its behalf
| void edma_read_slot | ( | unsigned | slot, |
| struct edmacc_param * | param | ||
| ) |
| void edma_resume | ( | unsigned | channel | ) |
edma_resume - resumes dma on a paused channel : on which edma_pause() has been called
This re-enables EDMA hardware events on the specified channel.
| void edma_set_dest | ( | unsigned | slot, |
| dma_addr_t | dest_port, | ||
| enum address_mode | mode, | ||
| enum fifo_width | width | ||
| ) |
edma_set_dest - set initial DMA destination address in parameter RAM slot : parameter RAM slot being configured : physical address of destination (memory, controller FIFO, etc) : INCR, except in very rare cases : ignored unless is FIFO, else specifies the width to use when addressing the fifo (e.g. W8BIT, W32BIT)
Note that the destination address is modified during the DMA transfer according to edma_set_dest_index().
edma_set_dest_index - configure DMA destination address indexing : parameter RAM slot being configured : byte offset between destination arrays in a frame : byte offset between destination frames in a block
Offsets are specified to support either contiguous or discontiguous memory transfers, or repeated access to a hardware register, as needed. When accessing hardware registers, both offsets are normally zero.
| void edma_set_src | ( | unsigned | slot, |
| dma_addr_t | src_port, | ||
| enum address_mode | mode, | ||
| enum fifo_width | width | ||
| ) |
edma_set_src - set initial DMA source address in parameter RAM slot : parameter RAM slot being configured : physical address of source (memory, controller FIFO, etc) : INCR, except in very rare cases : ignored unless is FIFO, else specifies the width to use when addressing the fifo (e.g. W8BIT, W32BIT)
Note that the source address is modified during the DMA transfer according to edma_set_src_index().
edma_set_src_index - configure DMA source address indexing : parameter RAM slot being configured : byte offset between source arrays in a frame : byte offset between source frames in a block
Offsets are specified to support either contiguous or discontiguous memory transfers, or repeated access to a hardware register, as needed. When accessing hardware registers, both offsets are normally zero.
| void edma_set_transfer_params | ( | unsigned | slot, |
| u16 | acnt, | ||
| u16 | bcnt, | ||
| u16 | ccnt, | ||
| u16 | bcnt_rld, | ||
| enum sync_dimension | sync_mode | ||
| ) |
edma_set_transfer_params - configure DMA transfer parameters : parameter RAM slot being configured : how many bytes per array (at least one) : how many arrays per frame (at least one) : how many frames per block (at least one) : used only for A-Synchronized transfers; this specifies the value to reload into bcnt when it decrements to zero : ASYNC or ABSYNC
See the EDMA3 documentation to understand how to configure and link transfers using the fields in PaRAM slots. If you are not doing it all at once with edma_write_slot(), you will use this routine plus two calls each for source and destination, setting the initial address and saying how to index that address.
An example of an A-Synchronized transfer is a serial link using a single word shift register. In that case, would be equal to that word size; the serial controller issues a DMA synchronization event to transfer each word, and memory access by the DMA transfer controller will be word-at-a-time.
An example of an AB-Synchronized transfer is a device using a FIFO. In that case, equals the FIFO width and equals its depth. The controller with the FIFO issues DMA synchronization events when the FIFO threshold is reached, and the DMA transfer controller will transfer one frame to (or from) the FIFO. It will probably use efficient burst modes to access memory.
| int edma_start | ( | unsigned | channel | ) |
edma_start - start dma on a channel : channel being activated
Channels with event associations will be triggered by their hardware events, and channels without such associations will be triggered by software. (At this writing there is no interface for using software triggers except with channels that don't support hardware triggers.)
Returns zero on success, else negative errno.
| void edma_stop | ( | unsigned | channel | ) |
| void edma_unlink | ( | unsigned | from | ) |
| void edma_write_slot | ( | unsigned | slot, |
| const struct edmacc_param * | param | ||
| ) |
edma_write_slot - write parameter RAM data for slot : number of parameter RAM slot being modified
| data to be written into parameter RAM slot |
Use this to assign all parameters of a transfer at once. This allows more efficient setup of transfers than issuing multiple calls to set up those parameters in small pieces, and provides complete control over all transfer options.
| EXPORT_SYMBOL | ( | edma_alloc_channel | ) |
| EXPORT_SYMBOL | ( | edma_free_channel | ) |
| EXPORT_SYMBOL | ( | edma_alloc_slot | ) |
| EXPORT_SYMBOL | ( | edma_free_slot | ) |
| EXPORT_SYMBOL | ( | edma_alloc_cont_slots | ) |
| EXPORT_SYMBOL | ( | edma_free_cont_slots | ) |
| EXPORT_SYMBOL | ( | edma_set_src | ) |
| EXPORT_SYMBOL | ( | edma_set_dest | ) |
| EXPORT_SYMBOL | ( | edma_get_position | ) |
| EXPORT_SYMBOL | ( | edma_set_src_index | ) |
| EXPORT_SYMBOL | ( | edma_set_dest_index | ) |
| EXPORT_SYMBOL | ( | edma_set_transfer_params | ) |
| EXPORT_SYMBOL | ( | edma_link | ) |
| EXPORT_SYMBOL | ( | edma_unlink | ) |
| EXPORT_SYMBOL | ( | edma_write_slot | ) |
| EXPORT_SYMBOL | ( | edma_read_slot | ) |
| EXPORT_SYMBOL | ( | edma_pause | ) |
| EXPORT_SYMBOL | ( | edma_resume | ) |
| EXPORT_SYMBOL | ( | edma_start | ) |
| EXPORT_SYMBOL | ( | edma_stop | ) |
| EXPORT_SYMBOL | ( | edma_clean_channel | ) |
| EXPORT_SYMBOL | ( | edma_clear_event | ) |
1.8.2