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dma.c
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1 /*
2  * EDMA3 support for DaVinci
3  *
4  * Copyright (C) 2006-2009 Texas Instruments.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27 
28 #include <mach/edma.h>
29 
30 /* Offsets matching "struct edmacc_param" */
31 #define PARM_OPT 0x00
32 #define PARM_SRC 0x04
33 #define PARM_A_B_CNT 0x08
34 #define PARM_DST 0x0c
35 #define PARM_SRC_DST_BIDX 0x10
36 #define PARM_LINK_BCNTRLD 0x14
37 #define PARM_SRC_DST_CIDX 0x18
38 #define PARM_CCNT 0x1c
39 
40 #define PARM_SIZE 0x20
41 
42 /* Offsets for EDMA CC global channel registers and their shadows */
43 #define SH_ER 0x00 /* 64 bits */
44 #define SH_ECR 0x08 /* 64 bits */
45 #define SH_ESR 0x10 /* 64 bits */
46 #define SH_CER 0x18 /* 64 bits */
47 #define SH_EER 0x20 /* 64 bits */
48 #define SH_EECR 0x28 /* 64 bits */
49 #define SH_EESR 0x30 /* 64 bits */
50 #define SH_SER 0x38 /* 64 bits */
51 #define SH_SECR 0x40 /* 64 bits */
52 #define SH_IER 0x50 /* 64 bits */
53 #define SH_IECR 0x58 /* 64 bits */
54 #define SH_IESR 0x60 /* 64 bits */
55 #define SH_IPR 0x68 /* 64 bits */
56 #define SH_ICR 0x70 /* 64 bits */
57 #define SH_IEVAL 0x78
58 #define SH_QER 0x80
59 #define SH_QEER 0x84
60 #define SH_QEECR 0x88
61 #define SH_QEESR 0x8c
62 #define SH_QSER 0x90
63 #define SH_QSECR 0x94
64 #define SH_SIZE 0x200
65 
66 /* Offsets for EDMA CC global registers */
67 #define EDMA_REV 0x0000
68 #define EDMA_CCCFG 0x0004
69 #define EDMA_QCHMAP 0x0200 /* 8 registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
71 #define EDMA_QDMAQNUM 0x0260
72 #define EDMA_QUETCMAP 0x0280
73 #define EDMA_QUEPRI 0x0284
74 #define EDMA_EMR 0x0300 /* 64 bits */
75 #define EDMA_EMCR 0x0308 /* 64 bits */
76 #define EDMA_QEMR 0x0310
77 #define EDMA_QEMCR 0x0314
78 #define EDMA_CCERR 0x0318
79 #define EDMA_CCERRCLR 0x031c
80 #define EDMA_EEVAL 0x0320
81 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
82 #define EDMA_QRAE 0x0380 /* 4 registers */
83 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
84 #define EDMA_QSTAT 0x0600 /* 2 registers */
85 #define EDMA_QWMTHRA 0x0620
86 #define EDMA_QWMTHRB 0x0624
87 #define EDMA_CCSTAT 0x0640
88 
89 #define EDMA_M 0x1000 /* global channel registers */
90 #define EDMA_ECR 0x1008
91 #define EDMA_ECRH 0x100C
92 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
93 #define EDMA_PARM 0x4000 /* 128 param entries */
94 
95 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
96 
97 #define EDMA_DCHMAP 0x0100 /* 64 registers */
98 #define CHMAP_EXIST BIT(24)
99 
100 #define EDMA_MAX_DMACH 64
101 #define EDMA_MAX_PARAMENTRY 512
102 
103 /*****************************************************************************/
104 
105 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
106 
107 static inline unsigned int edma_read(unsigned ctlr, int offset)
108 {
109  return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
110 }
111 
112 static inline void edma_write(unsigned ctlr, int offset, int val)
113 {
114  __raw_writel(val, edmacc_regs_base[ctlr] + offset);
115 }
116 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
117  unsigned or)
118 {
119  unsigned val = edma_read(ctlr, offset);
120  val &= and;
121  val |= or;
122  edma_write(ctlr, offset, val);
123 }
124 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
125 {
126  unsigned val = edma_read(ctlr, offset);
127  val &= and;
128  edma_write(ctlr, offset, val);
129 }
130 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
131 {
132  unsigned val = edma_read(ctlr, offset);
133  val |= or;
134  edma_write(ctlr, offset, val);
135 }
136 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
137 {
138  return edma_read(ctlr, offset + (i << 2));
139 }
140 static inline void edma_write_array(unsigned ctlr, int offset, int i,
141  unsigned val)
142 {
143  edma_write(ctlr, offset + (i << 2), val);
144 }
145 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
146  unsigned and, unsigned or)
147 {
148  edma_modify(ctlr, offset + (i << 2), and, or);
149 }
150 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
151 {
152  edma_or(ctlr, offset + (i << 2), or);
153 }
154 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
155  unsigned or)
156 {
157  edma_or(ctlr, offset + ((i*2 + j) << 2), or);
158 }
159 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
160  unsigned val)
161 {
162  edma_write(ctlr, offset + ((i*2 + j) << 2), val);
163 }
164 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
165 {
166  return edma_read(ctlr, EDMA_SHADOW0 + offset);
167 }
168 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
169  int i)
170 {
171  return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
172 }
173 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
174 {
175  edma_write(ctlr, EDMA_SHADOW0 + offset, val);
176 }
177 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
178  unsigned val)
179 {
180  edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
181 }
182 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
183  int param_no)
184 {
185  return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
186 }
187 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
188  unsigned val)
189 {
190  edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
191 }
192 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
193  unsigned and, unsigned or)
194 {
195  edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
196 }
197 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
198  unsigned and)
199 {
200  edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
201 }
202 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
203  unsigned or)
204 {
205  edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
206 }
207 
208 static inline void set_bits(int offset, int len, unsigned long *p)
209 {
210  for (; len > 0; len--)
211  set_bit(offset + (len - 1), p);
212 }
213 
214 static inline void clear_bits(int offset, int len, unsigned long *p)
215 {
216  for (; len > 0; len--)
217  clear_bit(offset + (len - 1), p);
218 }
219 
220 /*****************************************************************************/
221 
222 /* actual number of DMA channels and slots on this silicon */
223 struct edma {
224  /* how many dma resources of each type */
225  unsigned num_channels;
226  unsigned num_region;
227  unsigned num_slots;
228  unsigned num_tc;
229  unsigned num_cc;
230  enum dma_event_q default_queue;
231 
232  /* list of channels with no even trigger; terminated by "-1" */
233  const s8 *noevent;
234 
235  /* The edma_inuse bit for each PaRAM slot is clear unless the
236  * channel is in use ... by ARM or DSP, for QDMA, or whatever.
237  */
238  DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
239 
240  /* The edma_unused bit for each channel is clear unless
241  * it is not being used on this platform. It uses a bit
242  * of SOC-specific initialization code.
243  */
244  DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
245 
246  unsigned irq_res_start;
247  unsigned irq_res_end;
248 
249  struct dma_interrupt_data {
250  void (*callback)(unsigned channel, unsigned short ch_status,
251  void *data);
252  void *data;
253  } intr_data[EDMA_MAX_DMACH];
254 };
255 
256 static struct edma *edma_cc[EDMA_MAX_CC];
257 static int arch_num_cc;
258 
259 /* dummy param set used to (re)initialize parameter RAM slots */
260 static const struct edmacc_param dummy_paramset = {
261  .link_bcntrld = 0xffff,
262  .ccnt = 1,
263 };
264 
265 /*****************************************************************************/
266 
267 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
268  enum dma_event_q queue_no)
269 {
270  int bit = (ch_no & 0x7) * 4;
271 
272  /* default to low priority queue */
273  if (queue_no == EVENTQ_DEFAULT)
274  queue_no = edma_cc[ctlr]->default_queue;
275 
276  queue_no &= 7;
277  edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
278  ~(0x7 << bit), queue_no << bit);
279 }
280 
281 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
282 {
283  int bit = queue_no * 4;
284  edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
285 }
286 
287 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
288  int priority)
289 {
290  int bit = queue_no * 4;
291  edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
292  ((priority & 0x7) << bit));
293 }
294 
306 static void __init map_dmach_param(unsigned ctlr)
307 {
308  int i;
309  for (i = 0; i < EDMA_MAX_DMACH; i++)
310  edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
311 }
312 
313 static inline void
314 setup_dma_interrupt(unsigned lch,
315  void (*callback)(unsigned channel, u16 ch_status, void *data),
316  void *data)
317 {
318  unsigned ctlr;
319 
320  ctlr = EDMA_CTLR(lch);
321  lch = EDMA_CHAN_SLOT(lch);
322 
323  if (!callback)
324  edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
325  BIT(lch & 0x1f));
326 
327  edma_cc[ctlr]->intr_data[lch].callback = callback;
328  edma_cc[ctlr]->intr_data[lch].data = data;
329 
330  if (callback) {
331  edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
332  BIT(lch & 0x1f));
333  edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
334  BIT(lch & 0x1f));
335  }
336 }
337 
338 static int irq2ctlr(int irq)
339 {
340  if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
341  return 0;
342  else if (irq >= edma_cc[1]->irq_res_start &&
343  irq <= edma_cc[1]->irq_res_end)
344  return 1;
345 
346  return -1;
347 }
348 
349 /******************************************************************************
350  *
351  * DMA interrupt handler
352  *
353  *****************************************************************************/
354 static irqreturn_t dma_irq_handler(int irq, void *data)
355 {
356  int ctlr;
357  u32 sh_ier;
358  u32 sh_ipr;
359  u32 bank;
360 
361  ctlr = irq2ctlr(irq);
362  if (ctlr < 0)
363  return IRQ_NONE;
364 
365  dev_dbg(data, "dma_irq_handler\n");
366 
367  sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
368  if (!sh_ipr) {
369  sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
370  if (!sh_ipr)
371  return IRQ_NONE;
372  sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
373  bank = 1;
374  } else {
375  sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
376  bank = 0;
377  }
378 
379  do {
380  u32 slot;
381  u32 channel;
382 
383  dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
384 
385  slot = __ffs(sh_ipr);
386  sh_ipr &= ~(BIT(slot));
387 
388  if (sh_ier & BIT(slot)) {
389  channel = (bank << 5) | slot;
390  /* Clear the corresponding IPR bits */
391  edma_shadow0_write_array(ctlr, SH_ICR, bank,
392  BIT(slot));
393  if (edma_cc[ctlr]->intr_data[channel].callback)
394  edma_cc[ctlr]->intr_data[channel].callback(
395  channel, DMA_COMPLETE,
396  edma_cc[ctlr]->intr_data[channel].data);
397  }
398  } while (sh_ipr);
399 
400  edma_shadow0_write(ctlr, SH_IEVAL, 1);
401  return IRQ_HANDLED;
402 }
403 
404 /******************************************************************************
405  *
406  * DMA error interrupt handler
407  *
408  *****************************************************************************/
409 static irqreturn_t dma_ccerr_handler(int irq, void *data)
410 {
411  int i;
412  int ctlr;
413  unsigned int cnt = 0;
414 
415  ctlr = irq2ctlr(irq);
416  if (ctlr < 0)
417  return IRQ_NONE;
418 
419  dev_dbg(data, "dma_ccerr_handler\n");
420 
421  if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
422  (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
423  (edma_read(ctlr, EDMA_QEMR) == 0) &&
424  (edma_read(ctlr, EDMA_CCERR) == 0))
425  return IRQ_NONE;
426 
427  while (1) {
428  int j = -1;
429  if (edma_read_array(ctlr, EDMA_EMR, 0))
430  j = 0;
431  else if (edma_read_array(ctlr, EDMA_EMR, 1))
432  j = 1;
433  if (j >= 0) {
434  dev_dbg(data, "EMR%d %08x\n", j,
435  edma_read_array(ctlr, EDMA_EMR, j));
436  for (i = 0; i < 32; i++) {
437  int k = (j << 5) + i;
438  if (edma_read_array(ctlr, EDMA_EMR, j) &
439  BIT(i)) {
440  /* Clear the corresponding EMR bits */
441  edma_write_array(ctlr, EDMA_EMCR, j,
442  BIT(i));
443  /* Clear any SER */
444  edma_shadow0_write_array(ctlr, SH_SECR,
445  j, BIT(i));
446  if (edma_cc[ctlr]->intr_data[k].
447  callback) {
448  edma_cc[ctlr]->intr_data[k].
449  callback(k,
450  DMA_CC_ERROR,
451  edma_cc[ctlr]->intr_data
452  [k].data);
453  }
454  }
455  }
456  } else if (edma_read(ctlr, EDMA_QEMR)) {
457  dev_dbg(data, "QEMR %02x\n",
458  edma_read(ctlr, EDMA_QEMR));
459  for (i = 0; i < 8; i++) {
460  if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
461  /* Clear the corresponding IPR bits */
462  edma_write(ctlr, EDMA_QEMCR, BIT(i));
463  edma_shadow0_write(ctlr, SH_QSECR,
464  BIT(i));
465 
466  /* NOTE: not reported!! */
467  }
468  }
469  } else if (edma_read(ctlr, EDMA_CCERR)) {
470  dev_dbg(data, "CCERR %08x\n",
471  edma_read(ctlr, EDMA_CCERR));
472  /* FIXME: CCERR.BIT(16) ignored! much better
473  * to just write CCERRCLR with CCERR value...
474  */
475  for (i = 0; i < 8; i++) {
476  if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
477  /* Clear the corresponding IPR bits */
478  edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
479 
480  /* NOTE: not reported!! */
481  }
482  }
483  }
484  if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
485  (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
486  (edma_read(ctlr, EDMA_QEMR) == 0) &&
487  (edma_read(ctlr, EDMA_CCERR) == 0))
488  break;
489  cnt++;
490  if (cnt > 10)
491  break;
492  }
493  edma_write(ctlr, EDMA_EEVAL, 1);
494  return IRQ_HANDLED;
495 }
496 
497 /******************************************************************************
498  *
499  * Transfer controller error interrupt handlers
500  *
501  *****************************************************************************/
502 
503 #define tc_errs_handled false /* disabled as long as they're NOPs */
504 
505 static irqreturn_t dma_tc0err_handler(int irq, void *data)
506 {
507  dev_dbg(data, "dma_tc0err_handler\n");
508  return IRQ_HANDLED;
509 }
510 
511 static irqreturn_t dma_tc1err_handler(int irq, void *data)
512 {
513  dev_dbg(data, "dma_tc1err_handler\n");
514  return IRQ_HANDLED;
515 }
516 
517 static int reserve_contiguous_slots(int ctlr, unsigned int id,
518  unsigned int num_slots,
519  unsigned int start_slot)
520 {
521  int i, j;
522  unsigned int count = num_slots;
523  int stop_slot = start_slot;
524  DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
525 
526  for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
527  j = EDMA_CHAN_SLOT(i);
528  if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
529  /* Record our current beginning slot */
530  if (count == num_slots)
531  stop_slot = i;
532 
533  count--;
534  set_bit(j, tmp_inuse);
535 
536  if (count == 0)
537  break;
538  } else {
539  clear_bit(j, tmp_inuse);
540 
541  if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
542  stop_slot = i;
543  break;
544  } else {
545  count = num_slots;
546  }
547  }
548  }
549 
550  /*
551  * We have to clear any bits that we set
552  * if we run out parameter RAM slots, i.e we do find a set
553  * of contiguous parameter RAM slots but do not find the exact number
554  * requested as we may reach the total number of parameter RAM slots
555  */
556  if (i == edma_cc[ctlr]->num_slots)
557  stop_slot = i;
558 
559  j = start_slot;
560  for_each_set_bit_from(j, tmp_inuse, stop_slot)
561  clear_bit(j, edma_cc[ctlr]->edma_inuse);
562 
563  if (count)
564  return -EBUSY;
565 
566  for (j = i - num_slots + 1; j <= i; ++j)
567  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
568  &dummy_paramset, PARM_SIZE);
569 
570  return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
571 }
572 
573 static int prepare_unused_channel_list(struct device *dev, void *data)
574 {
575  struct platform_device *pdev = to_platform_device(dev);
576  int i, ctlr;
577 
578  for (i = 0; i < pdev->num_resources; i++) {
579  if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
580  (int)pdev->resource[i].start >= 0) {
581  ctlr = EDMA_CTLR(pdev->resource[i].start);
582  clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
583  edma_cc[ctlr]->edma_unused);
584  }
585  }
586 
587  return 0;
588 }
589 
590 /*-----------------------------------------------------------------------*/
591 
592 static bool unused_chan_list_done;
593 
594 /* Resource alloc/free: dma channels, parameter RAM slots */
595 
626 int edma_alloc_channel(int channel,
627  void (*callback)(unsigned channel, u16 ch_status, void *data),
628  void *data,
629  enum dma_event_q eventq_no)
630 {
631  unsigned i, done = 0, ctlr = 0;
632  int ret = 0;
633 
634  if (!unused_chan_list_done) {
635  /*
636  * Scan all the platform devices to find out the EDMA channels
637  * used and clear them in the unused list, making the rest
638  * available for ARM usage.
639  */
640  ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
641  prepare_unused_channel_list);
642  if (ret < 0)
643  return ret;
644 
645  unused_chan_list_done = true;
646  }
647 
648  if (channel >= 0) {
649  ctlr = EDMA_CTLR(channel);
650  channel = EDMA_CHAN_SLOT(channel);
651  }
652 
653  if (channel < 0) {
654  for (i = 0; i < arch_num_cc; i++) {
655  channel = 0;
656  for (;;) {
657  channel = find_next_bit(edma_cc[i]->edma_unused,
658  edma_cc[i]->num_channels,
659  channel);
660  if (channel == edma_cc[i]->num_channels)
661  break;
662  if (!test_and_set_bit(channel,
663  edma_cc[i]->edma_inuse)) {
664  done = 1;
665  ctlr = i;
666  break;
667  }
668  channel++;
669  }
670  if (done)
671  break;
672  }
673  if (!done)
674  return -ENOMEM;
675  } else if (channel >= edma_cc[ctlr]->num_channels) {
676  return -EINVAL;
677  } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
678  return -EBUSY;
679  }
680 
681  /* ensure access through shadow region 0 */
682  edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
683 
684  /* ensure no events are pending */
685  edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
686  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
687  &dummy_paramset, PARM_SIZE);
688 
689  if (callback)
690  setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
691  callback, data);
692 
693  map_dmach_queue(ctlr, channel, eventq_no);
694 
695  return EDMA_CTLR_CHAN(ctlr, channel);
696 }
697 EXPORT_SYMBOL(edma_alloc_channel);
698 
699 
711 void edma_free_channel(unsigned channel)
712 {
713  unsigned ctlr;
714 
715  ctlr = EDMA_CTLR(channel);
716  channel = EDMA_CHAN_SLOT(channel);
717 
718  if (channel >= edma_cc[ctlr]->num_channels)
719  return;
720 
721  setup_dma_interrupt(channel, NULL, NULL);
722  /* REVISIT should probably take out of shadow region 0 */
723 
724  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
725  &dummy_paramset, PARM_SIZE);
726  clear_bit(channel, edma_cc[ctlr]->edma_inuse);
727 }
728 EXPORT_SYMBOL(edma_free_channel);
729 
744 int edma_alloc_slot(unsigned ctlr, int slot)
745 {
746  if (slot >= 0)
747  slot = EDMA_CHAN_SLOT(slot);
748 
749  if (slot < 0) {
750  slot = edma_cc[ctlr]->num_channels;
751  for (;;) {
752  slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
753  edma_cc[ctlr]->num_slots, slot);
754  if (slot == edma_cc[ctlr]->num_slots)
755  return -ENOMEM;
756  if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
757  break;
758  }
759  } else if (slot < edma_cc[ctlr]->num_channels ||
760  slot >= edma_cc[ctlr]->num_slots) {
761  return -EINVAL;
762  } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
763  return -EBUSY;
764  }
765 
766  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
767  &dummy_paramset, PARM_SIZE);
768 
769  return EDMA_CTLR_CHAN(ctlr, slot);
770 }
771 EXPORT_SYMBOL(edma_alloc_slot);
772 
781 void edma_free_slot(unsigned slot)
782 {
783  unsigned ctlr;
784 
785  ctlr = EDMA_CTLR(slot);
786  slot = EDMA_CHAN_SLOT(slot);
787 
788  if (slot < edma_cc[ctlr]->num_channels ||
789  slot >= edma_cc[ctlr]->num_slots)
790  return;
791 
792  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
793  &dummy_paramset, PARM_SIZE);
794  clear_bit(slot, edma_cc[ctlr]->edma_inuse);
795 }
796 EXPORT_SYMBOL(edma_free_slot);
797 
798 
824 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
825 {
826  /*
827  * The start slot requested should be greater than
828  * the number of channels and lesser than the total number
829  * of slots
830  */
831  if ((id != EDMA_CONT_PARAMS_ANY) &&
832  (slot < edma_cc[ctlr]->num_channels ||
833  slot >= edma_cc[ctlr]->num_slots))
834  return -EINVAL;
835 
836  /*
837  * The number of parameter RAM slots requested cannot be less than 1
838  * and cannot be more than the number of slots minus the number of
839  * channels
840  */
841  if (count < 1 || count >
842  (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
843  return -EINVAL;
844 
845  switch (id) {
846  case EDMA_CONT_PARAMS_ANY:
847  return reserve_contiguous_slots(ctlr, id, count,
848  edma_cc[ctlr]->num_channels);
849  case EDMA_CONT_PARAMS_FIXED_EXACT:
850  case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
851  return reserve_contiguous_slots(ctlr, id, count, slot);
852  default:
853  return -EINVAL;
854  }
855 
856 }
857 EXPORT_SYMBOL(edma_alloc_cont_slots);
858 
872 int edma_free_cont_slots(unsigned slot, int count)
873 {
874  unsigned ctlr, slot_to_free;
875  int i;
876 
877  ctlr = EDMA_CTLR(slot);
878  slot = EDMA_CHAN_SLOT(slot);
879 
880  if (slot < edma_cc[ctlr]->num_channels ||
881  slot >= edma_cc[ctlr]->num_slots ||
882  count < 1)
883  return -EINVAL;
884 
885  for (i = slot; i < slot + count; ++i) {
886  ctlr = EDMA_CTLR(i);
887  slot_to_free = EDMA_CHAN_SLOT(i);
888 
889  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
890  &dummy_paramset, PARM_SIZE);
891  clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
892  }
893 
894  return 0;
895 }
896 EXPORT_SYMBOL(edma_free_cont_slots);
897 
898 /*-----------------------------------------------------------------------*/
899 
900 /* Parameter RAM operations (i) -- read/write partial slots */
901 
913 void edma_set_src(unsigned slot, dma_addr_t src_port,
914  enum address_mode mode, enum fifo_width width)
915 {
916  unsigned ctlr;
917 
918  ctlr = EDMA_CTLR(slot);
919  slot = EDMA_CHAN_SLOT(slot);
920 
921  if (slot < edma_cc[ctlr]->num_slots) {
922  unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
923 
924  if (mode) {
925  /* set SAM and program FWID */
926  i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
927  } else {
928  /* clear SAM */
929  i &= ~SAM;
930  }
931  edma_parm_write(ctlr, PARM_OPT, slot, i);
932 
933  /* set the source port address
934  in source register of param structure */
935  edma_parm_write(ctlr, PARM_SRC, slot, src_port);
936  }
937 }
938 EXPORT_SYMBOL(edma_set_src);
939 
951 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
952  enum address_mode mode, enum fifo_width width)
953 {
954  unsigned ctlr;
955 
956  ctlr = EDMA_CTLR(slot);
957  slot = EDMA_CHAN_SLOT(slot);
958 
959  if (slot < edma_cc[ctlr]->num_slots) {
960  unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
961 
962  if (mode) {
963  /* set DAM and program FWID */
964  i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
965  } else {
966  /* clear DAM */
967  i &= ~DAM;
968  }
969  edma_parm_write(ctlr, PARM_OPT, slot, i);
970  /* set the destination port address
971  in dest register of param structure */
972  edma_parm_write(ctlr, PARM_DST, slot, dest_port);
973  }
974 }
975 EXPORT_SYMBOL(edma_set_dest);
976 
986 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
987 {
988  struct edmacc_param temp;
989  unsigned ctlr;
990 
991  ctlr = EDMA_CTLR(slot);
992  slot = EDMA_CHAN_SLOT(slot);
993 
994  edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
995  if (src != NULL)
996  *src = temp.src;
997  if (dst != NULL)
998  *dst = temp.dst;
999 }
1000 EXPORT_SYMBOL(edma_get_position);
1001 
1012 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1013 {
1014  unsigned ctlr;
1015 
1016  ctlr = EDMA_CTLR(slot);
1017  slot = EDMA_CHAN_SLOT(slot);
1018 
1019  if (slot < edma_cc[ctlr]->num_slots) {
1020  edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1021  0xffff0000, src_bidx);
1022  edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1023  0xffff0000, src_cidx);
1024  }
1025 }
1026 EXPORT_SYMBOL(edma_set_src_index);
1027 
1038 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1039 {
1040  unsigned ctlr;
1041 
1042  ctlr = EDMA_CTLR(slot);
1043  slot = EDMA_CHAN_SLOT(slot);
1044 
1045  if (slot < edma_cc[ctlr]->num_slots) {
1046  edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1047  0x0000ffff, dest_bidx << 16);
1048  edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1049  0x0000ffff, dest_cidx << 16);
1050  }
1051 }
1052 EXPORT_SYMBOL(edma_set_dest_index);
1053 
1083 void edma_set_transfer_params(unsigned slot,
1084  u16 acnt, u16 bcnt, u16 ccnt,
1085  u16 bcnt_rld, enum sync_dimension sync_mode)
1086 {
1087  unsigned ctlr;
1088 
1089  ctlr = EDMA_CTLR(slot);
1090  slot = EDMA_CHAN_SLOT(slot);
1091 
1092  if (slot < edma_cc[ctlr]->num_slots) {
1093  edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1094  0x0000ffff, bcnt_rld << 16);
1095  if (sync_mode == ASYNC)
1096  edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1097  else
1098  edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1099  /* Set the acount, bcount, ccount registers */
1100  edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1101  edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1102  }
1103 }
1104 EXPORT_SYMBOL(edma_set_transfer_params);
1105 
1113 void edma_link(unsigned from, unsigned to)
1114 {
1115  unsigned ctlr_from, ctlr_to;
1116 
1117  ctlr_from = EDMA_CTLR(from);
1118  from = EDMA_CHAN_SLOT(from);
1119  ctlr_to = EDMA_CTLR(to);
1120  to = EDMA_CHAN_SLOT(to);
1121 
1122  if (from >= edma_cc[ctlr_from]->num_slots)
1123  return;
1124  if (to >= edma_cc[ctlr_to]->num_slots)
1125  return;
1126  edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1127  PARM_OFFSET(to));
1128 }
1129 EXPORT_SYMBOL(edma_link);
1130 
1138 void edma_unlink(unsigned from)
1139 {
1140  unsigned ctlr;
1141 
1142  ctlr = EDMA_CTLR(from);
1143  from = EDMA_CHAN_SLOT(from);
1144 
1145  if (from >= edma_cc[ctlr]->num_slots)
1146  return;
1147  edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1148 }
1149 EXPORT_SYMBOL(edma_unlink);
1150 
1151 /*-----------------------------------------------------------------------*/
1152 
1153 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1154 
1165 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1166 {
1167  unsigned ctlr;
1168 
1169  ctlr = EDMA_CTLR(slot);
1170  slot = EDMA_CHAN_SLOT(slot);
1171 
1172  if (slot >= edma_cc[ctlr]->num_slots)
1173  return;
1174  memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1175  PARM_SIZE);
1176 }
1177 EXPORT_SYMBOL(edma_write_slot);
1178 
1187 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1188 {
1189  unsigned ctlr;
1190 
1191  ctlr = EDMA_CTLR(slot);
1192  slot = EDMA_CHAN_SLOT(slot);
1193 
1194  if (slot >= edma_cc[ctlr]->num_slots)
1195  return;
1196  memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1197  PARM_SIZE);
1198 }
1199 EXPORT_SYMBOL(edma_read_slot);
1200 
1201 /*-----------------------------------------------------------------------*/
1202 
1203 /* Various EDMA channel control operations */
1204 
1212 void edma_pause(unsigned channel)
1213 {
1214  unsigned ctlr;
1215 
1216  ctlr = EDMA_CTLR(channel);
1217  channel = EDMA_CHAN_SLOT(channel);
1218 
1219  if (channel < edma_cc[ctlr]->num_channels) {
1220  unsigned int mask = BIT(channel & 0x1f);
1221 
1222  edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1223  }
1224 }
1225 EXPORT_SYMBOL(edma_pause);
1226 
1233 void edma_resume(unsigned channel)
1234 {
1235  unsigned ctlr;
1236 
1237  ctlr = EDMA_CTLR(channel);
1238  channel = EDMA_CHAN_SLOT(channel);
1239 
1240  if (channel < edma_cc[ctlr]->num_channels) {
1241  unsigned int mask = BIT(channel & 0x1f);
1242 
1243  edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1244  }
1245 }
1246 EXPORT_SYMBOL(edma_resume);
1247 
1259 int edma_start(unsigned channel)
1260 {
1261  unsigned ctlr;
1262 
1263  ctlr = EDMA_CTLR(channel);
1264  channel = EDMA_CHAN_SLOT(channel);
1265 
1266  if (channel < edma_cc[ctlr]->num_channels) {
1267  int j = channel >> 5;
1268  unsigned int mask = BIT(channel & 0x1f);
1269 
1270  /* EDMA channels without event association */
1271  if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1272  pr_debug("EDMA: ESR%d %08x\n", j,
1273  edma_shadow0_read_array(ctlr, SH_ESR, j));
1274  edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1275  return 0;
1276  }
1277 
1278  /* EDMA channel with event association */
1279  pr_debug("EDMA: ER%d %08x\n", j,
1280  edma_shadow0_read_array(ctlr, SH_ER, j));
1281  /* Clear any pending event or error */
1282  edma_write_array(ctlr, EDMA_ECR, j, mask);
1283  edma_write_array(ctlr, EDMA_EMCR, j, mask);
1284  /* Clear any SER */
1285  edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1286  edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1287  pr_debug("EDMA: EER%d %08x\n", j,
1288  edma_shadow0_read_array(ctlr, SH_EER, j));
1289  return 0;
1290  }
1291 
1292  return -EINVAL;
1293 }
1294 EXPORT_SYMBOL(edma_start);
1295 
1305 void edma_stop(unsigned channel)
1306 {
1307  unsigned ctlr;
1308 
1309  ctlr = EDMA_CTLR(channel);
1310  channel = EDMA_CHAN_SLOT(channel);
1311 
1312  if (channel < edma_cc[ctlr]->num_channels) {
1313  int j = channel >> 5;
1314  unsigned int mask = BIT(channel & 0x1f);
1315 
1316  edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1317  edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1318  edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1319  edma_write_array(ctlr, EDMA_EMCR, j, mask);
1320 
1321  pr_debug("EDMA: EER%d %08x\n", j,
1322  edma_shadow0_read_array(ctlr, SH_EER, j));
1323 
1324  /* REVISIT: consider guarding against inappropriate event
1325  * chaining by overwriting with dummy_paramset.
1326  */
1327  }
1328 }
1329 EXPORT_SYMBOL(edma_stop);
1330 
1331 /******************************************************************************
1332  *
1333  * It cleans ParamEntry qand bring back EDMA to initial state if media has
1334  * been removed before EDMA has finished.It is usedful for removable media.
1335  * Arguments:
1336  * ch_no - channel no
1337  *
1338  * Return: zero on success, or corresponding error no on failure
1339  *
1340  * FIXME this should not be needed ... edma_stop() should suffice.
1341  *
1342  *****************************************************************************/
1343 
1344 void edma_clean_channel(unsigned channel)
1345 {
1346  unsigned ctlr;
1347 
1348  ctlr = EDMA_CTLR(channel);
1349  channel = EDMA_CHAN_SLOT(channel);
1350 
1351  if (channel < edma_cc[ctlr]->num_channels) {
1352  int j = (channel >> 5);
1353  unsigned int mask = BIT(channel & 0x1f);
1354 
1355  pr_debug("EDMA: EMR%d %08x\n", j,
1356  edma_read_array(ctlr, EDMA_EMR, j));
1357  edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1358  /* Clear the corresponding EMR bits */
1359  edma_write_array(ctlr, EDMA_EMCR, j, mask);
1360  /* Clear any SER */
1361  edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1362  edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1363  }
1364 }
1365 EXPORT_SYMBOL(edma_clean_channel);
1366 
1367 /*
1368  * edma_clear_event - clear an outstanding event on the DMA channel
1369  * Arguments:
1370  * channel - channel number
1371  */
1372 void edma_clear_event(unsigned channel)
1373 {
1374  unsigned ctlr;
1375 
1376  ctlr = EDMA_CTLR(channel);
1377  channel = EDMA_CHAN_SLOT(channel);
1378 
1379  if (channel >= edma_cc[ctlr]->num_channels)
1380  return;
1381  if (channel < 32)
1382  edma_write(ctlr, EDMA_ECR, BIT(channel));
1383  else
1384  edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1385 }
1386 EXPORT_SYMBOL(edma_clear_event);
1387 
1388 /*-----------------------------------------------------------------------*/
1389 
1390 static int __init edma_probe(struct platform_device *pdev)
1391 {
1392  struct edma_soc_info **info = pdev->dev.platform_data;
1393  const s8 (*queue_priority_mapping)[2];
1394  const s8 (*queue_tc_mapping)[2];
1395  int i, j, off, ln, found = 0;
1396  int status = -1;
1397  const s16 (*rsv_chans)[2];
1398  const s16 (*rsv_slots)[2];
1399  int irq[EDMA_MAX_CC] = {0, 0};
1400  int err_irq[EDMA_MAX_CC] = {0, 0};
1401  struct resource *r[EDMA_MAX_CC] = {NULL};
1402  resource_size_t len[EDMA_MAX_CC];
1403  char res_name[10];
1404  char irq_name[10];
1405 
1406  if (!info)
1407  return -ENODEV;
1408 
1409  for (j = 0; j < EDMA_MAX_CC; j++) {
1410  sprintf(res_name, "edma_cc%d", j);
1411  r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1412  res_name);
1413  if (!r[j] || !info[j]) {
1414  if (found)
1415  break;
1416  else
1417  return -ENODEV;
1418  } else {
1419  found = 1;
1420  }
1421 
1422  len[j] = resource_size(r[j]);
1423 
1424  r[j] = request_mem_region(r[j]->start, len[j],
1425  dev_name(&pdev->dev));
1426  if (!r[j]) {
1427  status = -EBUSY;
1428  goto fail1;
1429  }
1430 
1431  edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
1432  if (!edmacc_regs_base[j]) {
1433  status = -EBUSY;
1434  goto fail1;
1435  }
1436 
1437  edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
1438  if (!edma_cc[j]) {
1439  status = -ENOMEM;
1440  goto fail1;
1441  }
1442 
1443  edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1444  EDMA_MAX_DMACH);
1445  edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
1446  EDMA_MAX_PARAMENTRY);
1447  edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
1448  EDMA_MAX_CC);
1449 
1450  edma_cc[j]->default_queue = info[j]->default_queue;
1451 
1452  dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1453  edmacc_regs_base[j]);
1454 
1455  for (i = 0; i < edma_cc[j]->num_slots; i++)
1456  memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1457  &dummy_paramset, PARM_SIZE);
1458 
1459  /* Mark all channels as unused */
1460  memset(edma_cc[j]->edma_unused, 0xff,
1461  sizeof(edma_cc[j]->edma_unused));
1462 
1463  if (info[j]->rsv) {
1464 
1465  /* Clear the reserved channels in unused list */
1466  rsv_chans = info[j]->rsv->rsv_chans;
1467  if (rsv_chans) {
1468  for (i = 0; rsv_chans[i][0] != -1; i++) {
1469  off = rsv_chans[i][0];
1470  ln = rsv_chans[i][1];
1471  clear_bits(off, ln,
1472  edma_cc[j]->edma_unused);
1473  }
1474  }
1475 
1476  /* Set the reserved slots in inuse list */
1477  rsv_slots = info[j]->rsv->rsv_slots;
1478  if (rsv_slots) {
1479  for (i = 0; rsv_slots[i][0] != -1; i++) {
1480  off = rsv_slots[i][0];
1481  ln = rsv_slots[i][1];
1482  set_bits(off, ln,
1483  edma_cc[j]->edma_inuse);
1484  }
1485  }
1486  }
1487 
1488  sprintf(irq_name, "edma%d", j);
1489  irq[j] = platform_get_irq_byname(pdev, irq_name);
1490  edma_cc[j]->irq_res_start = irq[j];
1491  status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1492  &pdev->dev);
1493  if (status < 0) {
1494  dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1495  irq[j], status);
1496  goto fail;
1497  }
1498 
1499  sprintf(irq_name, "edma%d_err", j);
1500  err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1501  edma_cc[j]->irq_res_end = err_irq[j];
1502  status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1503  "edma_error", &pdev->dev);
1504  if (status < 0) {
1505  dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1506  err_irq[j], status);
1507  goto fail;
1508  }
1509 
1510  for (i = 0; i < edma_cc[j]->num_channels; i++)
1511  map_dmach_queue(j, i, info[j]->default_queue);
1512 
1513  queue_tc_mapping = info[j]->queue_tc_mapping;
1514  queue_priority_mapping = info[j]->queue_priority_mapping;
1515 
1516  /* Event queue to TC mapping */
1517  for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1518  map_queue_tc(j, queue_tc_mapping[i][0],
1519  queue_tc_mapping[i][1]);
1520 
1521  /* Event queue priority mapping */
1522  for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1523  assign_priority_to_queue(j,
1524  queue_priority_mapping[i][0],
1525  queue_priority_mapping[i][1]);
1526 
1527  /* Map the channel to param entry if channel mapping logic
1528  * exist
1529  */
1530  if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1531  map_dmach_param(j);
1532 
1533  for (i = 0; i < info[j]->n_region; i++) {
1534  edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1535  edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1536  edma_write_array(j, EDMA_QRAE, i, 0x0);
1537  }
1538  arch_num_cc++;
1539  }
1540 
1541  if (tc_errs_handled) {
1542  status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
1543  "edma_tc0", &pdev->dev);
1544  if (status < 0) {
1545  dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1546  IRQ_TCERRINT0, status);
1547  return status;
1548  }
1549  status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
1550  "edma_tc1", &pdev->dev);
1551  if (status < 0) {
1552  dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
1553  IRQ_TCERRINT, status);
1554  return status;
1555  }
1556  }
1557 
1558  return 0;
1559 
1560 fail:
1561  for (i = 0; i < EDMA_MAX_CC; i++) {
1562  if (err_irq[i])
1563  free_irq(err_irq[i], &pdev->dev);
1564  if (irq[i])
1565  free_irq(irq[i], &pdev->dev);
1566  }
1567 fail1:
1568  for (i = 0; i < EDMA_MAX_CC; i++) {
1569  if (r[i])
1570  release_mem_region(r[i]->start, len[i]);
1571  if (edmacc_regs_base[i])
1572  iounmap(edmacc_regs_base[i]);
1573  kfree(edma_cc[i]);
1574  }
1575  return status;
1576 }
1577 
1578 
1579 static struct platform_driver edma_driver = {
1580  .driver.name = "edma",
1581 };
1582 
1583 static int __init edma_init(void)
1584 {
1585  return platform_driver_probe(&edma_driver, edma_probe);
1586 }
1587 arch_initcall(edma_init);
1588 
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