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tegra20_clocks_data.c
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1 /*
2  * arch/arm/mach-tegra/tegra2_clocks.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6  *
7  * Author:
8  * Colin Cross <[email protected]>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  */
20 
21 #include <linux/clk-private.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/clk.h>
29 
30 #include <mach/iomap.h>
31 
32 #include "clock.h"
33 #include "fuse.h"
34 #include "tegra2_emc.h"
35 #include "tegra20_clocks.h"
36 #include "tegra_cpu_car.h"
37 
38 /* Clock definitions */
39 
40 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
41  _parent_names, _parents, _parent) \
42  static struct clk tegra_##_name = { \
43  .hw = &tegra_##_name##_hw.hw, \
44  .name = #_name, \
45  .rate = _rate, \
46  .ops = _ops, \
47  .flags = _flags, \
48  .parent_names = _parent_names, \
49  .parents = _parents, \
50  .num_parents = ARRAY_SIZE(_parent_names), \
51  .parent = _parent, \
52  };
53 
54 static struct clk tegra_clk_32k;
55 static struct clk_tegra tegra_clk_32k_hw = {
56  .hw = {
57  .clk = &tegra_clk_32k,
58  },
59  .fixed_rate = 32768,
60 };
61 
62 static struct clk tegra_clk_32k = {
63  .name = "clk_32k",
64  .rate = 32768,
65  .ops = &tegra_clk_32k_ops,
66  .hw = &tegra_clk_32k_hw.hw,
67  .flags = CLK_IS_ROOT,
68 };
69 
70 static struct clk tegra_clk_m;
71 static struct clk_tegra tegra_clk_m_hw = {
72  .hw = {
73  .clk = &tegra_clk_m,
74  },
75  .flags = ENABLE_ON_INIT,
76  .reg = 0x1fc,
77  .reg_shift = 28,
78  .max_rate = 26000000,
79  .fixed_rate = 0,
80 };
81 
82 static struct clk tegra_clk_m = {
83  .name = "clk_m",
84  .ops = &tegra_clk_m_ops,
85  .hw = &tegra_clk_m_hw.hw,
86  .flags = CLK_IS_ROOT,
87 };
88 
89 #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
90  _input_max, _cf_min, _cf_max, _vco_min, \
91  _vco_max, _freq_table, _lock_delay, _ops, \
92  _fixed_rate, _parent) \
93  static const char *tegra_##_name##_parent_names[] = { \
94  #_parent, \
95  }; \
96  static struct clk *tegra_##_name##_parents[] = { \
97  &tegra_##_parent, \
98  }; \
99  static struct clk tegra_##_name; \
100  static struct clk_tegra tegra_##_name##_hw = { \
101  .hw = { \
102  .clk = &tegra_##_name, \
103  }, \
104  .flags = _flags, \
105  .reg = _reg, \
106  .max_rate = _max_rate, \
107  .u.pll = { \
108  .input_min = _input_min, \
109  .input_max = _input_max, \
110  .cf_min = _cf_min, \
111  .cf_max = _cf_max, \
112  .vco_min = _vco_min, \
113  .vco_max = _vco_max, \
114  .freq_table = _freq_table, \
115  .lock_delay = _lock_delay, \
116  .fixed_rate = _fixed_rate, \
117  }, \
118  }; \
119  static struct clk tegra_##_name = { \
120  .name = #_name, \
121  .ops = &_ops, \
122  .hw = &tegra_##_name##_hw.hw, \
123  .parent = &tegra_##_parent, \
124  .parent_names = tegra_##_name##_parent_names, \
125  .parents = tegra_##_name##_parents, \
126  .num_parents = 1, \
127  };
128 
129 #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
130  _max_rate, _ops, _parent, _clk_flags) \
131  static const char *tegra_##_name##_parent_names[] = { \
132  #_parent, \
133  }; \
134  static struct clk *tegra_##_name##_parents[] = { \
135  &tegra_##_parent, \
136  }; \
137  static struct clk tegra_##_name; \
138  static struct clk_tegra tegra_##_name##_hw = { \
139  .hw = { \
140  .clk = &tegra_##_name, \
141  }, \
142  .flags = _flags, \
143  .reg = _reg, \
144  .max_rate = _max_rate, \
145  .reg_shift = _reg_shift, \
146  }; \
147  static struct clk tegra_##_name = { \
148  .name = #_name, \
149  .ops = &tegra_pll_div_ops, \
150  .hw = &tegra_##_name##_hw.hw, \
151  .parent = &tegra_##_parent, \
152  .parent_names = tegra_##_name##_parent_names, \
153  .parents = tegra_##_name##_parents, \
154  .num_parents = 1, \
155  .flags = _clk_flags, \
156  };
157 
158 
159 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
160  {32768, 12000000, 366, 1, 1, 0},
161  {32768, 13000000, 397, 1, 1, 0},
162  {32768, 19200000, 586, 1, 1, 0},
163  {32768, 26000000, 793, 1, 1, 0},
164  {0, 0, 0, 0, 0, 0},
165 };
166 
167 DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
168  0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
169  tegra_pll_ops, 0, clk_32k);
170 
171 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
172  { 12000000, 600000000, 600, 12, 1, 8 },
173  { 13000000, 600000000, 600, 13, 1, 8 },
174  { 19200000, 600000000, 500, 16, 1, 6 },
175  { 26000000, 600000000, 600, 26, 1, 8 },
176  { 0, 0, 0, 0, 0, 0 },
177 };
178 
179 DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
180  6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
181  tegra_pll_ops, 0, clk_m);
182 
183 DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
184  tegra_pll_div_ops, pll_c, 0);
185 
186 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
187  { 12000000, 666000000, 666, 12, 1, 8},
188  { 13000000, 666000000, 666, 13, 1, 8},
189  { 19200000, 666000000, 555, 16, 1, 8},
190  { 26000000, 666000000, 666, 26, 1, 8},
191  { 12000000, 600000000, 600, 12, 1, 8},
192  { 13000000, 600000000, 600, 13, 1, 8},
193  { 19200000, 600000000, 375, 12, 1, 6},
194  { 26000000, 600000000, 600, 26, 1, 8},
195  { 0, 0, 0, 0, 0, 0 },
196 };
197 
198 DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
199  6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
200  tegra_pll_ops, 0, clk_m);
201 
202 DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
203  tegra_pll_div_ops, pll_m, 0);
204 
205 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
206  { 12000000, 216000000, 432, 12, 2, 8},
207  { 13000000, 216000000, 432, 13, 2, 8},
208  { 19200000, 216000000, 90, 4, 2, 1},
209  { 26000000, 216000000, 432, 26, 2, 8},
210  { 12000000, 432000000, 432, 12, 1, 8},
211  { 13000000, 432000000, 432, 13, 1, 8},
212  { 19200000, 432000000, 90, 4, 1, 1},
213  { 26000000, 432000000, 432, 26, 1, 8},
214  { 0, 0, 0, 0, 0, 0 },
215 };
216 
217 
218 DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
219  2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
220  tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
221 
222 DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
223  432000000, tegra_pll_div_ops, pll_p, 0);
224 DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
225  432000000, tegra_pll_div_ops, pll_p, 0);
226 DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
227  432000000, tegra_pll_div_ops, pll_p, 0);
228 DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
229  432000000, tegra_pll_div_ops, pll_p, 0);
230 
231 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
232  { 28800000, 56448000, 49, 25, 1, 1},
233  { 28800000, 73728000, 64, 25, 1, 1},
234  { 28800000, 24000000, 5, 6, 1, 1},
235  { 0, 0, 0, 0, 0, 0 },
236 };
237 
238 DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
239  6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
240  tegra_pll_ops, 0, pll_p_out1);
241 
242 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
243  tegra_pll_div_ops, pll_a, 0);
244 
245 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
246  { 12000000, 216000000, 216, 12, 1, 4},
247  { 13000000, 216000000, 216, 13, 1, 4},
248  { 19200000, 216000000, 135, 12, 1, 3},
249  { 26000000, 216000000, 216, 26, 1, 4},
250 
251  { 12000000, 594000000, 594, 12, 1, 8},
252  { 13000000, 594000000, 594, 13, 1, 8},
253  { 19200000, 594000000, 495, 16, 1, 8},
254  { 26000000, 594000000, 594, 26, 1, 8},
255 
256  { 12000000, 1000000000, 1000, 12, 1, 12},
257  { 13000000, 1000000000, 1000, 13, 1, 12},
258  { 19200000, 1000000000, 625, 12, 1, 8},
259  { 26000000, 1000000000, 1000, 26, 1, 12},
260 
261  { 0, 0, 0, 0, 0, 0 },
262 };
263 
264 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
265  1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
266  1000, tegra_pll_ops, 0, clk_m);
267 
268 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
269  tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
270 
271 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
272  { 12000000, 480000000, 960, 12, 2, 0},
273  { 13000000, 480000000, 960, 13, 2, 0},
274  { 19200000, 480000000, 200, 4, 2, 0},
275  { 26000000, 480000000, 960, 26, 2, 0},
276  { 0, 0, 0, 0, 0, 0 },
277 };
278 
279 DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
280  48000000, 960000000, tegra_pll_u_freq_table, 1000,
281  tegra_pll_ops, 0, clk_m);
282 
283 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
284  /* 1 GHz */
285  { 12000000, 1000000000, 1000, 12, 1, 12},
286  { 13000000, 1000000000, 1000, 13, 1, 12},
287  { 19200000, 1000000000, 625, 12, 1, 8},
288  { 26000000, 1000000000, 1000, 26, 1, 12},
289 
290  /* 912 MHz */
291  { 12000000, 912000000, 912, 12, 1, 12},
292  { 13000000, 912000000, 912, 13, 1, 12},
293  { 19200000, 912000000, 760, 16, 1, 8},
294  { 26000000, 912000000, 912, 26, 1, 12},
295 
296  /* 816 MHz */
297  { 12000000, 816000000, 816, 12, 1, 12},
298  { 13000000, 816000000, 816, 13, 1, 12},
299  { 19200000, 816000000, 680, 16, 1, 8},
300  { 26000000, 816000000, 816, 26, 1, 12},
301 
302  /* 760 MHz */
303  { 12000000, 760000000, 760, 12, 1, 12},
304  { 13000000, 760000000, 760, 13, 1, 12},
305  { 19200000, 760000000, 950, 24, 1, 8},
306  { 26000000, 760000000, 760, 26, 1, 12},
307 
308  /* 750 MHz */
309  { 12000000, 750000000, 750, 12, 1, 12},
310  { 13000000, 750000000, 750, 13, 1, 12},
311  { 19200000, 750000000, 625, 16, 1, 8},
312  { 26000000, 750000000, 750, 26, 1, 12},
313 
314  /* 608 MHz */
315  { 12000000, 608000000, 608, 12, 1, 12},
316  { 13000000, 608000000, 608, 13, 1, 12},
317  { 19200000, 608000000, 380, 12, 1, 8},
318  { 26000000, 608000000, 608, 26, 1, 12},
319 
320  /* 456 MHz */
321  { 12000000, 456000000, 456, 12, 1, 12},
322  { 13000000, 456000000, 456, 13, 1, 12},
323  { 19200000, 456000000, 380, 16, 1, 8},
324  { 26000000, 456000000, 456, 26, 1, 12},
325 
326  /* 312 MHz */
327  { 12000000, 312000000, 312, 12, 1, 12},
328  { 13000000, 312000000, 312, 13, 1, 12},
329  { 19200000, 312000000, 260, 16, 1, 8},
330  { 26000000, 312000000, 312, 26, 1, 12},
331 
332  { 0, 0, 0, 0, 0, 0 },
333 };
334 
335 DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
336  31000000, 1000000, 6000000, 20000000, 1200000000,
337  tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
338 
339 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
340  { 12000000, 100000000, 200, 24, 1, 0 },
341  { 0, 0, 0, 0, 0, 0 },
342 };
343 
344 DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
345  0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
346 
347 static const char *tegra_common_parent_names[] = {
348  "clk_m",
349 };
350 
351 static struct clk *tegra_common_parents[] = {
352  &tegra_clk_m,
353 };
354 
355 static struct clk tegra_clk_d;
356 static struct clk_tegra tegra_clk_d_hw = {
357  .hw = {
358  .clk = &tegra_clk_d,
359  },
360  .flags = PERIPH_NO_RESET,
361  .reg = 0x34,
362  .reg_shift = 12,
363  .max_rate = 52000000,
364  .u.periph = {
365  .clk_num = 90,
366  },
367 };
368 
369 static struct clk tegra_clk_d = {
370  .name = "clk_d",
371  .hw = &tegra_clk_d_hw.hw,
372  .ops = &tegra_clk_double_ops,
373  .parent = &tegra_clk_m,
374  .parent_names = tegra_common_parent_names,
375  .parents = tegra_common_parents,
376  .num_parents = ARRAY_SIZE(tegra_common_parent_names),
377 };
378 
379 static struct clk tegra_cdev1;
380 static struct clk_tegra tegra_cdev1_hw = {
381  .hw = {
382  .clk = &tegra_cdev1,
383  },
384  .fixed_rate = 26000000,
385  .u.periph = {
386  .clk_num = 94,
387  },
388 };
389 static struct clk tegra_cdev1 = {
390  .name = "cdev1",
391  .hw = &tegra_cdev1_hw.hw,
392  .ops = &tegra_cdev_clk_ops,
393  .flags = CLK_IS_ROOT,
394 };
395 
396 /* dap_mclk2, belongs to the cdev2 pingroup. */
397 static struct clk tegra_cdev2;
398 static struct clk_tegra tegra_cdev2_hw = {
399  .hw = {
400  .clk = &tegra_cdev2,
401  },
402  .fixed_rate = 26000000,
403  .u.periph = {
404  .clk_num = 93,
405  },
406 };
407 static struct clk tegra_cdev2 = {
408  .name = "cdev2",
409  .hw = &tegra_cdev2_hw.hw,
410  .ops = &tegra_cdev_clk_ops,
411  .flags = CLK_IS_ROOT,
412 };
413 
414 /* initialized before peripheral clocks */
415 static struct clk_mux_sel mux_audio_sync_clk[8+1];
416 static const struct audio_sources {
417  const char *name;
418  int value;
419 } mux_audio_sync_clk_sources[] = {
420  { .name = "spdif_in", .value = 0 },
421  { .name = "i2s1", .value = 1 },
422  { .name = "i2s2", .value = 2 },
423  { .name = "pll_a_out0", .value = 4 },
424 #if 0 /* FIXME: not implemented */
425  { .name = "ac97", .value = 3 },
426  { .name = "ext_audio_clk2", .value = 5 },
427  { .name = "ext_audio_clk1", .value = 6 },
428  { .name = "ext_vimclk", .value = 7 },
429 #endif
430  { NULL, 0 }
431 };
432 
433 static const char *audio_parent_names[] = {
434  "spdif_in",
435  "i2s1",
436  "i2s2",
437  "dummy",
438  "pll_a_out0",
439  "dummy",
440  "dummy",
441  "dummy",
442 };
443 
444 static struct clk *audio_parents[] = {
445  NULL,
446  NULL,
447  NULL,
448  NULL,
449  NULL,
450  NULL,
451  NULL,
452  NULL,
453 };
454 
455 static struct clk tegra_audio;
456 static struct clk_tegra tegra_audio_hw = {
457  .hw = {
458  .clk = &tegra_audio,
459  },
460  .reg = 0x38,
461  .max_rate = 73728000,
462 };
463 DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
464  audio_parents, NULL);
465 
466 static const char *audio_2x_parent_names[] = {
467  "audio",
468 };
469 
470 static struct clk *audio_2x_parents[] = {
471  &tegra_audio,
472 };
473 
474 static struct clk tegra_audio_2x;
475 static struct clk_tegra tegra_audio_2x_hw = {
476  .hw = {
477  .clk = &tegra_audio_2x,
478  },
479  .flags = PERIPH_NO_RESET,
480  .max_rate = 48000000,
481  .reg = 0x34,
482  .reg_shift = 8,
483  .u.periph = {
484  .clk_num = 89,
485  },
486 };
487 DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
488  audio_2x_parents, &tegra_audio);
489 
490 static struct clk_lookup tegra_audio_clk_lookups[] = {
491  { .con_id = "audio", .clk = &tegra_audio },
492  { .con_id = "audio_2x", .clk = &tegra_audio_2x }
493 };
494 
495 /* This is called after peripheral clocks are initialized, as the
496  * audio_sync clock depends on some of the peripheral clocks.
497  */
498 
499 static void init_audio_sync_clock_mux(void)
500 {
501  int i;
502  struct clk_mux_sel *sel = mux_audio_sync_clk;
503  const struct audio_sources *src = mux_audio_sync_clk_sources;
504  struct clk_lookup *lookup;
505 
506  for (i = 0; src->name; i++, sel++, src++) {
507  sel->input = tegra_get_clock_by_name(src->name);
508  if (!sel->input)
509  pr_err("%s: could not find clk %s\n", __func__,
510  src->name);
511  audio_parents[src->value] = sel->input;
512  sel->value = src->value;
513  }
514 
515  lookup = tegra_audio_clk_lookups;
516  for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
517  struct clk *c = lookup->clk;
518  struct clk_tegra *clk = to_clk_tegra(c->hw);
519  __clk_init(NULL, c);
520  INIT_LIST_HEAD(&clk->shared_bus_list);
521  clk->lookup.con_id = lookup->con_id;
522  clk->lookup.clk = c;
523  clkdev_add(&clk->lookup);
524  tegra_clk_add(c);
525  }
526 }
527 
528 static const char *mux_cclk[] = {
529  "clk_m",
530  "pll_c",
531  "clk_32k",
532  "pll_m",
533  "pll_p",
534  "pll_p_out4",
535  "pll_p_out3",
536  "clk_d",
537  "pll_x",
538 };
539 
540 
541 static struct clk *mux_cclk_p[] = {
542  &tegra_clk_m,
543  &tegra_pll_c,
544  &tegra_clk_32k,
545  &tegra_pll_m,
546  &tegra_pll_p,
547  &tegra_pll_p_out4,
548  &tegra_pll_p_out3,
549  &tegra_clk_d,
550  &tegra_pll_x,
551 };
552 
553 static const char *mux_sclk[] = {
554  "clk_m",
555  "pll_c_out1",
556  "pll_p_out4",
557  "pllp_p_out3",
558  "pll_p_out2",
559  "clk_d",
560  "clk_32k",
561  "pll_m_out1",
562 };
563 
564 static struct clk *mux_sclk_p[] = {
565  &tegra_clk_m,
566  &tegra_pll_c_out1,
567  &tegra_pll_p_out4,
568  &tegra_pll_p_out3,
569  &tegra_pll_p_out2,
570  &tegra_clk_d,
571  &tegra_clk_32k,
572  &tegra_pll_m_out1,
573 };
574 
575 static struct clk tegra_cclk;
576 static struct clk_tegra tegra_cclk_hw = {
577  .hw = {
578  .clk = &tegra_cclk,
579  },
580  .reg = 0x20,
581  .max_rate = 1000000000,
582 };
583 DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
584  mux_cclk_p, NULL);
585 
586 static const char *mux_twd[] = {
587  "cclk",
588 };
589 
590 static struct clk *mux_twd_p[] = {
591  &tegra_cclk,
592 };
593 
594 static struct clk tegra_clk_twd;
595 static struct clk_tegra tegra_clk_twd_hw = {
596  .hw = {
597  .clk = &tegra_clk_twd,
598  },
599  .max_rate = 1000000000,
600  .mul = 1,
601  .div = 4,
602 };
603 
604 static struct clk tegra_clk_twd = {
605  .name = "twd",
606  .ops = &tegra_twd_ops,
607  .hw = &tegra_clk_twd_hw.hw,
608  .parent = &tegra_cclk,
609  .parent_names = mux_twd,
610  .parents = mux_twd_p,
611  .num_parents = ARRAY_SIZE(mux_twd),
612 };
613 
614 static struct clk tegra_sclk;
615 static struct clk_tegra tegra_sclk_hw = {
616  .hw = {
617  .clk = &tegra_sclk,
618  },
619  .reg = 0x28,
620  .max_rate = 240000000,
621  .min_rate = 120000000,
622 };
623 DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
624  mux_sclk_p, NULL);
625 
626 static const char *tegra_cop_parent_names[] = {
627  "tegra_sclk",
628 };
629 
630 static struct clk *tegra_cop_parents[] = {
631  &tegra_sclk,
632 };
633 
634 static struct clk tegra_cop;
635 static struct clk_tegra tegra_cop_hw = {
636  .hw = {
637  .clk = &tegra_cop,
638  },
639  .max_rate = 240000000,
640  .reset = &tegra2_cop_clk_reset,
641 };
642 DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
643  tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
644 
645 static const char *tegra_hclk_parent_names[] = {
646  "tegra_sclk",
647 };
648 
649 static struct clk *tegra_hclk_parents[] = {
650  &tegra_sclk,
651 };
652 
653 static struct clk tegra_hclk;
654 static struct clk_tegra tegra_hclk_hw = {
655  .hw = {
656  .clk = &tegra_hclk,
657  },
658  .flags = DIV_BUS,
659  .reg = 0x30,
660  .reg_shift = 4,
661  .max_rate = 240000000,
662 };
663 DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
664  tegra_hclk_parents, &tegra_sclk);
665 
666 static const char *tegra_pclk_parent_names[] = {
667  "tegra_hclk",
668 };
669 
670 static struct clk *tegra_pclk_parents[] = {
671  &tegra_hclk,
672 };
673 
674 static struct clk tegra_pclk;
675 static struct clk_tegra tegra_pclk_hw = {
676  .hw = {
677  .clk = &tegra_pclk,
678  },
679  .flags = DIV_BUS,
680  .reg = 0x30,
681  .reg_shift = 0,
682  .max_rate = 120000000,
683 };
684 DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
685  tegra_pclk_parents, &tegra_hclk);
686 
687 static const char *tegra_blink_parent_names[] = {
688  "clk_32k",
689 };
690 
691 static struct clk *tegra_blink_parents[] = {
692  &tegra_clk_32k,
693 };
694 
695 static struct clk tegra_blink;
696 static struct clk_tegra tegra_blink_hw = {
697  .hw = {
698  .clk = &tegra_blink,
699  },
700  .reg = 0x40,
701  .max_rate = 32768,
702 };
703 DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
704  tegra_blink_parents, &tegra_clk_32k);
705 
706 static const char *mux_pllm_pllc_pllp_plla[] = {
707  "pll_m",
708  "pll_c",
709  "pll_p",
710  "pll_a_out0",
711 };
712 
713 static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
714  &tegra_pll_m,
715  &tegra_pll_c,
716  &tegra_pll_p,
717  &tegra_pll_a_out0,
718 };
719 
720 static const char *mux_pllm_pllc_pllp_clkm[] = {
721  "pll_m",
722  "pll_c",
723  "pll_p",
724  "clk_m",
725 };
726 
727 static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
728  &tegra_pll_m,
729  &tegra_pll_c,
730  &tegra_pll_p,
731  &tegra_clk_m,
732 };
733 
734 static const char *mux_pllp_pllc_pllm_clkm[] = {
735  "pll_p",
736  "pll_c",
737  "pll_m",
738  "clk_m",
739 };
740 
741 static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
742  &tegra_pll_p,
743  &tegra_pll_c,
744  &tegra_pll_m,
745  &tegra_clk_m,
746 };
747 
748 static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
749  "pll_a_out0",
750  "audio_2x",
751  "pll_p",
752  "clk_m",
753 };
754 
755 static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
756  &tegra_pll_a_out0,
757  &tegra_audio_2x,
758  &tegra_pll_p,
759  &tegra_clk_m,
760 };
761 
762 static const char *mux_pllp_plld_pllc_clkm[] = {
763  "pllp",
764  "pll_d_out0",
765  "pll_c",
766  "clk_m",
767 };
768 
769 static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
770  &tegra_pll_p,
771  &tegra_pll_d_out0,
772  &tegra_pll_c,
773  &tegra_clk_m,
774 };
775 
776 static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
777  "pll_p",
778  "pll_c",
779  "audio",
780  "clk_m",
781  "clk_32k",
782 };
783 
784 static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
785  &tegra_pll_p,
786  &tegra_pll_c,
787  &tegra_audio,
788  &tegra_clk_m,
789  &tegra_clk_32k,
790 };
791 
792 static const char *mux_pllp_pllc_pllm[] = {
793  "pll_p",
794  "pll_c",
795  "pll_m"
796 };
797 
798 static struct clk *mux_pllp_pllc_pllm_p[] = {
799  &tegra_pll_p,
800  &tegra_pll_c,
801  &tegra_pll_m,
802 };
803 
804 static const char *mux_clk_m[] = {
805  "clk_m",
806 };
807 
808 static struct clk *mux_clk_m_p[] = {
809  &tegra_clk_m,
810 };
811 
812 static const char *mux_pllp_out3[] = {
813  "pll_p_out3",
814 };
815 
816 static struct clk *mux_pllp_out3_p[] = {
817  &tegra_pll_p_out3,
818 };
819 
820 static const char *mux_plld[] = {
821  "pll_d",
822 };
823 
824 static struct clk *mux_plld_p[] = {
825  &tegra_pll_d,
826 };
827 
828 static const char *mux_clk_32k[] = {
829  "clk_32k",
830 };
831 
832 static struct clk *mux_clk_32k_p[] = {
833  &tegra_clk_32k,
834 };
835 
836 static const char *mux_pclk[] = {
837  "pclk",
838 };
839 
840 static struct clk *mux_pclk_p[] = {
841  &tegra_pclk,
842 };
843 
844 static struct clk tegra_emc;
845 static struct clk_tegra tegra_emc_hw = {
846  .hw = {
847  .clk = &tegra_emc,
848  },
849  .reg = 0x19c,
850  .max_rate = 800000000,
851  .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
852  .reset = &tegra2_periph_clk_reset,
853  .u.periph = {
854  .clk_num = 57,
855  },
856 };
857 DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
858  mux_pllm_pllc_pllp_clkm_p, NULL);
859 
860 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
861  _max, _inputs, _flags) \
862  static struct clk tegra_##_name; \
863  static struct clk_tegra tegra_##_name##_hw = { \
864  .hw = { \
865  .clk = &tegra_##_name, \
866  }, \
867  .lookup = { \
868  .dev_id = _dev, \
869  .con_id = _con, \
870  }, \
871  .reg = _reg, \
872  .flags = _flags, \
873  .max_rate = _max, \
874  .u.periph = { \
875  .clk_num = _clk_num, \
876  }, \
877  .reset = tegra2_periph_clk_reset, \
878  }; \
879  static struct clk tegra_##_name = { \
880  .name = #_name, \
881  .ops = &tegra_periph_clk_ops, \
882  .hw = &tegra_##_name##_hw.hw, \
883  .parent_names = _inputs, \
884  .parents = _inputs##_p, \
885  .num_parents = ARRAY_SIZE(_inputs), \
886  };
887 
888 PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
889 PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
890 PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
891 PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
892 PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
893 PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
894 PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
895 PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
896 PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
897 PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
898 PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
899 PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900 PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901 PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902 PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
903 PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
904 PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
905 PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
906 PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
907 PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908 PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
909 PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
910 PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
911 PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
912 PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
913 PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
914 PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
915 /* FIXME: what is la? */
916 PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
917 PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
918 PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
919 PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
920 PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
921 PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
922 PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
923 PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924 PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
925 PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
926 PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
927 PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
928 PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
929 PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
930 PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
931 PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
932 PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
933 PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
934 PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
935 PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
936 PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
937 PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
938 PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
939 PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
940 PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
941 PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
942 PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
943 PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
944 PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
945 PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
946 PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
947 PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
948 PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
949 PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
950 PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
951 PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
952 
953 static struct clk *tegra_list_clks[] = {
954  &tegra_apbdma,
955  &tegra_rtc,
956  &tegra_timer,
957  &tegra_i2s1,
958  &tegra_i2s2,
959  &tegra_spdif_out,
960  &tegra_spdif_in,
961  &tegra_pwm,
962  &tegra_spi,
963  &tegra_xio,
964  &tegra_twc,
965  &tegra_sbc1,
966  &tegra_sbc2,
967  &tegra_sbc3,
968  &tegra_sbc4,
969  &tegra_ide,
970  &tegra_ndflash,
971  &tegra_vfir,
972  &tegra_sdmmc1,
973  &tegra_sdmmc2,
974  &tegra_sdmmc3,
975  &tegra_sdmmc4,
976  &tegra_vcp,
977  &tegra_bsea,
978  &tegra_bsev,
979  &tegra_vde,
980  &tegra_csite,
981  &tegra_la,
982  &tegra_owr,
983  &tegra_nor,
984  &tegra_mipi,
985  &tegra_i2c1,
986  &tegra_i2c2,
987  &tegra_i2c3,
988  &tegra_dvc,
989  &tegra_uarta,
990  &tegra_uartb,
991  &tegra_uartc,
992  &tegra_uartd,
993  &tegra_uarte,
994  &tegra_3d,
995  &tegra_2d,
996  &tegra_vi,
997  &tegra_vi_sensor,
998  &tegra_epp,
999  &tegra_mpe,
1000  &tegra_host1x,
1001  &tegra_cve,
1002  &tegra_tvo,
1003  &tegra_hdmi,
1004  &tegra_tvdac,
1005  &tegra_disp1,
1006  &tegra_disp2,
1007  &tegra_usbd,
1008  &tegra_usb2,
1009  &tegra_usb3,
1010  &tegra_dsi,
1011  &tegra_csi,
1012  &tegra_isp,
1013  &tegra_csus,
1014  &tegra_pex,
1015  &tegra_afi,
1016  &tegra_pcie_xclk,
1017 };
1018 
1019 #define CLK_DUPLICATE(_name, _dev, _con) \
1020  { \
1021  .name = _name, \
1022  .lookup = { \
1023  .dev_id = _dev, \
1024  .con_id = _con, \
1025  }, \
1026  }
1027 
1028 /* Some clocks may be used by different drivers depending on the board
1029  * configuration. List those here to register them twice in the clock lookup
1030  * table under two names.
1031  */
1032 static struct clk_duplicate tegra_clk_duplicates[] = {
1033  CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1034  CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1035  CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1036  CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1037  CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1038  CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1039  CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1040  CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1041  CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1042  CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1043  CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
1044  CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1045  CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1046  CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1047  CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1048  CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1049  CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1050  CLK_DUPLICATE("cclk", NULL, "cpu"),
1051  CLK_DUPLICATE("twd", "smp_twd", NULL),
1052  CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1053  CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1054  CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1055  CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1056 };
1057 
1058 #define CLK(dev, con, ck) \
1059  { \
1060  .dev_id = dev, \
1061  .con_id = con, \
1062  .clk = ck, \
1063  }
1064 
1065 static struct clk *tegra_ptr_clks[] = {
1066  &tegra_clk_32k,
1067  &tegra_pll_s,
1068  &tegra_clk_m,
1069  &tegra_pll_m,
1070  &tegra_pll_m_out1,
1071  &tegra_pll_c,
1072  &tegra_pll_c_out1,
1073  &tegra_pll_p,
1074  &tegra_pll_p_out1,
1075  &tegra_pll_p_out2,
1076  &tegra_pll_p_out3,
1077  &tegra_pll_p_out4,
1078  &tegra_pll_a,
1079  &tegra_pll_a_out0,
1080  &tegra_pll_d,
1081  &tegra_pll_d_out0,
1082  &tegra_pll_u,
1083  &tegra_pll_x,
1084  &tegra_pll_e,
1085  &tegra_cclk,
1086  &tegra_clk_twd,
1087  &tegra_sclk,
1088  &tegra_hclk,
1089  &tegra_pclk,
1090  &tegra_clk_d,
1091  &tegra_cdev1,
1092  &tegra_cdev2,
1093  &tegra_blink,
1094  &tegra_cop,
1095  &tegra_emc,
1096 };
1097 
1098 static void tegra2_init_one_clock(struct clk *c)
1099 {
1100  struct clk_tegra *clk = to_clk_tegra(c->hw);
1101  int ret;
1102 
1103  ret = __clk_init(NULL, c);
1104  if (ret)
1105  pr_err("clk init failed %s\n", __clk_get_name(c));
1106 
1107  INIT_LIST_HEAD(&clk->shared_bus_list);
1108  if (!clk->lookup.dev_id && !clk->lookup.con_id)
1109  clk->lookup.con_id = c->name;
1110  clk->lookup.clk = c;
1111  clkdev_add(&clk->lookup);
1112  tegra_clk_add(c);
1113 }
1114 
1115 void __init tegra2_init_clocks(void)
1116 {
1117  int i;
1118  struct clk *c;
1119 
1120  for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1121  tegra2_init_one_clock(tegra_ptr_clks[i]);
1122 
1123  for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1124  tegra2_init_one_clock(tegra_list_clks[i]);
1125 
1126  for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1127  c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1128  if (!c) {
1129  pr_err("%s: Unknown duplicate clock %s\n", __func__,
1130  tegra_clk_duplicates[i].name);
1131  continue;
1132  }
1133 
1134  tegra_clk_duplicates[i].lookup.clk = c;
1135  clkdev_add(&tegra_clk_duplicates[i].lookup);
1136  }
1137 
1138  init_audio_sync_clock_mux();
1139  tegra20_cpu_car_ops_init();
1140 }
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