#include <mach-common/irq.h>

Macros
#define	NR_PERI_INTS (2 * 32)

#define	IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */

#define	IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */

#define	IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */

#define	IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */

#define	IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */

#define	IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */

#define	IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */

#define	IRQ_RTC BFIN_IRQ(7) /* RTC */

#define	IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */

#define	IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */

#define	IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */

#define	IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */

#define	IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */

#define	IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */

#define	IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */

#define	IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */

#define	IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */

#define	IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */

#define	IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */

#define	IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */

#define	IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */

#define	IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */

#define	IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */

#define	IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */

#define	IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */

#define	IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */

#define	IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */

#define	IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */

#define	IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */

#define	IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */

#define	IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */

#define	IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */

#define	IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */

#define	IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */

#define	IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */

#define	IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */

#define	IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */

#define	IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */

#define	IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */

#define	IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */

#define	IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */

#define	IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */

#define	IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */

#define	IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */

#define	IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */

#define	IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */

#define	IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */

#define	IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */

#define	SYS_IRQS BFIN_IRQ(63) /* 70 */

#define	IRQ_PF0 71

#define	IRQ_PF1 72

#define	IRQ_PF2 73

#define	IRQ_PF3 74

#define	IRQ_PF4 75

#define	IRQ_PF5 76

#define	IRQ_PF6 77

#define	IRQ_PF7 78

#define	IRQ_PF8 79

#define	IRQ_PF9 80

#define	IRQ_PF10 81

#define	IRQ_PF11 82

#define	IRQ_PF12 83

#define	IRQ_PF13 84

#define	IRQ_PF14 85

#define	IRQ_PF15 86

#define	GPIO_IRQ_BASE IRQ_PF0

#define	NR_MACH_IRQS (IRQ_PF15 + 1)

#define	IRQ_PLL_WAKEUP_POS 0

#define	IRQ_DMA0_ERROR_POS 4

#define	IRQ_PPI_ERROR_POS 8

#define	IRQ_SPORT0_ERROR_POS 12

#define	IRQ_SPORT1_ERROR_POS 16

#define	IRQ_SPI0_ERROR_POS 20

#define	IRQ_UART0_ERROR_POS 24

#define	IRQ_RTC_POS 28

#define	IRQ_PPI_POS 0

#define	IRQ_SPORT0_RX_POS 4

#define	IRQ_SPORT0_TX_POS 8

#define	IRQ_SPORT1_RX_POS 12

#define	IRQ_SPORT1_TX_POS 16

#define	IRQ_SPI0_POS 20

#define	IRQ_UART0_RX_POS 24

#define	IRQ_UART0_TX_POS 28

#define	IRQ_TIMER0_POS 0

#define	IRQ_TIMER1_POS 4

#define	IRQ_TIMER2_POS 8

#define	IRQ_PORTF_INTA_POS 12

#define	IRQ_PORTF_INTB_POS 16

#define	IRQ_MEM0_DMA0_POS 20

#define	IRQ_MEM0_DMA1_POS 24

#define	IRQ_WATCH_POS 28

#define	IRQ_DMA1_ERROR_POS 0

#define	IRQ_SPORT2_ERROR_POS 4

#define	IRQ_SPORT3_ERROR_POS 8

#define	IRQ_SPI1_ERROR_POS 16

#define	IRQ_SPI2_ERROR_POS 20

#define	IRQ_UART1_ERROR_POS 24

#define	IRQ_UART2_ERROR_POS 28

#define	IRQ_CAN_ERROR_POS 0

#define	IRQ_SPORT2_RX_POS 4

#define	IRQ_SPORT2_TX_POS 8

#define	IRQ_SPORT3_RX_POS 12

#define	IRQ_SPORT3_TX_POS 16

#define	IRQ_SPI1_POS 28

#define	IRQ_SPI2_POS 0

#define	IRQ_UART1_RX_POS 4

#define	IRQ_UART1_TX_POS 8

#define	IRQ_UART2_RX_POS 12

#define	IRQ_UART2_TX_POS 16

#define	IRQ_TWI0_POS 20

#define	IRQ_TWI1_POS 24

#define	IRQ_CAN_RX_POS 28

#define	IRQ_CAN_TX_POS 0

#define	IRQ_MEM1_DMA0_POS 4

#define	IRQ_MEM1_DMA1_POS 8

Macro Definition Documentation

#define GPIO_IRQ_BASE IRQ_PF0

Definition at line 82 of file irq.h.

#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */

Definition at line 45 of file irq.h.

#define IRQ_CAN_ERROR_POS 0

Definition at line 126 of file irq.h.

#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */

Definition at line 58 of file irq.h.

#define IRQ_CAN_RX_POS 28

Definition at line 141 of file irq.h.

#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */

Definition at line 59 of file irq.h.

#define IRQ_CAN_TX_POS 0

Definition at line 144 of file irq.h.

#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */

Definition at line 15 of file irq.h.

#define IRQ_DMA0_ERROR_POS 4

Definition at line 88 of file irq.h.

#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */

Definition at line 38 of file irq.h.

#define IRQ_DMA1_ERROR_POS 0

Definition at line 117 of file irq.h.

#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */

Definition at line 35 of file irq.h.

#define IRQ_MEM0_DMA0_POS 20

Definition at line 112 of file irq.h.

#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */

Definition at line 36 of file irq.h.

#define IRQ_MEM0_DMA1_POS 24

Definition at line 113 of file irq.h.

#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */

Definition at line 60 of file irq.h.

#define IRQ_MEM1_DMA0_POS 4

Definition at line 145 of file irq.h.

#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */

Definition at line 61 of file irq.h.

#define IRQ_MEM1_DMA1_POS 8

Definition at line 146 of file irq.h.

#define IRQ_PF0 71

Definition at line 65 of file irq.h.

#define IRQ_PF1 72

Definition at line 66 of file irq.h.

#define IRQ_PF10 81

Definition at line 75 of file irq.h.

#define IRQ_PF11 82

Definition at line 76 of file irq.h.

#define IRQ_PF12 83

Definition at line 77 of file irq.h.

#define IRQ_PF13 84

Definition at line 78 of file irq.h.

#define IRQ_PF14 85

Definition at line 79 of file irq.h.

#define IRQ_PF15 86

Definition at line 80 of file irq.h.

#define IRQ_PF2 73

Definition at line 67 of file irq.h.

#define IRQ_PF3 74

Definition at line 68 of file irq.h.

#define IRQ_PF4 75

Definition at line 69 of file irq.h.

#define IRQ_PF5 76

Definition at line 70 of file irq.h.

#define IRQ_PF6 77

Definition at line 71 of file irq.h.

#define IRQ_PF7 78

Definition at line 72 of file irq.h.

#define IRQ_PF8 79

Definition at line 73 of file irq.h.

#define IRQ_PF9 80

Definition at line 74 of file irq.h.

#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */

Definition at line 14 of file irq.h.

#define IRQ_PLL_WAKEUP_POS 0

Definition at line 87 of file irq.h.

#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */

Definition at line 33 of file irq.h.

#define IRQ_PORTF_INTA_POS 12

Definition at line 110 of file irq.h.

#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */

Definition at line 34 of file irq.h.

#define IRQ_PORTF_INTB_POS 16

Definition at line 111 of file irq.h.

#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */

Definition at line 22 of file irq.h.

#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */

Definition at line 16 of file irq.h.

#define IRQ_PPI_ERROR_POS 8

Definition at line 89 of file irq.h.

#define IRQ_PPI_POS 0

Definition at line 97 of file irq.h.

#define IRQ_RTC BFIN_IRQ(7) /* RTC */

Definition at line 21 of file irq.h.

#define IRQ_RTC_POS 28

Definition at line 94 of file irq.h.

#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */

Definition at line 27 of file irq.h.

#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */

Definition at line 19 of file irq.h.

#define IRQ_SPI0_ERROR_POS 20

Definition at line 92 of file irq.h.

#define IRQ_SPI0_POS 20

Definition at line 102 of file irq.h.

#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */

Definition at line 50 of file irq.h.

#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */

Definition at line 41 of file irq.h.

#define IRQ_SPI1_ERROR_POS 16

Definition at line 120 of file irq.h.

#define IRQ_SPI1_POS 28

Definition at line 131 of file irq.h.

#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */

Definition at line 51 of file irq.h.

#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */

Definition at line 42 of file irq.h.

#define IRQ_SPI2_ERROR_POS 20

Definition at line 121 of file irq.h.

#define IRQ_SPI2_POS 0

Definition at line 134 of file irq.h.

#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */

Definition at line 17 of file irq.h.

#define IRQ_SPORT0_ERROR_POS 12

Definition at line 90 of file irq.h.

#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */

Definition at line 23 of file irq.h.

#define IRQ_SPORT0_RX_POS 4

Definition at line 98 of file irq.h.

#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */

Definition at line 24 of file irq.h.

#define IRQ_SPORT0_TX_POS 8

Definition at line 99 of file irq.h.

#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */

Definition at line 18 of file irq.h.

#define IRQ_SPORT1_ERROR_POS 16

Definition at line 91 of file irq.h.

#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */

Definition at line 25 of file irq.h.

#define IRQ_SPORT1_RX_POS 12

Definition at line 100 of file irq.h.

#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */

Definition at line 26 of file irq.h.

#define IRQ_SPORT1_TX_POS 16

Definition at line 101 of file irq.h.

#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */

Definition at line 39 of file irq.h.

#define IRQ_SPORT2_ERROR_POS 4

Definition at line 118 of file irq.h.

#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */

Definition at line 46 of file irq.h.

#define IRQ_SPORT2_RX_POS 4

Definition at line 127 of file irq.h.

#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */

Definition at line 47 of file irq.h.

#define IRQ_SPORT2_TX_POS 8

Definition at line 128 of file irq.h.

#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */

Definition at line 40 of file irq.h.

#define IRQ_SPORT3_ERROR_POS 8

Definition at line 119 of file irq.h.

#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */

Definition at line 48 of file irq.h.

#define IRQ_SPORT3_RX_POS 12

Definition at line 129 of file irq.h.

#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */

Definition at line 49 of file irq.h.

#define IRQ_SPORT3_TX_POS 16

Definition at line 130 of file irq.h.

#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */

Definition at line 30 of file irq.h.

#define IRQ_TIMER0_POS 0

Definition at line 107 of file irq.h.

#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */

Definition at line 31 of file irq.h.

#define IRQ_TIMER1_POS 4

Definition at line 108 of file irq.h.

#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */

Definition at line 32 of file irq.h.

#define IRQ_TIMER2_POS 8

Definition at line 109 of file irq.h.

#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */

Definition at line 56 of file irq.h.

#define IRQ_TWI0_POS 20

Definition at line 139 of file irq.h.

#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */

Definition at line 57 of file irq.h.

#define IRQ_TWI1_POS 24

Definition at line 140 of file irq.h.

#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */

Definition at line 20 of file irq.h.

#define IRQ_UART0_ERROR_POS 24

Definition at line 93 of file irq.h.

#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */

Definition at line 28 of file irq.h.

#define IRQ_UART0_RX_POS 24

Definition at line 103 of file irq.h.

#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */

Definition at line 29 of file irq.h.

#define IRQ_UART0_TX_POS 28

Definition at line 104 of file irq.h.

#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */

Definition at line 43 of file irq.h.

#define IRQ_UART1_ERROR_POS 24

Definition at line 122 of file irq.h.

#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */

Definition at line 52 of file irq.h.

#define IRQ_UART1_RX_POS 4

Definition at line 135 of file irq.h.

#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */

Definition at line 53 of file irq.h.

#define IRQ_UART1_TX_POS 8

Definition at line 136 of file irq.h.

#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */

Definition at line 44 of file irq.h.

#define IRQ_UART2_ERROR_POS 28

Definition at line 123 of file irq.h.

#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */

Definition at line 54 of file irq.h.

#define IRQ_UART2_RX_POS 12

Definition at line 137 of file irq.h.

#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */

Definition at line 55 of file irq.h.

#define IRQ_UART2_TX_POS 16

Definition at line 138 of file irq.h.

#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */

Definition at line 37 of file irq.h.

#define IRQ_WATCH_POS 28

Definition at line 114 of file irq.h.

#define NR_MACH_IRQS (IRQ_PF15 + 1)

Definition at line 84 of file irq.h.

#define NR_PERI_INTS (2 * 32)

Definition at line 12 of file irq.h.

#define SYS_IRQS BFIN_IRQ(63) /* 70 */

Definition at line 63 of file irq.h.

Macros

Macro Definition Documentation