#include <mach-common/irq.h>
#include <linux/types.h>

Data Structures
struct	bfin_pint_regs

Macros
#define	BFIN_IRQ(x) ((x) + IVG15)

#define	NR_PERI_INTS (5 * 32)

#define	IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */

#define	IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */

#define	IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */

#define	IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */

#define	IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */

#define	IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */

#define	IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */

#define	IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */

#define	IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */

#define	IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */

#define	IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */

#define	IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */

#define	CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)

#define	IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */

#define	IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */

#define	IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */

#define	IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */

#define	IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */

#define	IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */

#define	IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */

#define	IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */

#define	IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */

#define	IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */

#define	IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */

#define	IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */

#define	IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */

#define	IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */

#define	IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */

#define	IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */

#define	IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */

#define	IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */

#define	IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */

#define	IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */

#define	IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */

#define	IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */

#define	IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */

#define	IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */

#define	IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */

#define	IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */

#define	IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */

#define	IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */

#define	IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */

#define	IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */

#define	IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */

#define	IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */

#define	IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */

#define	IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */

#define	IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */

#define	IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */

#define	IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */

#define	IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */

#define	IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */

#define	IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */

#define	IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */

#define	IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */

#define	IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */

#define	IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */

#define	IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */

#define	IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */

#define	IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */

#define	IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */

#define	IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */

#define	IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */

#define	IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */

#define	IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */

#define	IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */

#define	IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */

#define	IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */

#define	IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */

#define	IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */

#define	IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */

#define	IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */

#define	IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */

#define	IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */

#define	IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */

#define	IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */

#define	IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */

#define	IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */

#define	IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */

#define	IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */

#define	IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */

#define	IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */

#define	IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */

#define	IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */

#define	IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0

#define	IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */

#define	IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */

#define	IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */

#define	IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */

#define	IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1

#define	IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */

#define	IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */

#define	IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */

#define	IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */

#define	IRQ_MDMAS2 IRQ_MDMA2_DEST

#define	IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */

#define	IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */

#define	IRQ_MDMAS3 IRQ_MDMA3_DEST

#define	IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */

#define	IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */

#define	IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */

#define	IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */

#define	IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */

#define	IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */

#define	IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */

#define	IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */

#define	IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */

#define	IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */

#define	IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */

#define	IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */

#define	IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */

#define	IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */

#define	IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */

#define	IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */

#define	IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */

#define	IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */

#define	IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */

#define	IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */

#define	IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */

#define	IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */

#define	IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */

#define	IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */

#define	IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */

#define	IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */

#define	IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */

#define	IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */

#define	IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */

#define	IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */

#define	IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */

#define	IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */

#define	IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */

#define	IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */

#define	IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */

#define	IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */

#define	IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */

#define	IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */

#define	IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */

#define	IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */

#define	SYS_IRQS IRQ_SWU6

#define	BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)

#define	IRQ_PA0 BFIN_PA_IRQ(0)

#define	IRQ_PA1 BFIN_PA_IRQ(1)

#define	IRQ_PA2 BFIN_PA_IRQ(2)

#define	IRQ_PA3 BFIN_PA_IRQ(3)

#define	IRQ_PA4 BFIN_PA_IRQ(4)

#define	IRQ_PA5 BFIN_PA_IRQ(5)

#define	IRQ_PA6 BFIN_PA_IRQ(6)

#define	IRQ_PA7 BFIN_PA_IRQ(7)

#define	IRQ_PA8 BFIN_PA_IRQ(8)

#define	IRQ_PA9 BFIN_PA_IRQ(9)

#define	IRQ_PA10 BFIN_PA_IRQ(10)

#define	IRQ_PA11 BFIN_PA_IRQ(11)

#define	IRQ_PA12 BFIN_PA_IRQ(12)

#define	IRQ_PA13 BFIN_PA_IRQ(13)

#define	IRQ_PA14 BFIN_PA_IRQ(14)

#define	IRQ_PA15 BFIN_PA_IRQ(15)

#define	BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)

#define	IRQ_PB0 BFIN_PB_IRQ(0)

#define	IRQ_PB1 BFIN_PB_IRQ(1)

#define	IRQ_PB2 BFIN_PB_IRQ(2)

#define	IRQ_PB3 BFIN_PB_IRQ(3)

#define	IRQ_PB4 BFIN_PB_IRQ(4)

#define	IRQ_PB5 BFIN_PB_IRQ(5)

#define	IRQ_PB6 BFIN_PB_IRQ(6)

#define	IRQ_PB7 BFIN_PB_IRQ(7)

#define	IRQ_PB8 BFIN_PB_IRQ(8)

#define	IRQ_PB9 BFIN_PB_IRQ(9)

#define	IRQ_PB10 BFIN_PB_IRQ(10)

#define	IRQ_PB11 BFIN_PB_IRQ(11)

#define	IRQ_PB12 BFIN_PB_IRQ(12)

#define	IRQ_PB13 BFIN_PB_IRQ(13)

#define	IRQ_PB14 BFIN_PB_IRQ(14)

#define	IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */

#define	BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)

#define	IRQ_PC0 BFIN_PC_IRQ(0)

#define	IRQ_PC1 BFIN_PC_IRQ(1)

#define	IRQ_PC2 BFIN_PC_IRQ(2)

#define	IRQ_PC3 BFIN_PC_IRQ(3)

#define	IRQ_PC4 BFIN_PC_IRQ(4)

#define	IRQ_PC5 BFIN_PC_IRQ(5)

#define	IRQ_PC6 BFIN_PC_IRQ(6)

#define	IRQ_PC7 BFIN_PC_IRQ(7)

#define	IRQ_PC8 BFIN_PC_IRQ(8)

#define	IRQ_PC9 BFIN_PC_IRQ(9)

#define	IRQ_PC10 BFIN_PC_IRQ(10)

#define	IRQ_PC11 BFIN_PC_IRQ(11)

#define	IRQ_PC12 BFIN_PC_IRQ(12)

#define	IRQ_PC13 BFIN_PC_IRQ(13)

#define	IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */

#define	IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */

#define	BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)

#define	IRQ_PD0 BFIN_PD_IRQ(0)

#define	IRQ_PD1 BFIN_PD_IRQ(1)

#define	IRQ_PD2 BFIN_PD_IRQ(2)

#define	IRQ_PD3 BFIN_PD_IRQ(3)

#define	IRQ_PD4 BFIN_PD_IRQ(4)

#define	IRQ_PD5 BFIN_PD_IRQ(5)

#define	IRQ_PD6 BFIN_PD_IRQ(6)

#define	IRQ_PD7 BFIN_PD_IRQ(7)

#define	IRQ_PD8 BFIN_PD_IRQ(8)

#define	IRQ_PD9 BFIN_PD_IRQ(9)

#define	IRQ_PD10 BFIN_PD_IRQ(10)

#define	IRQ_PD11 BFIN_PD_IRQ(11)

#define	IRQ_PD12 BFIN_PD_IRQ(12)

#define	IRQ_PD13 BFIN_PD_IRQ(13)

#define	IRQ_PD14 BFIN_PD_IRQ(14)

#define	IRQ_PD15 BFIN_PD_IRQ(15)

#define	BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)

#define	IRQ_PE0 BFIN_PE_IRQ(0)

#define	IRQ_PE1 BFIN_PE_IRQ(1)

#define	IRQ_PE2 BFIN_PE_IRQ(2)

#define	IRQ_PE3 BFIN_PE_IRQ(3)

#define	IRQ_PE4 BFIN_PE_IRQ(4)

#define	IRQ_PE5 BFIN_PE_IRQ(5)

#define	IRQ_PE6 BFIN_PE_IRQ(6)

#define	IRQ_PE7 BFIN_PE_IRQ(7)

#define	IRQ_PE8 BFIN_PE_IRQ(8)

#define	IRQ_PE9 BFIN_PE_IRQ(9)

#define	IRQ_PE10 BFIN_PE_IRQ(10)

#define	IRQ_PE11 BFIN_PE_IRQ(11)

#define	IRQ_PE12 BFIN_PE_IRQ(12)

#define	IRQ_PE13 BFIN_PE_IRQ(13)

#define	IRQ_PE14 BFIN_PE_IRQ(14)

#define	IRQ_PE15 BFIN_PE_IRQ(15)

#define	BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)

#define	IRQ_PF0 BFIN_PF_IRQ(0)

#define	IRQ_PF1 BFIN_PF_IRQ(1)

#define	IRQ_PF2 BFIN_PF_IRQ(2)

#define	IRQ_PF3 BFIN_PF_IRQ(3)

#define	IRQ_PF4 BFIN_PF_IRQ(4)

#define	IRQ_PF5 BFIN_PF_IRQ(5)

#define	IRQ_PF6 BFIN_PF_IRQ(6)

#define	IRQ_PF7 BFIN_PF_IRQ(7)

#define	IRQ_PF8 BFIN_PF_IRQ(8)

#define	IRQ_PF9 BFIN_PF_IRQ(9)

#define	IRQ_PF10 BFIN_PF_IRQ(10)

#define	IRQ_PF11 BFIN_PF_IRQ(11)

#define	IRQ_PF12 BFIN_PF_IRQ(12)

#define	IRQ_PF13 BFIN_PF_IRQ(13)

#define	IRQ_PF14 BFIN_PF_IRQ(14)

#define	IRQ_PF15 BFIN_PF_IRQ(15)

#define	BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)

#define	IRQ_PG0 BFIN_PG_IRQ(0)

#define	IRQ_PG1 BFIN_PG_IRQ(1)

#define	IRQ_PG2 BFIN_PG_IRQ(2)

#define	IRQ_PG3 BFIN_PG_IRQ(3)

#define	IRQ_PG4 BFIN_PG_IRQ(4)

#define	IRQ_PG5 BFIN_PG_IRQ(5)

#define	IRQ_PG6 BFIN_PG_IRQ(6)

#define	IRQ_PG7 BFIN_PG_IRQ(7)

#define	IRQ_PG8 BFIN_PG_IRQ(8)

#define	IRQ_PG9 BFIN_PG_IRQ(9)

#define	IRQ_PG10 BFIN_PG_IRQ(10)

#define	IRQ_PG11 BFIN_PG_IRQ(11)

#define	IRQ_PG12 BFIN_PG_IRQ(12)

#define	IRQ_PG13 BFIN_PG_IRQ(13)

#define	IRQ_PG14 BFIN_PG_IRQ(14)

#define	IRQ_PG15 BFIN_PG_IRQ(15)

#define	GPIO_IRQ_BASE IRQ_PA0

#define	NR_MACH_IRQS (IRQ_PG15 + 1)

#define	SEC_SCTL_PRIO_OFFSET 8

Variables
u8	sec_int_priority []

Macro Definition Documentation

#define BFIN_IRQ ( x ) ((x) + IVG15)

Definition at line 13 of file irq.h.

#define BFIN_PA_IRQ ( x ) ((x) + SYS_IRQS + 1)

Definition at line 166 of file irq.h.

#define BFIN_PB_IRQ ( x ) ((x) + IRQ_PA15 + 1)

Definition at line 184 of file irq.h.

#define BFIN_PC_IRQ ( x ) ((x) + IRQ_PB15 + 1)

Definition at line 202 of file irq.h.

#define BFIN_PD_IRQ ( x ) ((x) + IRQ_PC15 + 1)

Definition at line 220 of file irq.h.

#define BFIN_PE_IRQ ( x ) ((x) + IRQ_PD15 + 1)

Definition at line 238 of file irq.h.

#define BFIN_PF_IRQ ( x ) ((x) + IRQ_PE15 + 1)

Definition at line 256 of file irq.h.

#define BFIN_PG_IRQ ( x ) ((x) + IRQ_PF15 + 1)

Definition at line 274 of file irq.h.

#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)

Definition at line 29 of file irq.h.

#define GPIO_IRQ_BASE IRQ_PA0

Definition at line 292 of file irq.h.

#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */

Definition at line 58 of file irq.h.

#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */

Definition at line 57 of file irq.h.

#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */

Definition at line 23 of file irq.h.

#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */

Definition at line 25 of file irq.h.

#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */

Definition at line 27 of file irq.h.

#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */

Definition at line 24 of file irq.h.

#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */

Definition at line 26 of file irq.h.

#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */

Definition at line 28 of file irq.h.

#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */

Definition at line 59 of file irq.h.

#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */

Definition at line 61 of file irq.h.

#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */

Definition at line 60 of file irq.h.

#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */

Definition at line 152 of file irq.h.

#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */

Definition at line 18 of file irq.h.

#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */

Definition at line 46 of file irq.h.

#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */

Definition at line 108 of file irq.h.

#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */

Definition at line 109 of file irq.h.

#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */

Definition at line 113 of file irq.h.

#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */

Definition at line 114 of file irq.h.

#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */

Definition at line 151 of file irq.h.

#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */

Definition at line 154 of file irq.h.

#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */

Definition at line 87 of file irq.h.

#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */

Definition at line 89 of file irq.h.

#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */

Definition at line 121 of file irq.h.

#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */

Definition at line 122 of file irq.h.

#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */

Definition at line 123 of file irq.h.

#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */

Definition at line 127 of file irq.h.

#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */

Definition at line 128 of file irq.h.

#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */

Definition at line 129 of file irq.h.

#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */

Definition at line 124 of file irq.h.

#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */

Definition at line 125 of file irq.h.

#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */

Definition at line 126 of file irq.h.

#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */

Definition at line 21 of file irq.h.

#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */

Definition at line 22 of file irq.h.

#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */

Definition at line 91 of file irq.h.

#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */

Definition at line 92 of file irq.h.

#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */

Definition at line 93 of file irq.h.

#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */

Definition at line 94 of file irq.h.

#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */

Definition at line 95 of file irq.h.

#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */

Definition at line 96 of file irq.h.

#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */

Definition at line 97 of file irq.h.

#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */

Definition at line 98 of file irq.h.

#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */

Definition at line 106 of file irq.h.

#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */

Definition at line 105 of file irq.h.

#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */

Definition at line 111 of file irq.h.

#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */

Definition at line 110 of file irq.h.

#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */

Definition at line 116 of file irq.h.

#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */

Definition at line 115 of file irq.h.

#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */

Definition at line 119 of file irq.h.

#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */

Definition at line 118 of file irq.h.

#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0

Definition at line 107 of file irq.h.

#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1

Definition at line 112 of file irq.h.

#define IRQ_MDMAS2 IRQ_MDMA2_DEST

Definition at line 117 of file irq.h.

#define IRQ_MDMAS3 IRQ_MDMA3_DEST

Definition at line 120 of file irq.h.

#define IRQ_PA0 BFIN_PA_IRQ(0)

Definition at line 167 of file irq.h.

#define IRQ_PA1 BFIN_PA_IRQ(1)

Definition at line 168 of file irq.h.

#define IRQ_PA10 BFIN_PA_IRQ(10)

Definition at line 177 of file irq.h.

#define IRQ_PA11 BFIN_PA_IRQ(11)

Definition at line 178 of file irq.h.

#define IRQ_PA12 BFIN_PA_IRQ(12)

Definition at line 179 of file irq.h.

#define IRQ_PA13 BFIN_PA_IRQ(13)

Definition at line 180 of file irq.h.

#define IRQ_PA14 BFIN_PA_IRQ(14)

Definition at line 181 of file irq.h.

#define IRQ_PA15 BFIN_PA_IRQ(15)

Definition at line 182 of file irq.h.

#define IRQ_PA2 BFIN_PA_IRQ(2)

Definition at line 169 of file irq.h.

#define IRQ_PA3 BFIN_PA_IRQ(3)

Definition at line 170 of file irq.h.

#define IRQ_PA4 BFIN_PA_IRQ(4)

Definition at line 171 of file irq.h.

#define IRQ_PA5 BFIN_PA_IRQ(5)

Definition at line 172 of file irq.h.

#define IRQ_PA6 BFIN_PA_IRQ(6)

Definition at line 173 of file irq.h.

#define IRQ_PA7 BFIN_PA_IRQ(7)

Definition at line 174 of file irq.h.

#define IRQ_PA8 BFIN_PA_IRQ(8)

Definition at line 175 of file irq.h.

#define IRQ_PA9 BFIN_PA_IRQ(9)

Definition at line 176 of file irq.h.

#define IRQ_PB0 BFIN_PB_IRQ(0)

Definition at line 185 of file irq.h.

#define IRQ_PB1 BFIN_PB_IRQ(1)

Definition at line 186 of file irq.h.

#define IRQ_PB10 BFIN_PB_IRQ(10)

Definition at line 195 of file irq.h.

#define IRQ_PB11 BFIN_PB_IRQ(11)

Definition at line 196 of file irq.h.

#define IRQ_PB12 BFIN_PB_IRQ(12)

Definition at line 197 of file irq.h.

#define IRQ_PB13 BFIN_PB_IRQ(13)

Definition at line 198 of file irq.h.

#define IRQ_PB14 BFIN_PB_IRQ(14)

Definition at line 199 of file irq.h.

#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */

Definition at line 200 of file irq.h.

#define IRQ_PB2 BFIN_PB_IRQ(2)

Definition at line 187 of file irq.h.

#define IRQ_PB3 BFIN_PB_IRQ(3)

Definition at line 188 of file irq.h.

#define IRQ_PB4 BFIN_PB_IRQ(4)

Definition at line 189 of file irq.h.

#define IRQ_PB5 BFIN_PB_IRQ(5)

Definition at line 190 of file irq.h.

#define IRQ_PB6 BFIN_PB_IRQ(6)

Definition at line 191 of file irq.h.

#define IRQ_PB7 BFIN_PB_IRQ(7)

Definition at line 192 of file irq.h.

#define IRQ_PB8 BFIN_PB_IRQ(8)

Definition at line 193 of file irq.h.

#define IRQ_PB9 BFIN_PB_IRQ(9)

Definition at line 194 of file irq.h.

#define IRQ_PC0 BFIN_PC_IRQ(0)

Definition at line 203 of file irq.h.

#define IRQ_PC1 BFIN_PC_IRQ(1)

Definition at line 204 of file irq.h.

#define IRQ_PC10 BFIN_PC_IRQ(10)

Definition at line 213 of file irq.h.

#define IRQ_PC11 BFIN_PC_IRQ(11)

Definition at line 214 of file irq.h.

#define IRQ_PC12 BFIN_PC_IRQ(12)

Definition at line 215 of file irq.h.

#define IRQ_PC13 BFIN_PC_IRQ(13)

Definition at line 216 of file irq.h.

#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */

Definition at line 217 of file irq.h.

#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */

Definition at line 218 of file irq.h.

#define IRQ_PC2 BFIN_PC_IRQ(2)

Definition at line 205 of file irq.h.

#define IRQ_PC3 BFIN_PC_IRQ(3)

Definition at line 206 of file irq.h.

#define IRQ_PC4 BFIN_PC_IRQ(4)

Definition at line 207 of file irq.h.

#define IRQ_PC5 BFIN_PC_IRQ(5)

Definition at line 208 of file irq.h.

#define IRQ_PC6 BFIN_PC_IRQ(6)

Definition at line 209 of file irq.h.

#define IRQ_PC7 BFIN_PC_IRQ(7)

Definition at line 210 of file irq.h.

#define IRQ_PC8 BFIN_PC_IRQ(8)

Definition at line 211 of file irq.h.

#define IRQ_PC9 BFIN_PC_IRQ(9)

Definition at line 212 of file irq.h.

#define IRQ_PD0 BFIN_PD_IRQ(0)

Definition at line 221 of file irq.h.

#define IRQ_PD1 BFIN_PD_IRQ(1)

Definition at line 222 of file irq.h.

#define IRQ_PD10 BFIN_PD_IRQ(10)

Definition at line 231 of file irq.h.

#define IRQ_PD11 BFIN_PD_IRQ(11)

Definition at line 232 of file irq.h.

#define IRQ_PD12 BFIN_PD_IRQ(12)

Definition at line 233 of file irq.h.

#define IRQ_PD13 BFIN_PD_IRQ(13)

Definition at line 234 of file irq.h.

#define IRQ_PD14 BFIN_PD_IRQ(14)

Definition at line 235 of file irq.h.

#define IRQ_PD15 BFIN_PD_IRQ(15)

Definition at line 236 of file irq.h.

#define IRQ_PD2 BFIN_PD_IRQ(2)

Definition at line 223 of file irq.h.

#define IRQ_PD3 BFIN_PD_IRQ(3)

Definition at line 224 of file irq.h.

#define IRQ_PD4 BFIN_PD_IRQ(4)

Definition at line 225 of file irq.h.

#define IRQ_PD5 BFIN_PD_IRQ(5)

Definition at line 226 of file irq.h.

#define IRQ_PD6 BFIN_PD_IRQ(6)

Definition at line 227 of file irq.h.

#define IRQ_PD7 BFIN_PD_IRQ(7)

Definition at line 228 of file irq.h.

#define IRQ_PD8 BFIN_PD_IRQ(8)

Definition at line 229 of file irq.h.

#define IRQ_PD9 BFIN_PD_IRQ(9)

Definition at line 230 of file irq.h.

#define IRQ_PE0 BFIN_PE_IRQ(0)

Definition at line 239 of file irq.h.

#define IRQ_PE1 BFIN_PE_IRQ(1)

Definition at line 240 of file irq.h.

#define IRQ_PE10 BFIN_PE_IRQ(10)

Definition at line 249 of file irq.h.

#define IRQ_PE11 BFIN_PE_IRQ(11)

Definition at line 250 of file irq.h.

#define IRQ_PE12 BFIN_PE_IRQ(12)

Definition at line 251 of file irq.h.

#define IRQ_PE13 BFIN_PE_IRQ(13)

Definition at line 252 of file irq.h.

#define IRQ_PE14 BFIN_PE_IRQ(14)

Definition at line 253 of file irq.h.

#define IRQ_PE15 BFIN_PE_IRQ(15)

Definition at line 254 of file irq.h.

#define IRQ_PE2 BFIN_PE_IRQ(2)

Definition at line 241 of file irq.h.

#define IRQ_PE3 BFIN_PE_IRQ(3)

Definition at line 242 of file irq.h.

#define IRQ_PE4 BFIN_PE_IRQ(4)

Definition at line 243 of file irq.h.

#define IRQ_PE5 BFIN_PE_IRQ(5)

Definition at line 244 of file irq.h.

#define IRQ_PE6 BFIN_PE_IRQ(6)

Definition at line 245 of file irq.h.

#define IRQ_PE7 BFIN_PE_IRQ(7)

Definition at line 246 of file irq.h.

#define IRQ_PE8 BFIN_PE_IRQ(8)

Definition at line 247 of file irq.h.

#define IRQ_PE9 BFIN_PE_IRQ(9)

Definition at line 248 of file irq.h.

#define IRQ_PF0 BFIN_PF_IRQ(0)

Definition at line 257 of file irq.h.

#define IRQ_PF1 BFIN_PF_IRQ(1)

Definition at line 258 of file irq.h.

#define IRQ_PF10 BFIN_PF_IRQ(10)

Definition at line 267 of file irq.h.

#define IRQ_PF11 BFIN_PF_IRQ(11)

Definition at line 268 of file irq.h.

#define IRQ_PF12 BFIN_PF_IRQ(12)

Definition at line 269 of file irq.h.

#define IRQ_PF13 BFIN_PF_IRQ(13)

Definition at line 270 of file irq.h.

#define IRQ_PF14 BFIN_PF_IRQ(14)

Definition at line 271 of file irq.h.

#define IRQ_PF15 BFIN_PF_IRQ(15)

Definition at line 272 of file irq.h.

#define IRQ_PF2 BFIN_PF_IRQ(2)

Definition at line 259 of file irq.h.

#define IRQ_PF3 BFIN_PF_IRQ(3)

Definition at line 260 of file irq.h.

#define IRQ_PF4 BFIN_PF_IRQ(4)

Definition at line 261 of file irq.h.

#define IRQ_PF5 BFIN_PF_IRQ(5)

Definition at line 262 of file irq.h.

#define IRQ_PF6 BFIN_PF_IRQ(6)

Definition at line 263 of file irq.h.

#define IRQ_PF7 BFIN_PF_IRQ(7)

Definition at line 264 of file irq.h.

#define IRQ_PF8 BFIN_PF_IRQ(8)

Definition at line 265 of file irq.h.

#define IRQ_PF9 BFIN_PF_IRQ(9)

Definition at line 266 of file irq.h.

#define IRQ_PG0 BFIN_PG_IRQ(0)

Definition at line 275 of file irq.h.

#define IRQ_PG1 BFIN_PG_IRQ(1)

Definition at line 276 of file irq.h.

#define IRQ_PG10 BFIN_PG_IRQ(10)

Definition at line 285 of file irq.h.

#define IRQ_PG11 BFIN_PG_IRQ(11)

Definition at line 286 of file irq.h.

#define IRQ_PG12 BFIN_PG_IRQ(12)

Definition at line 287 of file irq.h.

#define IRQ_PG13 BFIN_PG_IRQ(13)

Definition at line 288 of file irq.h.

#define IRQ_PG14 BFIN_PG_IRQ(14)

Definition at line 289 of file irq.h.

#define IRQ_PG15 BFIN_PG_IRQ(15)

Definition at line 290 of file irq.h.

#define IRQ_PG2 BFIN_PG_IRQ(2)

Definition at line 277 of file irq.h.

#define IRQ_PG3 BFIN_PG_IRQ(3)

Definition at line 278 of file irq.h.

#define IRQ_PG4 BFIN_PG_IRQ(4)

Definition at line 279 of file irq.h.

#define IRQ_PG5 BFIN_PG_IRQ(5)

Definition at line 280 of file irq.h.

#define IRQ_PG6 BFIN_PG_IRQ(6)

Definition at line 281 of file irq.h.

#define IRQ_PG7 BFIN_PG_IRQ(7)

Definition at line 282 of file irq.h.

#define IRQ_PG8 BFIN_PG_IRQ(8)

Definition at line 283 of file irq.h.

#define IRQ_PG9 BFIN_PG_IRQ(9)

Definition at line 284 of file irq.h.

#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */

Definition at line 40 of file irq.h.

#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */

Definition at line 41 of file irq.h.

#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */

Definition at line 42 of file irq.h.

#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */

Definition at line 43 of file irq.h.

#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */

Definition at line 44 of file irq.h.

#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */

Definition at line 45 of file irq.h.

#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */

Definition at line 130 of file irq.h.

#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */

Definition at line 131 of file irq.h.

#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */

Definition at line 132 of file irq.h.

#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */

Definition at line 133 of file irq.h.

#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */

Definition at line 137 of file irq.h.

#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */

Definition at line 143 of file irq.h.

#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */

Definition at line 134 of file irq.h.

#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */

Definition at line 135 of file irq.h.

#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */

Definition at line 136 of file irq.h.

#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */

Definition at line 142 of file irq.h.

#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */

Definition at line 140 of file irq.h.

#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */

Definition at line 139 of file irq.h.

#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */

Definition at line 141 of file irq.h.

#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */

Definition at line 138 of file irq.h.

#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */

Definition at line 144 of file irq.h.

#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */

Definition at line 48 of file irq.h.

#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */

Definition at line 47 of file irq.h.

#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */

Definition at line 50 of file irq.h.

#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */

Definition at line 49 of file irq.h.

#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */

Definition at line 80 of file irq.h.

#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */

Definition at line 81 of file irq.h.

#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */

Definition at line 82 of file irq.h.

#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */

Definition at line 83 of file irq.h.

#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */

Definition at line 17 of file irq.h.

#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */

Definition at line 53 of file irq.h.

#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */

Definition at line 54 of file irq.h.

#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */

Definition at line 55 of file irq.h.

#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */

Definition at line 56 of file irq.h.

#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */

Definition at line 75 of file irq.h.

#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */

Definition at line 76 of file irq.h.

#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */

Definition at line 74 of file irq.h.

#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */

Definition at line 78 of file irq.h.

#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */

Definition at line 79 of file irq.h.

#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */

Definition at line 77 of file irq.h.

#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */

Definition at line 64 of file irq.h.

#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */

Definition at line 65 of file irq.h.

#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */

Definition at line 62 of file irq.h.

#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */

Definition at line 63 of file irq.h.

#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */

Definition at line 68 of file irq.h.

#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */

Definition at line 69 of file irq.h.

#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */

Definition at line 66 of file irq.h.

#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */

Definition at line 67 of file irq.h.

#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */

Definition at line 72 of file irq.h.

#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */

Definition at line 73 of file irq.h.

#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */

Definition at line 70 of file irq.h.

#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */

Definition at line 71 of file irq.h.

#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */

Definition at line 156 of file irq.h.

#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */

Definition at line 157 of file irq.h.

#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */

Definition at line 158 of file irq.h.

#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */

Definition at line 159 of file irq.h.

#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */

Definition at line 160 of file irq.h.

#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */

Definition at line 161 of file irq.h.

#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */

Definition at line 162 of file irq.h.

#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */

Definition at line 31 of file irq.h.

#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */

Definition at line 32 of file irq.h.

#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */

Definition at line 33 of file irq.h.

#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */

Definition at line 34 of file irq.h.

#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */

Definition at line 35 of file irq.h.

#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */

Definition at line 36 of file irq.h.

#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */

Definition at line 37 of file irq.h.

#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */

Definition at line 38 of file irq.h.

#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */

Definition at line 39 of file irq.h.

#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */

Definition at line 147 of file irq.h.

#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */

Definition at line 148 of file irq.h.

#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */

Definition at line 149 of file irq.h.

#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */

Definition at line 150 of file irq.h.

#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */

Definition at line 51 of file irq.h.

#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */

Definition at line 52 of file irq.h.

#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */

Definition at line 100 of file irq.h.

#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */

Definition at line 101 of file irq.h.

#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */

Definition at line 99 of file irq.h.

#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */

Definition at line 103 of file irq.h.

#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */

Definition at line 104 of file irq.h.

#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */

Definition at line 102 of file irq.h.

#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */

Definition at line 146 of file irq.h.

#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */

Definition at line 145 of file irq.h.

#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */

Definition at line 19 of file irq.h.

#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */

Definition at line 20 of file irq.h.

#define NR_MACH_IRQS (IRQ_PG15 + 1)

Definition at line 294 of file irq.h.

#define NR_PERI_INTS (5 * 32)

Definition at line 15 of file irq.h.

#define SEC_SCTL_PRIO_OFFSET 8

Definition at line 296 of file irq.h.

#define SYS_IRQS IRQ_SWU6

Definition at line 164 of file irq.h.

Variable Documentation

u8 sec_int_priority[]

Definition at line 13 of file ints-priority.c.

Data Structures

Macros

Variables

Macro Definition Documentation

Variable Documentation