15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
20 #include <linux/slab.h>
23 #include <linux/export.h>
25 #include <asm/machvec.h>
31 #include <asm/hw_irq.h>
39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
40 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
45 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
53 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
56 if ((seg | reg) <= 255) {
66 result = ia64_sal_pci_config_read(addr, mode, len, &data);
80 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
83 if ((seg | reg) <= 255) {
92 result = ia64_sal_pci_config_write(addr, mode, len, value);
102 devfn, where, size, value);
105 static int pci_write(
struct pci_bus *bus,
unsigned int devfn,
int where,
109 devfn, where, size, value);
124 controller = kzalloc(
sizeof(*controller),
GFP_KERNEL);
129 controller->
node = -1;
141 new_space (
u64 phys_base,
int sparse)
151 if (
io_space[i].mmio_base == mmio_base &&
174 unsigned int sparse = 0, space_nr,
len;
176 resource = kzalloc(
sizeof(*resource),
GFP_KERNEL);
202 snprintf(name, len,
"%s I/O Ports %08lx-%08lx", info->
name,
203 base_port + min, base_port + max);
255 unsigned int *windows = (
unsigned int *) data;
259 status = resource_to_window(resource, &addr);
273 struct resource *
root;
276 status = resource_to_window(res, &addr);
287 offset = add_io_space(info, &addr);
302 "can't allocate host bridge window %pR\n",
307 "(PCI address [%#llx-%#llx])\n",
313 "host bridge window %pR\n",
330 struct acpi_device *
device = root->device;
331 int domain = root->segment;
332 int bus = root->secondary.start;
334 unsigned int windows = 0;
359 kzalloc_node(
sizeof(*controller->
window) * windows,
368 sprintf(name,
"PCI Bus %04x:%02x", domain, bus);
402 struct resource *devr = &dev->
resource[
idx], *busr;
407 pci_bus_for_each_resource(dev->
bus, busr, i) {
408 if (!busr || ((busr->flags ^ devr->
flags) & type_mask))
410 if ((devr->
start) && (devr->
start >= busr->start) &&
411 (devr->
end <= busr->end))
422 for (i = start; i <
limit; i++) {
425 if ((is_valid_resource(dev, i)))
451 pcibios_fixup_bridge_resources(b->
self);
586 return PTR_ERR(addr);
672 static void __init set_pci_dfl_cacheline_size(
void)
674 unsigned long levels, unique_caches;
678 status = ia64_pal_cache_summary(&levels, &unique_caches);
681 "(status=%ld)\n", __func__, status);
685 status = ia64_pal_cache_config_info(levels - 1,
689 "(status=%ld)\n", __func__, status);
701 if (!high_totalram) {
703 low_totalram = (1 << (fls(low_totalram) - 1));
704 low_totalram += low_totalram - 1;
707 high_totalram = (1 << (fls(high_totalram) - 1));
708 high_totalram += high_totalram - 1;
709 mask = (((
u64)high_totalram) << 32) + 0xffffffff;
723 set_pci_dfl_cacheline_size();