#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/io.h>
#include <asm/smp.h>
Go to the source code of this file.
#define EIEM_MASK |
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irq | ) |
(1UL<<(CPU_IRQ_MAX - irq)) |
Definition at line 41 of file irq.c.
Definition at line 83 of file irq.c.
Definition at line 98 of file irq.c.
The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.
The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.
Definition at line 409 of file irq.c.
unsigned long txn_affinity_addr |
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unsigned int |
irq, |
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int |
cpu |
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unsigned long txn_alloc_addr |
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unsigned int |
virt_irq | ) |
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unsigned int txn_alloc_data |
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unsigned int |
virt_irq | ) |
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int txn_alloc_irq |
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unsigned int |
bits_wide | ) |
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