Linux Kernel  3.7.1
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pci.c
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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License. See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1997, 1998 Ralf Baechle
7  * Copyright (C) 1999 SuSE GmbH
8  * Copyright (C) 1999-2001 Hewlett-Packard Company
9  * Copyright (C) 1999-2001 Grant Grundler
10  */
11 #include <linux/eisa.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/types.h>
17 
18 #include <asm/io.h>
19 #include <asm/superio.h>
20 
21 #define DEBUG_RESOURCES 0
22 #define DEBUG_CONFIG 0
23 
24 #if DEBUG_CONFIG
25 # define DBGC(x...) printk(KERN_DEBUG x)
26 #else
27 # define DBGC(x...)
28 #endif
29 
30 
31 #if DEBUG_RESOURCES
32 #define DBG_RES(x...) printk(KERN_DEBUG x)
33 #else
34 #define DBG_RES(x...)
35 #endif
36 
37 /* To be used as: mdelay(pci_post_reset_delay);
38  *
39  * post_reset is the time the kernel should stall to prevent anyone from
40  * accessing the PCI bus once #RESET is de-asserted.
41  * PCI spec somewhere says 1 second but with multi-PCI bus systems,
42  * this makes the boot time much longer than necessary.
43  * 20ms seems to work for all the HP PCI implementations to date.
44  *
45  * #define pci_post_reset_delay 50
46  */
47 
50 
51 static int pci_hba_count __read_mostly;
52 
53 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
54 #define PCI_HBA_MAX 32
55 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
56 
57 
58 /********************************************************************
59 **
60 ** I/O port space support
61 **
62 *********************************************************************/
63 
64 /* EISA port numbers and PCI port numbers share the same interface. Some
65  * machines have both EISA and PCI adapters installed. Rather than turn
66  * pci_port into an array, we reserve bus 0 for EISA and call the EISA
67  * routines if the access is to a port on bus 0. We don't want to fix
68  * EISA and ISA drivers which assume port space is <= 0xffff.
69  */
70 
71 #ifdef CONFIG_EISA
72 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
73 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
74 #else
75 #define EISA_IN(size)
76 #define EISA_OUT(size)
77 #endif
78 
79 #define PCI_PORT_IN(type, size) \
80 u##size in##type (int addr) \
81 { \
82  int b = PCI_PORT_HBA(addr); \
83  EISA_IN(size); \
84  if (!parisc_pci_hba[b]) return (u##size) -1; \
85  return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
86 } \
87 EXPORT_SYMBOL(in##type);
88 
89 PCI_PORT_IN(b, 8)
90 PCI_PORT_IN(w, 16)
91 PCI_PORT_IN(l, 32)
92 
93 
94 #define PCI_PORT_OUT(type, size) \
95 void out##type (u##size d, int addr) \
96 { \
97  int b = PCI_PORT_HBA(addr); \
98  EISA_OUT(size); \
99  if (!parisc_pci_hba[b]) return; \
100  pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
101 } \
102 EXPORT_SYMBOL(out##type);
103 
104 PCI_PORT_OUT(b, 8)
105 PCI_PORT_OUT(w, 16)
106 PCI_PORT_OUT(l, 32)
107 
108 
109 
110 /*
111  * BIOS32 replacement.
112  */
113 static int __init pcibios_init(void)
114 {
115  if (!pci_bios)
116  return -1;
117 
118  if (pci_bios->init) {
119  pci_bios->init();
120  } else {
121  printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
122  }
123 
124  /* Set the CLS for PCI as early as possible. */
126 
127  return 0;
128 }
129 
130 
131 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
133 {
134  if (pci_bios->fixup_bus) {
135  pci_bios->fixup_bus(bus);
136  } else {
137  printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
138  }
139 }
140 
141 
142 /*
143  * Called by pci_set_master() - a driver interface.
144  *
145  * Legacy PDC guarantees to set:
146  * Map Memory BAR's into PA IO space.
147  * Map Expansion ROM BAR into one common PA IO space per bus.
148  * Map IO BAR's into PCI IO space.
149  * Command (see below)
150  * Cache Line Size
151  * Latency Timer
152  * Interrupt Line
153  * PPB: secondary latency timer, io/mmio base/limit,
154  * bus numbers, bridge control
155  *
156  */
158 {
159  u8 lat;
160 
161  /* If someone already mucked with this, don't touch it. */
162  pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
163  if (lat >= 16) return;
164 
165  /*
166  ** HP generally has fewer devices on the bus than other architectures.
167  ** upper byte is PCI_LATENCY_TIMER.
168  */
169  pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
170  (0x80 << 8) | pci_cache_line_size);
171 }
172 
173 
175 {
176  struct pci_dev *dev = bus->self;
177  unsigned short bridge_ctl;
178 
179  /* We deal only with pci controllers and pci-pci bridges. */
180  if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
181  return;
182 
183  /* PCI-PCI bridge - set the cache line and default latency
184  (32) for primary and secondary buses. */
185  pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
186 
187  pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
189  pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
190 }
191 
192 /*
193  * pcibios align resources() is called every time generic PCI code
194  * wants to generate a new address. The process of looking for
195  * an available address, each candidate is first "aligned" and
196  * then checked if the resource is available until a match is found.
197  *
198  * Since we are just checking candidates, don't use any fields other
199  * than res->start.
200  */
203 {
205 
206  DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
207  pci_name(((struct pci_dev *) data)),
208  res->parent, res->start, res->end,
209  (int) res->flags, size, alignment);
210 
211  /* If it's not IO, then it's gotta be MEM */
212  align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
213 
214  /* Align to largest of MIN or input size */
215  mask = max(alignment, align) - 1;
216  start += mask;
217  start &= ~mask;
218 
219  return start;
220 }
221 
222 
223 /*
224  * A driver is enabling the device. We make sure that all the appropriate
225  * bits are set to allow the device to operate as the driver is expecting.
226  * We enable the port IO and memory IO bits if the device has any BARs of
227  * that type, and we enable the PERR and SERR bits unconditionally.
228  * Drivers that do not need parity (eg graphics and possibly networking)
229  * can clear these bits if they want.
230  */
232 {
233  int err;
234  u16 cmd, old_cmd;
235 
236  err = pci_enable_resources(dev, mask);
237  if (err < 0)
238  return err;
239 
240  pci_read_config_word(dev, PCI_COMMAND, &cmd);
241  old_cmd = cmd;
242 
244 
245 #if 0
246  /* If bridge/bus controller has FBB enabled, child must too. */
247  if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
248  cmd |= PCI_COMMAND_FAST_BACK;
249 #endif
250 
251  if (cmd != old_cmd) {
252  dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
253  old_cmd, cmd);
254  pci_write_config_word(dev, PCI_COMMAND, cmd);
255  }
256  return 0;
257 }
258 
259 
260 /* PA-RISC specific */
262 {
263  if (pci_hba_count >= PCI_HBA_MAX) {
264  printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
265  return;
266  }
267 
268  parisc_pci_hba[pci_hba_count] = hba;
269  hba->hba_num = pci_hba_count++;
270 }
271 
272 subsys_initcall(pcibios_init);