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perf_event.c File Reference
#include <linux/bitmap.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <asm/cputype.h>
#include <asm/irq.h>
#include <asm/irq_regs.h>
#include <asm/pmu.h>
#include <asm/stacktrace.h>

Go to the source code of this file.

Data Structures

struct  frame_tail
 

Macros

#define pr_fmt(fmt)   "hw perfevents: " fmt
 
#define ARMPMU_MAX_HWEVENTS   32
 
#define to_arm_pmu(p)   (container_of(p, struct arm_pmu, pmu))
 
#define HW_OP_UNSUPPORTED   0xFFFF
 
#define C(_x)   PERF_COUNT_HW_CACHE_##_x
 
#define CACHE_OP_UNSUPPORTED   0xFFFF
 
#define ARMV8_IDX_CYCLE_COUNTER   0
 
#define ARMV8_IDX_COUNTER0   1
 
#define ARMV8_IDX_COUNTER_LAST   (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 
#define ARMV8_MAX_COUNTERS   32
 
#define ARMV8_COUNTER_MASK   (ARMV8_MAX_COUNTERS - 1)
 
#define ARMV8_IDX_TO_COUNTER(x)   (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
 
#define ARMV8_PMCR_E   (1 << 0) /* Enable all counters */
 
#define ARMV8_PMCR_P   (1 << 1) /* Reset all counters */
 
#define ARMV8_PMCR_C   (1 << 2) /* Cycle counter reset */
 
#define ARMV8_PMCR_D   (1 << 3) /* CCNT counts every 64th cpu cycle */
 
#define ARMV8_PMCR_X   (1 << 4) /* Export to ETM */
 
#define ARMV8_PMCR_DP   (1 << 5) /* Disable CCNT if non-invasive debug*/
 
#define ARMV8_PMCR_N_SHIFT   11 /* Number of counters supported */
 
#define ARMV8_PMCR_N_MASK   0x1f
 
#define ARMV8_PMCR_MASK   0x3f /* Mask for writable bits */
 
#define ARMV8_OVSR_MASK   0xffffffff /* Mask for writable bits */
 
#define ARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK
 
#define ARMV8_EVTYPE_MASK   0xc00000ff /* Mask for writable bits */
 
#define ARMV8_EVTYPE_EVENT   0xff /* Mask for EVENT bits */
 
#define ARMV8_EXCLUDE_EL1   (1 << 31)
 
#define ARMV8_EXCLUDE_EL0   (1 << 30)
 
#define ARMV8_INCLUDE_EL2   (1 << 27)
 

Enumerations

enum  armv8_pmuv3_perf_types {
  ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR = 0x00, ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL = 0x03, ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS = 0x04, ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
  ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES = 0x11, ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED = 0x12, ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED = 0x08, ARMV8_PMUV3_PERFCTR_OP_SPEC = 0x1B,
  ARMV8_PMUV3_PERFCTR_MEM_READ = 0x06, ARMV8_PMUV3_PERFCTR_MEM_WRITE = 0x07, ARMV8_PMUV3_PERFCTR_EXC_TAKEN = 0x09, ARMV8_PMUV3_PERFCTR_EXC_EXECUTED = 0x0A,
  ARMV8_PMUV3_PERFCTR_CID_WRITE = 0x0B, ARMV8_PMUV3_PERFCTR_PC_WRITE = 0x0C, ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH = 0x0D, ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN = 0x0E,
  ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F, ARMV8_PMUV3_PERFCTR_TTBR_WRITE = 0x1C, ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL = 0x01, ARMV8_PMUV3_PERFCTR_ITLB_REFILL = 0x02,
  ARMV8_PMUV3_PERFCTR_DTLB_REFILL = 0x05, ARMV8_PMUV3_PERFCTR_MEM_ACCESS = 0x13, ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS = 0x14, ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB = 0x15,
  ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS = 0x16, ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL = 0x17, ARMV8_PMUV3_PERFCTR_L2_CACHE_WB = 0x18, ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
  ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A, ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D
}
 

Functions

int armpmu_get_max_events (void)
 
 EXPORT_SYMBOL_GPL (armpmu_get_max_events)
 
int perf_num_counters (void)
 
 EXPORT_SYMBOL_GPL (perf_num_counters)
 
int armpmu_event_set_period (struct perf_event *event, struct hw_perf_event *hwc, int idx)
 
u64 armpmu_event_update (struct perf_event *event, struct hw_perf_event *hwc, int idx)
 
int __init armpmu_register (struct arm_pmu *armpmu, char *name, int type)
 
 arch_initcall (cpu_pmu_reset)
 
 device_initcall (register_pmu_driver)
 
 early_initcall (init_hw_perf_events)
 
struct frame_tail __attribute__ ((packed))
 
void perf_callchain_user (struct perf_callchain_entry *entry, struct pt_regs *regs)
 
void perf_callchain_kernel (struct perf_callchain_entry *entry, struct pt_regs *regs)
 

Variables

struct frame_tail __user * fp
 
unsigned long lr
 

Macro Definition Documentation

#define ARMPMU_MAX_HWEVENTS   32

Definition at line 42 of file perf_event.c.

#define ARMV8_COUNTER_MASK   (ARMV8_MAX_COUNTERS - 1)

Definition at line 742 of file perf_event.c.

#define ARMV8_EVTYPE_EVENT   0xff /* Mask for EVENT bits */

Definition at line 777 of file perf_event.c.

#define ARMV8_EVTYPE_MASK   0xc00000ff /* Mask for writable bits */

Definition at line 776 of file perf_event.c.

#define ARMV8_EXCLUDE_EL0   (1 << 30)

Definition at line 783 of file perf_event.c.

#define ARMV8_EXCLUDE_EL1   (1 << 31)

Definition at line 782 of file perf_event.c.

#define ARMV8_IDX_COUNTER0   1

Definition at line 738 of file perf_event.c.

#define ARMV8_IDX_COUNTER_LAST   (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)

Definition at line 739 of file perf_event.c.

#define ARMV8_IDX_CYCLE_COUNTER   0

Definition at line 737 of file perf_event.c.

#define ARMV8_IDX_TO_COUNTER (   x)    (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)

Definition at line 751 of file perf_event.c.

#define ARMV8_INCLUDE_EL2   (1 << 27)

Definition at line 784 of file perf_event.c.

#define ARMV8_MAX_COUNTERS   32

Definition at line 741 of file perf_event.c.

#define ARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK

Definition at line 771 of file perf_event.c.

#define ARMV8_OVSR_MASK   0xffffffff /* Mask for writable bits */

Definition at line 770 of file perf_event.c.

#define ARMV8_PMCR_C   (1 << 2) /* Cycle counter reset */

Definition at line 759 of file perf_event.c.

#define ARMV8_PMCR_D   (1 << 3) /* CCNT counts every 64th cpu cycle */

Definition at line 760 of file perf_event.c.

#define ARMV8_PMCR_DP   (1 << 5) /* Disable CCNT if non-invasive debug*/

Definition at line 762 of file perf_event.c.

#define ARMV8_PMCR_E   (1 << 0) /* Enable all counters */

Definition at line 757 of file perf_event.c.

#define ARMV8_PMCR_MASK   0x3f /* Mask for writable bits */

Definition at line 765 of file perf_event.c.

#define ARMV8_PMCR_N_MASK   0x1f

Definition at line 764 of file perf_event.c.

#define ARMV8_PMCR_N_SHIFT   11 /* Number of counters supported */

Definition at line 763 of file perf_event.c.

#define ARMV8_PMCR_P   (1 << 1) /* Reset all counters */

Definition at line 758 of file perf_event.c.

#define ARMV8_PMCR_X   (1 << 4) /* Export to ETM */

Definition at line 761 of file perf_event.c.

#define C (   _x)    PERF_COUNT_HW_CACHE_##_x

Definition at line 73 of file perf_event.c.

#define CACHE_OP_UNSUPPORTED   0xFFFF

Definition at line 76 of file perf_event.c.

#define HW_OP_UNSUPPORTED   0xFFFF

Definition at line 71 of file perf_event.c.

#define pr_fmt (   fmt)    "hw perfevents: " fmt

Definition at line 21 of file perf_event.c.

#define to_arm_pmu (   p)    (container_of(p, struct arm_pmu, pmu))

Definition at line 48 of file perf_event.c.

Enumeration Type Documentation

enum armv8_pmuv3_perf_types
Enumerator:
ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR 
ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL 
ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS 
ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED 
ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES 
ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED 
ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED 
ARMV8_PMUV3_PERFCTR_OP_SPEC 
ARMV8_PMUV3_PERFCTR_MEM_READ 
ARMV8_PMUV3_PERFCTR_MEM_WRITE 
ARMV8_PMUV3_PERFCTR_EXC_TAKEN 
ARMV8_PMUV3_PERFCTR_EXC_EXECUTED 
ARMV8_PMUV3_PERFCTR_CID_WRITE 
ARMV8_PMUV3_PERFCTR_PC_WRITE 
ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH 
ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN 
ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS 
ARMV8_PMUV3_PERFCTR_TTBR_WRITE 
ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL 
ARMV8_PMUV3_PERFCTR_ITLB_REFILL 
ARMV8_PMUV3_PERFCTR_DTLB_REFILL 
ARMV8_PMUV3_PERFCTR_MEM_ACCESS 
ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS 
ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB 
ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS 
ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL 
ARMV8_PMUV3_PERFCTR_L2_CACHE_WB 
ARMV8_PMUV3_PERFCTR_BUS_ACCESS 
ARMV8_PMUV3_PERFCTR_MEM_ERROR 
ARMV8_PMUV3_PERFCTR_BUS_CYCLES 

Definition at line 578 of file perf_event.c.

Function Documentation

struct frame_tail __attribute__ ( (packed)  )
read

Definition at line 171 of file esd_usb2.c.

arch_initcall ( cpu_pmu_reset  )
int armpmu_event_set_period ( struct perf_event *  event,
struct hw_perf_event *  hwc,
int  idx 
)

Definition at line 143 of file perf_event.c.

u64 armpmu_event_update ( struct perf_event *  event,
struct hw_perf_event *  hwc,
int  idx 
)

Definition at line 179 of file perf_event.c.

int armpmu_get_max_events ( void  )

Definition at line 54 of file perf_event.c.

int __init armpmu_register ( struct arm_pmu *  armpmu,
char *  name,
int  type 
)

Definition at line 568 of file perf_event.c.

device_initcall ( register_pmu_driver  )
early_initcall ( init_hw_perf_events  )
EXPORT_SYMBOL_GPL ( armpmu_get_max_events  )
EXPORT_SYMBOL_GPL ( perf_num_counters  )
void perf_callchain_kernel ( struct perf_callchain_entry *  entry,
struct pt_regs *  regs 
)

Definition at line 1353 of file perf_event.c.

void perf_callchain_user ( struct perf_callchain_entry *  entry,
struct pt_regs *  regs 
)

Definition at line 1329 of file perf_event.c.

int perf_num_counters ( void  )

Definition at line 65 of file perf_event.c.

Variable Documentation

struct frame_tail __user* fp

Definition at line 1294 of file perf_event.c.

unsigned long lr

Definition at line 1295 of file perf_event.c.

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