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Macros
at91_mci.h File Reference

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Macros

#define AT91_MCI_CR   0x00 /* Control Register */
 
#define AT91_MCI_MCIEN   (1 << 0) /* Multi-Media Interface Enable */
 
#define AT91_MCI_MCIDIS   (1 << 1) /* Multi-Media Interface Disable */
 
#define AT91_MCI_PWSEN   (1 << 2) /* Power Save Mode Enable */
 
#define AT91_MCI_PWSDIS   (1 << 3) /* Power Save Mode Disable */
 
#define AT91_MCI_SWRST   (1 << 7) /* Software Reset */
 
#define AT91_MCI_MR   0x04 /* Mode Register */
 
#define AT91_MCI_CLKDIV   (0xff << 0) /* Clock Divider */
 
#define AT91_MCI_PWSDIV   (7 << 8) /* Power Saving Divider */
 
#define AT91_MCI_RDPROOF   (1 << 11) /* Read Proof Enable [SAM926[03] only] */
 
#define AT91_MCI_WRPROOF   (1 << 12) /* Write Proof Enable [SAM926[03] only] */
 
#define AT91_MCI_PDCFBYTE   (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
 
#define AT91_MCI_PDCPADV   (1 << 14) /* PDC Padding Value */
 
#define AT91_MCI_PDCMODE   (1 << 15) /* PDC-orientated Mode */
 
#define AT91_MCI_BLKLEN   (0xfff << 18) /* Data Block Length */
 
#define AT91_MCI_DTOR   0x08 /* Data Timeout Register */
 
#define AT91_MCI_DTOCYC   (0xf << 0) /* Data Timeout Cycle Number */
 
#define AT91_MCI_DTOMUL   (7 << 4) /* Data Timeout Multiplier */
 
#define AT91_MCI_DTOMUL_1   (0 << 4)
 
#define AT91_MCI_DTOMUL_16   (1 << 4)
 
#define AT91_MCI_DTOMUL_128   (2 << 4)
 
#define AT91_MCI_DTOMUL_256   (3 << 4)
 
#define AT91_MCI_DTOMUL_1K   (4 << 4)
 
#define AT91_MCI_DTOMUL_4K   (5 << 4)
 
#define AT91_MCI_DTOMUL_64K   (6 << 4)
 
#define AT91_MCI_DTOMUL_1M   (7 << 4)
 
#define AT91_MCI_SDCR   0x0c /* SD Card Register */
 
#define AT91_MCI_SDCSEL   (3 << 0) /* SD Card Selector */
 
#define AT91_MCI_SDCBUS   (1 << 7) /* 1-bit or 4-bit bus */
 
#define AT91_MCI_ARGR   0x10 /* Argument Register */
 
#define AT91_MCI_CMDR   0x14 /* Command Register */
 
#define AT91_MCI_CMDNB   (0x3f << 0) /* Command Number */
 
#define AT91_MCI_RSPTYP   (3 << 6) /* Response Type */
 
#define AT91_MCI_RSPTYP_NONE   (0 << 6)
 
#define AT91_MCI_RSPTYP_48   (1 << 6)
 
#define AT91_MCI_RSPTYP_136   (2 << 6)
 
#define AT91_MCI_SPCMD   (7 << 8) /* Special Command */
 
#define AT91_MCI_SPCMD_NONE   (0 << 8)
 
#define AT91_MCI_SPCMD_INIT   (1 << 8)
 
#define AT91_MCI_SPCMD_SYNC   (2 << 8)
 
#define AT91_MCI_SPCMD_ICMD   (4 << 8)
 
#define AT91_MCI_SPCMD_IRESP   (5 << 8)
 
#define AT91_MCI_OPDCMD   (1 << 11) /* Open Drain Command */
 
#define AT91_MCI_MAXLAT   (1 << 12) /* Max Latency for Command to Response */
 
#define AT91_MCI_TRCMD   (3 << 16) /* Transfer Command */
 
#define AT91_MCI_TRCMD_NONE   (0 << 16)
 
#define AT91_MCI_TRCMD_START   (1 << 16)
 
#define AT91_MCI_TRCMD_STOP   (2 << 16)
 
#define AT91_MCI_TRDIR   (1 << 18) /* Transfer Direction */
 
#define AT91_MCI_TRTYP   (3 << 19) /* Transfer Type */
 
#define AT91_MCI_TRTYP_BLOCK   (0 << 19)
 
#define AT91_MCI_TRTYP_MULTIPLE   (1 << 19)
 
#define AT91_MCI_TRTYP_STREAM   (2 << 19)
 
#define AT91_MCI_TRTYP_SDIO_BYTE   (4 << 19)
 
#define AT91_MCI_TRTYP_SDIO_BLOCK   (5 << 19)
 
#define AT91_MCI_BLKR   0x18 /* Block Register */
 
#define AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0) /* Block count */
 
#define AT91_MCI_BLKR_BLKLEN(n)   ((0xffff & (n)) << 16) /* Block length */
 
#define AT91_MCI_RSPR(n)   (0x20 + ((n) * 4)) /* Response Registers 0-3 */
 
#define AT91_MCR_RDR   0x30 /* Receive Data Register */
 
#define AT91_MCR_TDR   0x34 /* Transmit Data Register */
 
#define AT91_MCI_SR   0x40 /* Status Register */
 
#define AT91_MCI_CMDRDY   (1 << 0) /* Command Ready */
 
#define AT91_MCI_RXRDY   (1 << 1) /* Receiver Ready */
 
#define AT91_MCI_TXRDY   (1 << 2) /* Transmit Ready */
 
#define AT91_MCI_BLKE   (1 << 3) /* Data Block Ended */
 
#define AT91_MCI_DTIP   (1 << 4) /* Data Transfer in Progress */
 
#define AT91_MCI_NOTBUSY   (1 << 5) /* Data Not Busy */
 
#define AT91_MCI_ENDRX   (1 << 6) /* End of RX Buffer */
 
#define AT91_MCI_ENDTX   (1 << 7) /* End fo TX Buffer */
 
#define AT91_MCI_SDIOIRQA   (1 << 8) /* SDIO Interrupt for Slot A */
 
#define AT91_MCI_SDIOIRQB   (1 << 9) /* SDIO Interrupt for Slot B */
 
#define AT91_MCI_RXBUFF   (1 << 14) /* RX Buffer Full */
 
#define AT91_MCI_TXBUFE   (1 << 15) /* TX Buffer Empty */
 
#define AT91_MCI_RINDE   (1 << 16) /* Response Index Error */
 
#define AT91_MCI_RDIRE   (1 << 17) /* Response Direction Error */
 
#define AT91_MCI_RCRCE   (1 << 18) /* Response CRC Error */
 
#define AT91_MCI_RENDE   (1 << 19) /* Response End Bit Error */
 
#define AT91_MCI_RTOE   (1 << 20) /* Response Time-out Error */
 
#define AT91_MCI_DCRCE   (1 << 21) /* Data CRC Error */
 
#define AT91_MCI_DTOE   (1 << 22) /* Data Time-out Error */
 
#define AT91_MCI_OVRE   (1 << 30) /* Overrun */
 
#define AT91_MCI_UNRE   (1 << 31) /* Underrun */
 
#define AT91_MCI_IER   0x44 /* Interrupt Enable Register */
 
#define AT91_MCI_IDR   0x48 /* Interrupt Disable Register */
 
#define AT91_MCI_IMR   0x4c /* Interrupt Mask Register */
 

Macro Definition Documentation

#define AT91_MCI_ARGR   0x10 /* Argument Register */

Definition at line 52 of file at91_mci.h.

#define AT91_MCI_BLKE   (1 << 3) /* Data Block Ended */

Definition at line 92 of file at91_mci.h.

#define AT91_MCI_BLKLEN   (0xfff << 18) /* Data Block Length */

Definition at line 34 of file at91_mci.h.

#define AT91_MCI_BLKR   0x18 /* Block Register */

Definition at line 80 of file at91_mci.h.

#define AT91_MCI_BLKR_BCNT (   n)    ((0xffff & (n)) << 0) /* Block count */

Definition at line 81 of file at91_mci.h.

#define AT91_MCI_BLKR_BLKLEN (   n)    ((0xffff & (n)) << 16) /* Block length */

Definition at line 82 of file at91_mci.h.

#define AT91_MCI_CLKDIV   (0xff << 0) /* Clock Divider */

Definition at line 27 of file at91_mci.h.

#define AT91_MCI_CMDNB   (0x3f << 0) /* Command Number */

Definition at line 55 of file at91_mci.h.

#define AT91_MCI_CMDR   0x14 /* Command Register */

Definition at line 54 of file at91_mci.h.

#define AT91_MCI_CMDRDY   (1 << 0) /* Command Ready */

Definition at line 89 of file at91_mci.h.

#define AT91_MCI_CR   0x00 /* Control Register */

Definition at line 19 of file at91_mci.h.

#define AT91_MCI_DCRCE   (1 << 21) /* Data CRC Error */

Definition at line 106 of file at91_mci.h.

#define AT91_MCI_DTIP   (1 << 4) /* Data Transfer in Progress */

Definition at line 93 of file at91_mci.h.

#define AT91_MCI_DTOCYC   (0xf << 0) /* Data Timeout Cycle Number */

Definition at line 37 of file at91_mci.h.

#define AT91_MCI_DTOE   (1 << 22) /* Data Time-out Error */

Definition at line 107 of file at91_mci.h.

#define AT91_MCI_DTOMUL   (7 << 4) /* Data Timeout Multiplier */

Definition at line 38 of file at91_mci.h.

#define AT91_MCI_DTOMUL_1   (0 << 4)

Definition at line 39 of file at91_mci.h.

#define AT91_MCI_DTOMUL_128   (2 << 4)

Definition at line 41 of file at91_mci.h.

#define AT91_MCI_DTOMUL_16   (1 << 4)

Definition at line 40 of file at91_mci.h.

#define AT91_MCI_DTOMUL_1K   (4 << 4)

Definition at line 43 of file at91_mci.h.

#define AT91_MCI_DTOMUL_1M   (7 << 4)

Definition at line 46 of file at91_mci.h.

#define AT91_MCI_DTOMUL_256   (3 << 4)

Definition at line 42 of file at91_mci.h.

#define AT91_MCI_DTOMUL_4K   (5 << 4)

Definition at line 44 of file at91_mci.h.

#define AT91_MCI_DTOMUL_64K   (6 << 4)

Definition at line 45 of file at91_mci.h.

#define AT91_MCI_DTOR   0x08 /* Data Timeout Register */

Definition at line 36 of file at91_mci.h.

#define AT91_MCI_ENDRX   (1 << 6) /* End of RX Buffer */

Definition at line 95 of file at91_mci.h.

#define AT91_MCI_ENDTX   (1 << 7) /* End fo TX Buffer */

Definition at line 96 of file at91_mci.h.

#define AT91_MCI_IDR   0x48 /* Interrupt Disable Register */

Definition at line 112 of file at91_mci.h.

#define AT91_MCI_IER   0x44 /* Interrupt Enable Register */

Definition at line 111 of file at91_mci.h.

#define AT91_MCI_IMR   0x4c /* Interrupt Mask Register */

Definition at line 113 of file at91_mci.h.

#define AT91_MCI_MAXLAT   (1 << 12) /* Max Latency for Command to Response */

Definition at line 67 of file at91_mci.h.

#define AT91_MCI_MCIDIS   (1 << 1) /* Multi-Media Interface Disable */

Definition at line 21 of file at91_mci.h.

#define AT91_MCI_MCIEN   (1 << 0) /* Multi-Media Interface Enable */

Definition at line 20 of file at91_mci.h.

#define AT91_MCI_MR   0x04 /* Mode Register */

Definition at line 26 of file at91_mci.h.

#define AT91_MCI_NOTBUSY   (1 << 5) /* Data Not Busy */

Definition at line 94 of file at91_mci.h.

#define AT91_MCI_OPDCMD   (1 << 11) /* Open Drain Command */

Definition at line 66 of file at91_mci.h.

#define AT91_MCI_OVRE   (1 << 30) /* Overrun */

Definition at line 108 of file at91_mci.h.

#define AT91_MCI_PDCFBYTE   (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */

Definition at line 31 of file at91_mci.h.

#define AT91_MCI_PDCMODE   (1 << 15) /* PDC-orientated Mode */

Definition at line 33 of file at91_mci.h.

#define AT91_MCI_PDCPADV   (1 << 14) /* PDC Padding Value */

Definition at line 32 of file at91_mci.h.

#define AT91_MCI_PWSDIS   (1 << 3) /* Power Save Mode Disable */

Definition at line 23 of file at91_mci.h.

#define AT91_MCI_PWSDIV   (7 << 8) /* Power Saving Divider */

Definition at line 28 of file at91_mci.h.

#define AT91_MCI_PWSEN   (1 << 2) /* Power Save Mode Enable */

Definition at line 22 of file at91_mci.h.

#define AT91_MCI_RCRCE   (1 << 18) /* Response CRC Error */

Definition at line 103 of file at91_mci.h.

#define AT91_MCI_RDIRE   (1 << 17) /* Response Direction Error */

Definition at line 102 of file at91_mci.h.

#define AT91_MCI_RDPROOF   (1 << 11) /* Read Proof Enable [SAM926[03] only] */

Definition at line 29 of file at91_mci.h.

#define AT91_MCI_RENDE   (1 << 19) /* Response End Bit Error */

Definition at line 104 of file at91_mci.h.

#define AT91_MCI_RINDE   (1 << 16) /* Response Index Error */

Definition at line 101 of file at91_mci.h.

#define AT91_MCI_RSPR (   n)    (0x20 + ((n) * 4)) /* Response Registers 0-3 */

Definition at line 84 of file at91_mci.h.

#define AT91_MCI_RSPTYP   (3 << 6) /* Response Type */

Definition at line 56 of file at91_mci.h.

#define AT91_MCI_RSPTYP_136   (2 << 6)

Definition at line 59 of file at91_mci.h.

#define AT91_MCI_RSPTYP_48   (1 << 6)

Definition at line 58 of file at91_mci.h.

#define AT91_MCI_RSPTYP_NONE   (0 << 6)

Definition at line 57 of file at91_mci.h.

#define AT91_MCI_RTOE   (1 << 20) /* Response Time-out Error */

Definition at line 105 of file at91_mci.h.

#define AT91_MCI_RXBUFF   (1 << 14) /* RX Buffer Full */

Definition at line 99 of file at91_mci.h.

#define AT91_MCI_RXRDY   (1 << 1) /* Receiver Ready */

Definition at line 90 of file at91_mci.h.

#define AT91_MCI_SDCBUS   (1 << 7) /* 1-bit or 4-bit bus */

Definition at line 50 of file at91_mci.h.

#define AT91_MCI_SDCR   0x0c /* SD Card Register */

Definition at line 48 of file at91_mci.h.

#define AT91_MCI_SDCSEL   (3 << 0) /* SD Card Selector */

Definition at line 49 of file at91_mci.h.

#define AT91_MCI_SDIOIRQA   (1 << 8) /* SDIO Interrupt for Slot A */

Definition at line 97 of file at91_mci.h.

#define AT91_MCI_SDIOIRQB   (1 << 9) /* SDIO Interrupt for Slot B */

Definition at line 98 of file at91_mci.h.

#define AT91_MCI_SPCMD   (7 << 8) /* Special Command */

Definition at line 60 of file at91_mci.h.

#define AT91_MCI_SPCMD_ICMD   (4 << 8)

Definition at line 64 of file at91_mci.h.

#define AT91_MCI_SPCMD_INIT   (1 << 8)

Definition at line 62 of file at91_mci.h.

#define AT91_MCI_SPCMD_IRESP   (5 << 8)

Definition at line 65 of file at91_mci.h.

#define AT91_MCI_SPCMD_NONE   (0 << 8)

Definition at line 61 of file at91_mci.h.

#define AT91_MCI_SPCMD_SYNC   (2 << 8)

Definition at line 63 of file at91_mci.h.

#define AT91_MCI_SR   0x40 /* Status Register */

Definition at line 88 of file at91_mci.h.

#define AT91_MCI_SWRST   (1 << 7) /* Software Reset */

Definition at line 24 of file at91_mci.h.

#define AT91_MCI_TRCMD   (3 << 16) /* Transfer Command */

Definition at line 68 of file at91_mci.h.

#define AT91_MCI_TRCMD_NONE   (0 << 16)

Definition at line 69 of file at91_mci.h.

#define AT91_MCI_TRCMD_START   (1 << 16)

Definition at line 70 of file at91_mci.h.

#define AT91_MCI_TRCMD_STOP   (2 << 16)

Definition at line 71 of file at91_mci.h.

#define AT91_MCI_TRDIR   (1 << 18) /* Transfer Direction */

Definition at line 72 of file at91_mci.h.

#define AT91_MCI_TRTYP   (3 << 19) /* Transfer Type */

Definition at line 73 of file at91_mci.h.

#define AT91_MCI_TRTYP_BLOCK   (0 << 19)

Definition at line 74 of file at91_mci.h.

#define AT91_MCI_TRTYP_MULTIPLE   (1 << 19)

Definition at line 75 of file at91_mci.h.

#define AT91_MCI_TRTYP_SDIO_BLOCK   (5 << 19)

Definition at line 78 of file at91_mci.h.

#define AT91_MCI_TRTYP_SDIO_BYTE   (4 << 19)

Definition at line 77 of file at91_mci.h.

#define AT91_MCI_TRTYP_STREAM   (2 << 19)

Definition at line 76 of file at91_mci.h.

#define AT91_MCI_TXBUFE   (1 << 15) /* TX Buffer Empty */

Definition at line 100 of file at91_mci.h.

#define AT91_MCI_TXRDY   (1 << 2) /* Transmit Ready */

Definition at line 91 of file at91_mci.h.

#define AT91_MCI_UNRE   (1 << 31) /* Underrun */

Definition at line 109 of file at91_mci.h.

#define AT91_MCI_WRPROOF   (1 << 12) /* Write Proof Enable [SAM926[03] only] */

Definition at line 30 of file at91_mci.h.

#define AT91_MCR_RDR   0x30 /* Receive Data Register */

Definition at line 85 of file at91_mci.h.

#define AT91_MCR_TDR   0x34 /* Transmit Data Register */

Definition at line 86 of file at91_mci.h.