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at91rm9200_time.c
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1 /*
2  * linux/arch/arm/mach-at91/at91rm9200_time.c
3  *
4  * Copyright (C) 2003 SAN People
5  * Copyright (C) 2003 ATMEL
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20  */
21 
22 #include <linux/kernel.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/clockchips.h>
26 #include <linux/export.h>
27 
28 #include <asm/mach/time.h>
29 
30 #include <mach/at91_st.h>
31 
32 static unsigned long last_crtr;
33 static u32 irqmask;
34 static struct clock_event_device clkevt;
35 
36 #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
37 
38 /*
39  * The ST_CRTR is updated asynchronously to the master clock ... but
40  * the updates as seen by the CPU don't seem to be strictly monotonic.
41  * Waiting until we read the same value twice avoids glitching.
42  */
43 static inline unsigned long read_CRTR(void)
44 {
45  unsigned long x1, x2;
46 
48  do {
50  if (x1 == x2)
51  break;
52  x1 = x2;
53  } while (1);
54  return x1;
55 }
56 
57 /*
58  * IRQ handler for the timer.
59  */
60 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
61 {
62  u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
63 
64  /*
65  * irqs should be disabled here, but as the irq is shared they are only
66  * guaranteed to be off if the timer irq is registered first.
67  */
69 
70  /* simulate "oneshot" timer with alarm */
71  if (sr & AT91_ST_ALMS) {
72  clkevt.event_handler(&clkevt);
73  return IRQ_HANDLED;
74  }
75 
76  /* periodic mode should handle delayed ticks */
77  if (sr & AT91_ST_PITS) {
78  u32 crtr = read_CRTR();
79 
80  while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
81  last_crtr += RM9200_TIMER_LATCH;
82  clkevt.event_handler(&clkevt);
83  }
84  return IRQ_HANDLED;
85  }
86 
87  /* this irq is shared ... */
88  return IRQ_NONE;
89 }
90 
91 static struct irqaction at91rm9200_timer_irq = {
92  .name = "at91_tick",
94  .handler = at91rm9200_timer_interrupt
95 };
96 
97 static cycle_t read_clk32k(struct clocksource *cs)
98 {
99  return read_CRTR();
100 }
101 
102 static struct clocksource clk32k = {
103  .name = "32k_counter",
104  .rating = 150,
105  .read = read_clk32k,
106  .mask = CLOCKSOURCE_MASK(20),
108 };
109 
110 static void
111 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
112 {
113  /* Disable and flush pending timer interrupts */
114  at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
116 
117  last_crtr = read_CRTR();
118  switch (mode) {
119  case CLOCK_EVT_MODE_PERIODIC:
120  /* PIT for periodic irqs; fixed rate of 1/HZ */
121  irqmask = AT91_ST_PITS;
123  break;
124  case CLOCK_EVT_MODE_ONESHOT:
125  /* ALM for oneshot irqs, set by next_event()
126  * before 32 seconds have passed
127  */
128  irqmask = AT91_ST_ALMS;
129  at91_st_write(AT91_ST_RTAR, last_crtr);
130  break;
131  case CLOCK_EVT_MODE_SHUTDOWN:
132  case CLOCK_EVT_MODE_UNUSED:
133  case CLOCK_EVT_MODE_RESUME:
134  irqmask = 0;
135  break;
136  }
137  at91_st_write(AT91_ST_IER, irqmask);
138 }
139 
140 static int
141 clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
142 {
143  u32 alm;
144  int status = 0;
145 
146  BUG_ON(delta < 2);
147 
148  /* The alarm IRQ uses absolute time (now+delta), not the relative
149  * time (delta) in our calling convention. Like all clockevents
150  * using such "match" hardware, we have a race to defend against.
151  *
152  * Our defense here is to have set up the clockevent device so the
153  * delta is at least two. That way we never end up writing RTAR
154  * with the value then held in CRTR ... which would mean the match
155  * wouldn't trigger until 32 seconds later, after CRTR wraps.
156  */
157  alm = read_CRTR();
158 
159  /* Cancel any pending alarm; flush any pending IRQ */
162 
163  /* Schedule alarm by writing RTAR. */
164  alm += delta;
166 
167  return status;
168 }
169 
170 static struct clock_event_device clkevt = {
171  .name = "at91_tick",
172  .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
173  .shift = 32,
174  .rating = 150,
175  .set_next_event = clkevt32k_next_event,
176  .set_mode = clkevt32k_mode,
177 };
178 
180 EXPORT_SYMBOL_GPL(at91_st_base);
181 
183 {
184  at91_st_base = ioremap(addr, 256);
185  if (!at91_st_base)
186  panic("Impossible to ioremap ST\n");
187 }
188 
189 /*
190  * ST (system timer) module supports both clockevents and clocksource.
191  */
193 {
194  /* Disable all timer interrupts, and clear any pending ones */
196  AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
198 
199  /* Make IRQs happen for the system timer */
200  setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
201 
202  /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
203  * directly for the clocksource and all clockevents, after adjusting
204  * its prescaler from the 1 Hz default.
205  */
207 
208  /* Setup timer clockevent, with minimum of two ticks (important!!) */
209  clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
210  clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
211  clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
212  clkevt.cpumask = cpumask_of(0);
214 
215  /* register clocksource */
216  clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
217 }
218 
220  .init = at91rm9200_timer_init,
221 };
222