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at91sam9g45.c
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1 /*
2  * Chip-specific setup code for the AT91SAM9G45 family
3  *
4  * Copyright (C) 2009 Atmel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  */
12 
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9g45.h>
21 #include <mach/at91_aic.h>
22 #include <mach/at91_pmc.h>
23 #include <mach/cpu.h>
24 
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
28 #include "sam9_smc.h"
29 
30 /* --------------------------------------------------------------------
31  * Clocks
32  * -------------------------------------------------------------------- */
33 
34 /*
35  * The peripheral clocks.
36  */
37 static struct clk pioA_clk = {
38  .name = "pioA_clk",
39  .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
40  .type = CLK_TYPE_PERIPHERAL,
41 };
42 static struct clk pioB_clk = {
43  .name = "pioB_clk",
44  .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
45  .type = CLK_TYPE_PERIPHERAL,
46 };
47 static struct clk pioC_clk = {
48  .name = "pioC_clk",
49  .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
50  .type = CLK_TYPE_PERIPHERAL,
51 };
52 static struct clk pioDE_clk = {
53  .name = "pioDE_clk",
54  .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
55  .type = CLK_TYPE_PERIPHERAL,
56 };
57 static struct clk trng_clk = {
58  .name = "trng_clk",
59  .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
60  .type = CLK_TYPE_PERIPHERAL,
61 };
62 static struct clk usart0_clk = {
63  .name = "usart0_clk",
64  .pmc_mask = 1 << AT91SAM9G45_ID_US0,
65  .type = CLK_TYPE_PERIPHERAL,
66 };
67 static struct clk usart1_clk = {
68  .name = "usart1_clk",
69  .pmc_mask = 1 << AT91SAM9G45_ID_US1,
70  .type = CLK_TYPE_PERIPHERAL,
71 };
72 static struct clk usart2_clk = {
73  .name = "usart2_clk",
74  .pmc_mask = 1 << AT91SAM9G45_ID_US2,
75  .type = CLK_TYPE_PERIPHERAL,
76 };
77 static struct clk usart3_clk = {
78  .name = "usart3_clk",
79  .pmc_mask = 1 << AT91SAM9G45_ID_US3,
80  .type = CLK_TYPE_PERIPHERAL,
81 };
82 static struct clk mmc0_clk = {
83  .name = "mci0_clk",
84  .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
85  .type = CLK_TYPE_PERIPHERAL,
86 };
87 static struct clk twi0_clk = {
88  .name = "twi0_clk",
89  .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
90  .type = CLK_TYPE_PERIPHERAL,
91 };
92 static struct clk twi1_clk = {
93  .name = "twi1_clk",
94  .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
95  .type = CLK_TYPE_PERIPHERAL,
96 };
97 static struct clk spi0_clk = {
98  .name = "spi0_clk",
99  .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
100  .type = CLK_TYPE_PERIPHERAL,
101 };
102 static struct clk spi1_clk = {
103  .name = "spi1_clk",
104  .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
105  .type = CLK_TYPE_PERIPHERAL,
106 };
107 static struct clk ssc0_clk = {
108  .name = "ssc0_clk",
109  .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
110  .type = CLK_TYPE_PERIPHERAL,
111 };
112 static struct clk ssc1_clk = {
113  .name = "ssc1_clk",
114  .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
115  .type = CLK_TYPE_PERIPHERAL,
116 };
117 static struct clk tcb0_clk = {
118  .name = "tcb0_clk",
119  .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
120  .type = CLK_TYPE_PERIPHERAL,
121 };
122 static struct clk pwm_clk = {
123  .name = "pwm_clk",
124  .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
125  .type = CLK_TYPE_PERIPHERAL,
126 };
127 static struct clk tsc_clk = {
128  .name = "tsc_clk",
129  .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
130  .type = CLK_TYPE_PERIPHERAL,
131 };
132 static struct clk dma_clk = {
133  .name = "dma_clk",
134  .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
135  .type = CLK_TYPE_PERIPHERAL,
136 };
137 static struct clk uhphs_clk = {
138  .name = "uhphs_clk",
139  .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
140  .type = CLK_TYPE_PERIPHERAL,
141 };
142 static struct clk lcdc_clk = {
143  .name = "lcdc_clk",
144  .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
145  .type = CLK_TYPE_PERIPHERAL,
146 };
147 static struct clk ac97_clk = {
148  .name = "ac97_clk",
149  .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
150  .type = CLK_TYPE_PERIPHERAL,
151 };
152 static struct clk macb_clk = {
153  .name = "pclk",
154  .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
155  .type = CLK_TYPE_PERIPHERAL,
156 };
157 static struct clk isi_clk = {
158  .name = "isi_clk",
159  .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
160  .type = CLK_TYPE_PERIPHERAL,
161 };
162 static struct clk udphs_clk = {
163  .name = "udphs_clk",
164  .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
165  .type = CLK_TYPE_PERIPHERAL,
166 };
167 static struct clk mmc1_clk = {
168  .name = "mci1_clk",
169  .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
170  .type = CLK_TYPE_PERIPHERAL,
171 };
172 
173 /* Video decoder clock - Only for sam9m10/sam9m11 */
174 static struct clk vdec_clk = {
175  .name = "vdec_clk",
176  .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
177  .type = CLK_TYPE_PERIPHERAL,
178 };
179 
180 static struct clk adc_op_clk = {
181  .name = "adc_op_clk",
182  .type = CLK_TYPE_PERIPHERAL,
183  .rate_hz = 13200000,
184 };
185 
186 /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
187 static struct clk aestdessha_clk = {
188  .name = "aestdessha_clk",
189  .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
190  .type = CLK_TYPE_PERIPHERAL,
191 };
192 
193 static struct clk *periph_clocks[] __initdata = {
194  &pioA_clk,
195  &pioB_clk,
196  &pioC_clk,
197  &pioDE_clk,
198  &trng_clk,
199  &usart0_clk,
200  &usart1_clk,
201  &usart2_clk,
202  &usart3_clk,
203  &mmc0_clk,
204  &twi0_clk,
205  &twi1_clk,
206  &spi0_clk,
207  &spi1_clk,
208  &ssc0_clk,
209  &ssc1_clk,
210  &tcb0_clk,
211  &pwm_clk,
212  &tsc_clk,
213  &dma_clk,
214  &uhphs_clk,
215  &lcdc_clk,
216  &ac97_clk,
217  &macb_clk,
218  &isi_clk,
219  &udphs_clk,
220  &mmc1_clk,
221  &adc_op_clk,
222  &aestdessha_clk,
223  // irq0
224 };
225 
226 static struct clk_lookup periph_clocks_lookups[] = {
227  /* One additional fake clock for macb_hclk */
228  CLKDEV_CON_ID("hclk", &macb_clk),
229  /* One additional fake clock for ohci */
230  CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
231  CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
232  CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
233  CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
234  CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
235  CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
236  CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
237  CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
238  CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
239  CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
240  CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
241  CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
242  CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
243  CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
244  CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
245  CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
246  CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
247  CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
248  /* more usart lookup table for DT entries */
249  CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
250  CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
251  CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
252  CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
253  CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
254  /* more tc lookup table for DT entries */
255  CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
256  CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
257  CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
258  CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
259  CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
260  CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
261  /* fake hclk clock */
262  CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
263  CLKDEV_CON_ID("pioA", &pioA_clk),
264  CLKDEV_CON_ID("pioB", &pioB_clk),
265  CLKDEV_CON_ID("pioC", &pioC_clk),
266  CLKDEV_CON_ID("pioD", &pioDE_clk),
267  CLKDEV_CON_ID("pioE", &pioDE_clk),
268  /* Fake adc clock */
269  CLKDEV_CON_ID("adc_clk", &tsc_clk),
270 };
271 
272 static struct clk_lookup usart_clocks_lookups[] = {
273  CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
274  CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
275  CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
276  CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
277  CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
278 };
279 
280 /*
281  * The two programmable clocks.
282  * You must configure pin multiplexing to bring these signals out.
283  */
284 static struct clk pck0 = {
285  .name = "pck0",
286  .pmc_mask = AT91_PMC_PCK0,
287  .type = CLK_TYPE_PROGRAMMABLE,
288  .id = 0,
289 };
290 static struct clk pck1 = {
291  .name = "pck1",
292  .pmc_mask = AT91_PMC_PCK1,
293  .type = CLK_TYPE_PROGRAMMABLE,
294  .id = 1,
295 };
296 
297 static void __init at91sam9g45_register_clocks(void)
298 {
299  int i;
300 
301  for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
302  clk_register(periph_clocks[i]);
303 
304  clkdev_add_table(periph_clocks_lookups,
305  ARRAY_SIZE(periph_clocks_lookups));
306  clkdev_add_table(usart_clocks_lookups,
307  ARRAY_SIZE(usart_clocks_lookups));
308 
309  if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
310  clk_register(&vdec_clk);
311 
312  clk_register(&pck0);
313  clk_register(&pck1);
314 }
315 
316 /* --------------------------------------------------------------------
317  * GPIO
318  * -------------------------------------------------------------------- */
319 
320 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
321  {
322  .id = AT91SAM9G45_ID_PIOA,
323  .regbase = AT91SAM9G45_BASE_PIOA,
324  }, {
325  .id = AT91SAM9G45_ID_PIOB,
326  .regbase = AT91SAM9G45_BASE_PIOB,
327  }, {
328  .id = AT91SAM9G45_ID_PIOC,
329  .regbase = AT91SAM9G45_BASE_PIOC,
330  }, {
331  .id = AT91SAM9G45_ID_PIODE,
332  .regbase = AT91SAM9G45_BASE_PIOD,
333  }, {
334  .id = AT91SAM9G45_ID_PIODE,
335  .regbase = AT91SAM9G45_BASE_PIOE,
336  }
337 };
338 
339 /* --------------------------------------------------------------------
340  * AT91SAM9G45 processor initialization
341  * -------------------------------------------------------------------- */
342 
343 static void __init at91sam9g45_map_io(void)
344 {
345  at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
346  init_consistent_dma_size(SZ_4M);
347 }
348 
349 static void __init at91sam9g45_ioremap_registers(void)
350 {
351  at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
352  at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
353  at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
354  at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
355  at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
356  at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
357  at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
358 }
359 
360 static void __init at91sam9g45_initialize(void)
361 {
362  arm_pm_idle = at91sam9_idle;
363  arm_pm_restart = at91sam9g45_restart;
364  at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
365 
366  /* Register GPIO subsystem */
367  at91_gpio_init(at91sam9g45_gpio, 5);
368 }
369 
370 /* --------------------------------------------------------------------
371  * Interrupt initialization
372  * -------------------------------------------------------------------- */
373 
374 /*
375  * The default interrupt priority levels (0 = lowest, 7 = highest).
376  */
377 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
378  7, /* Advanced Interrupt Controller (FIQ) */
379  7, /* System Peripherals */
380  1, /* Parallel IO Controller A */
381  1, /* Parallel IO Controller B */
382  1, /* Parallel IO Controller C */
383  1, /* Parallel IO Controller D and E */
384  0,
385  5, /* USART 0 */
386  5, /* USART 1 */
387  5, /* USART 2 */
388  5, /* USART 3 */
389  0, /* Multimedia Card Interface 0 */
390  6, /* Two-Wire Interface 0 */
391  6, /* Two-Wire Interface 1 */
392  5, /* Serial Peripheral Interface 0 */
393  5, /* Serial Peripheral Interface 1 */
394  4, /* Serial Synchronous Controller 0 */
395  4, /* Serial Synchronous Controller 1 */
396  0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
397  0, /* Pulse Width Modulation Controller */
398  0, /* Touch Screen Controller */
399  0, /* DMA Controller */
400  2, /* USB Host High Speed port */
401  3, /* LDC Controller */
402  5, /* AC97 Controller */
403  3, /* Ethernet */
404  0, /* Image Sensor Interface */
405  2, /* USB Device High speed port */
406  0, /* AESTDESSHA Crypto HW Accelerators */
407  0, /* Multimedia Card Interface 1 */
408  0,
409  0, /* Advanced Interrupt Controller (IRQ0) */
410 };
411 
412 struct at91_init_soc __initdata at91sam9g45_soc = {
413  .map_io = at91sam9g45_map_io,
414  .default_irq_priority = at91sam9g45_default_irq_priority,
415  .ioremap_registers = at91sam9g45_ioremap_registers,
416  .register_clocks = at91sam9g45_register_clocks,
417  .init = at91sam9g45_initialize,
418 };
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