|
| #define | AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
| |
| #define | AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
| |
| #define | AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
| |
| #define | AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ |
| |
| #define | AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
| |
| #define | AT_VLAN_TO_TAG(_vlan, _tag) |
| |
| #define | AT_TAG_TO_VLAN(_tag, _vlan) |
| |
| #define | SPEED_0 0xffff |
| |
| #define | HALF_DUPLEX 1 |
| |
| #define | FULL_DUPLEX 2 |
| |
| #define | AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN) |
| |
| #define | MAX_JUMBO_FRAME_SIZE (6*1024) |
| |
| #define | AT_MAX_RECEIVE_QUEUE 4 |
| |
| #define | AT_DEF_RECEIVE_QUEUE 1 |
| |
| #define | AT_MAX_TRANSMIT_QUEUE 2 |
| |
| #define | AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL |
| |
| #define | AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL |
| |
| #define | AT_TX_WATCHDOG (5 * HZ) |
| |
| #define | AT_MAX_INT_WORK 5 |
| |
| #define | AT_TWSI_EEPROM_TIMEOUT 100 |
| |
| #define | AT_HW_MAX_IDLE_DELAY 10 |
| |
| #define | AT_SUSPEND_LINK_TIMEOUT 100 |
| |
| #define | AT_ASPM_L0S_TIMER 6 |
| |
| #define | AT_ASPM_L1_TIMER 12 |
| |
| #define | AT_LCKDET_TIMER 12 |
| |
| #define | ATL1C_PCIE_L0S_L1_DISABLE 0x01 |
| |
| #define | ATL1C_PCIE_PHY_RESET 0x02 |
| |
| #define | ATL1C_ASPM_L0s_ENABLE 0x0001 |
| |
| #define | ATL1C_ASPM_L1_ENABLE 0x0002 |
| |
| #define | AT_REGS_LEN (74 * sizeof(u32)) |
| |
| #define | AT_EEPROM_LEN 512 |
| |
| #define | ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) |
| |
| #define | ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) |
| |
| #define | ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) |
| |
| #define | ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) |
| |
| #define | TPD_L4HDR_OFFSET_MASK 0x00FF |
| |
| #define | TPD_L4HDR_OFFSET_SHIFT 0 |
| |
| #define | TPD_TCPHDR_OFFSET_MASK 0x00FF |
| |
| #define | TPD_TCPHDR_OFFSET_SHIFT 0 |
| |
| #define | TPD_PLOADOFFSET_MASK 0x00FF |
| |
| #define | TPD_PLOADOFFSET_SHIFT 0 |
| |
| #define | TPD_CCSUM_EN_MASK 0x0001 |
| |
| #define | TPD_CCSUM_EN_SHIFT 8 |
| |
| #define | TPD_IP_CSUM_MASK 0x0001 |
| |
| #define | TPD_IP_CSUM_SHIFT 9 |
| |
| #define | TPD_TCP_CSUM_MASK 0x0001 |
| |
| #define | TPD_TCP_CSUM_SHIFT 10 |
| |
| #define | TPD_UDP_CSUM_MASK 0x0001 |
| |
| #define | TPD_UDP_CSUM_SHIFT 11 |
| |
| #define | TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */ |
| |
| #define | TPD_LSO_EN_SHIFT 12 |
| |
| #define | TPD_LSO_VER_MASK 0x0001 |
| |
| #define | TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */ |
| |
| #define | TPD_CON_VTAG_MASK 0x0001 |
| |
| #define | TPD_CON_VTAG_SHIFT 14 |
| |
| #define | TPD_INS_VTAG_MASK 0x0001 |
| |
| #define | TPD_INS_VTAG_SHIFT 15 |
| |
| #define | TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */ |
| |
| #define | TPD_IPV4_PACKET_SHIFT 16 |
| |
| #define | TPD_ETH_TYPE_MASK 0x0001 |
| |
| #define | TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */ |
| |
| #define | TPD_CCSUM_OFFSET_MASK 0x00FF |
| |
| #define | TPD_CCSUM_OFFSET_SHIFT 18 |
| |
| #define | TPD_CCSUM_EPAD_MASK 0x0001 |
| |
| #define | TPD_CCSUM_EPAD_SHIFT 30 |
| |
| #define | TPD_MSS_MASK 0x1FFF |
| |
| #define | TPD_MSS_SHIFT 18 |
| |
| #define | TPD_EOP_MASK 0x0001 |
| |
| #define | TPD_EOP_SHIFT 31 |
| |
| #define | RRS_RX_CSUM_MASK 0xFFFF |
| |
| #define | RRS_RX_CSUM_SHIFT 0 |
| |
| #define | RRS_RX_RFD_CNT_MASK 0x000F |
| |
| #define | RRS_RX_RFD_CNT_SHIFT 16 |
| |
| #define | RRS_RX_RFD_INDEX_MASK 0x0FFF |
| |
| #define | RRS_RX_RFD_INDEX_SHIFT 20 |
| |
| #define | RRS_HEAD_LEN_MASK 0x00FF |
| |
| #define | RRS_HEAD_LEN_SHIFT 0 |
| |
| #define | RRS_HDS_TYPE_MASK 0x0003 |
| |
| #define | RRS_HDS_TYPE_SHIFT 8 |
| |
| #define | RRS_CPU_NUM_MASK 0x0003 |
| |
| #define | RRS_CPU_NUM_SHIFT 10 |
| |
| #define | RRS_HASH_FLG_MASK 0x000F |
| |
| #define | RRS_HASH_FLG_SHIFT 12 |
| |
| #define | RRS_HDS_TYPE_HEAD 1 |
| |
| #define | RRS_HDS_TYPE_DATA 2 |
| |
| #define | RRS_IS_NO_HDS_TYPE(flag) ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0) |
| |
| #define | RRS_IS_HDS_HEAD(flag) |
| |
| #define | RRS_IS_HDS_DATA(flag) |
| |
| #define | RRS_PKT_SIZE_MASK 0x3FFF |
| |
| #define | RRS_PKT_SIZE_SHIFT 0 |
| |
| #define | RRS_ERR_L4_CSUM_MASK 0x0001 |
| |
| #define | RRS_ERR_L4_CSUM_SHIFT 14 |
| |
| #define | RRS_ERR_IP_CSUM_MASK 0x0001 |
| |
| #define | RRS_ERR_IP_CSUM_SHIFT 15 |
| |
| #define | RRS_VLAN_INS_MASK 0x0001 |
| |
| #define | RRS_VLAN_INS_SHIFT 16 |
| |
| #define | RRS_PROT_ID_MASK 0x0007 |
| |
| #define | RRS_PROT_ID_SHIFT 17 |
| |
| #define | RRS_RX_ERR_SUM_MASK 0x0001 |
| |
| #define | RRS_RX_ERR_SUM_SHIFT 20 |
| |
| #define | RRS_RX_ERR_CRC_MASK 0x0001 |
| |
| #define | RRS_RX_ERR_CRC_SHIFT 21 |
| |
| #define | RRS_RX_ERR_FAE_MASK 0x0001 |
| |
| #define | RRS_RX_ERR_FAE_SHIFT 22 |
| |
| #define | RRS_RX_ERR_TRUNC_MASK 0x0001 |
| |
| #define | RRS_RX_ERR_TRUNC_SHIFT 23 |
| |
| #define | RRS_RX_ERR_RUNC_MASK 0x0001 |
| |
| #define | RRS_RX_ERR_RUNC_SHIFT 24 |
| |
| #define | RRS_RX_ERR_ICMP_MASK 0x0001 |
| |
| #define | RRS_RX_ERR_ICMP_SHIFT 25 |
| |
| #define | RRS_PACKET_BCAST_MASK 0x0001 |
| |
| #define | RRS_PACKET_BCAST_SHIFT 26 |
| |
| #define | RRS_PACKET_MCAST_MASK 0x0001 |
| |
| #define | RRS_PACKET_MCAST_SHIFT 27 |
| |
| #define | RRS_PACKET_TYPE_MASK 0x0001 |
| |
| #define | RRS_PACKET_TYPE_SHIFT 28 |
| |
| #define | RRS_FIFO_FULL_MASK 0x0001 |
| |
| #define | RRS_FIFO_FULL_SHIFT 29 |
| |
| #define | RRS_802_3_LEN_ERR_MASK 0x0001 |
| |
| #define | RRS_802_3_LEN_ERR_SHIFT 30 |
| |
| #define | RRS_RXD_UPDATED_MASK 0x0001 |
| |
| #define | RRS_RXD_UPDATED_SHIFT 31 |
| |
| #define | RRS_ERR_L4_CSUM 0x00004000 |
| |
| #define | RRS_ERR_IP_CSUM 0x00008000 |
| |
| #define | RRS_VLAN_INS 0x00010000 |
| |
| #define | RRS_RX_ERR_SUM 0x00100000 |
| |
| #define | RRS_RX_ERR_CRC 0x00200000 |
| |
| #define | RRS_802_3_LEN_ERR 0x40000000 |
| |
| #define | RRS_RXD_UPDATED 0x80000000 |
| |
| #define | RRS_PACKET_TYPE_802_3 1 |
| |
| #define | RRS_PACKET_TYPE_ETH 0 |
| |
| #define | RRS_PACKET_IS_ETH(word) |
| |
| #define | RRS_RXD_IS_VALID(word) ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1) |
| |
| #define | RRS_PACKET_PROT_IS_IPV4_ONLY(word) ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1) |
| |
| #define | RRS_PACKET_PROT_IS_IPV6_ONLY(word) ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6) |
| |
| #define | MEDIA_TYPE_AUTO_SENSOR 0 |
| |
| #define | MEDIA_TYPE_100M_FULL 1 |
| |
| #define | MEDIA_TYPE_100M_HALF 2 |
| |
| #define | MEDIA_TYPE_10M_FULL 3 |
| |
| #define | MEDIA_TYPE_10M_HALF 4 |
| |
| #define | ATL1C_INTR_CLEAR_ON_READ 0x0001 |
| |
| #define | ATL1C_INTR_MODRT_ENABLE 0x0002 |
| |
| #define | ATL1C_CMB_ENABLE 0x0004 |
| |
| #define | ATL1C_SMB_ENABLE 0x0010 |
| |
| #define | ATL1C_TXQ_MODE_ENHANCE 0x0020 |
| |
| #define | ATL1C_RX_IPV6_CHKSUM 0x0040 |
| |
| #define | ATL1C_ASPM_L0S_SUPPORT 0x0080 |
| |
| #define | ATL1C_ASPM_L1_SUPPORT 0x0100 |
| |
| #define | ATL1C_ASPM_CTRL_MON 0x0200 |
| |
| #define | ATL1C_HIB_DISABLE 0x0400 |
| |
| #define | ATL1C_APS_MODE_ENABLE 0x0800 |
| |
| #define | ATL1C_LINK_EXT_SYNC 0x1000 |
| |
| #define | ATL1C_CLK_GATING_EN 0x2000 |
| |
| #define | ATL1C_FPGA_VERSION 0x8000 |
| |
| #define | ATL1C_LINK_CAP_1000M 0x0001 |
| |
| #define | ATL1C_BUFFER_FREE 0x0001 |
| |
| #define | ATL1C_BUFFER_BUSY 0x0002 |
| |
| #define | ATL1C_BUFFER_STATE_MASK 0x0003 |
| |
| #define | ATL1C_PCIMAP_SINGLE 0x0004 |
| |
| #define | ATL1C_PCIMAP_PAGE 0x0008 |
| |
| #define | ATL1C_PCIMAP_TYPE_MASK 0x000C |
| |
| #define | ATL1C_PCIMAP_TODEVICE 0x0010 |
| |
| #define | ATL1C_PCIMAP_FROMDEVICE 0x0020 |
| |
| #define | ATL1C_PCIMAP_DIRECTION_MASK 0x0030 |
| |
| #define | ATL1C_SET_BUFFER_STATE(buff, state) |
| |
| #define | ATL1C_SET_PCIMAP_TYPE(buff, type, direction) |
| |
| #define | __AT_TESTING 0x0001 |
| |
| #define | __AT_RESETTING 0x0002 |
| |
| #define | __AT_DOWN 0x0003 |
| |
| #define | ATL1C_WORK_EVENT_RESET 0 |
| |
| #define | ATL1C_WORK_EVENT_LINK_CHANGE 1 |
| |
| #define | AT_WRITE_REG(a, reg, value) |
| |
| #define | AT_WRITE_FLUSH(a) |
| |
| #define | AT_READ_REG(a, reg, pdata) |
| |
| #define | AT_WRITE_REGB(a, reg, value) |
| |
| #define | AT_READ_REGB(a, reg) |
| |
| #define | AT_WRITE_REGW(a, reg, value) |
| |
| #define | AT_READ_REGW(a, reg, pdata) |
| |
| #define | AT_WRITE_REG_ARRAY(a, reg, offset, value) |
| |
| #define | AT_READ_REG_ARRAY(a, reg, offset) |
| |
1.8.2