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clk-imx51-imx53.c
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1 /*
2  * Copyright (C) 2011 Sascha Hauer, Pengutronix <[email protected]>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  */
9 #include <linux/mm.h>
10 #include <linux/delay.h>
11 #include <linux/clk.h>
12 #include <linux/io.h>
13 #include <linux/clkdev.h>
14 #include <linux/of.h>
15 #include <linux/err.h>
16 
17 #include <mach/hardware.h>
18 #include <mach/common.h>
19 
20 #include "crm-regs-imx5.h"
21 #include "clk.h"
22 
23 /* Low-power Audio Playback Mode clock */
24 static const char *lp_apm_sel[] = { "osc", };
25 
26 /* This is used multiple times */
27 static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
28 static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
29 static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
30 static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
31 static const char *per_root_sel[] = { "per_podf", "ipg", };
32 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
33 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
34 static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
35 static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
36 static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
37 static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
38 static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
39 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
40 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
41 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
42 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
43 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
44 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
45 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
46 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
47 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
48 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
49 static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
50 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
51 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
52 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
53 
54 enum imx5_clks {
55  dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
56  uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
57  emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
58  usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
59  tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
60  uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
61  gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
62  gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
63  esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
64  ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
65  ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
66  ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
67  vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
68  uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
69  esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
70  mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
71  ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
72  ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
73  periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
74  tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
75  esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
76  usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
77  pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
78  ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
79  usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
80  ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
81  ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
82  ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
83  ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
84  ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
85  epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
86  can_sel, can1_serial_gate, can1_ipg_gate,
87  clk_max
88 };
89 
90 static struct clk *clk[clk_max];
91 
92 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
93  unsigned long rate_osc, unsigned long rate_ckih1,
94  unsigned long rate_ckih2)
95 {
96  int i;
97 
98  clk[dummy] = imx_clk_fixed("dummy", 0);
99  clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
100  clk[osc] = imx_clk_fixed("osc", rate_osc);
101  clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
102  clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
103 
104  clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
105  lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
106  clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
107  periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
108  clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
109  main_bus_sel, ARRAY_SIZE(main_bus_sel));
110  clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
111  per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
112  clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
113  clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
114  clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
115  clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
116  per_root_sel, ARRAY_SIZE(per_root_sel));
117  clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
118  clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
119  clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
120  clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
121  clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
122  clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
123  clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
124  clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
125  clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
126  clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
127  clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
128  clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
129  standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
130  clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
131  clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
132 
133  clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
134  standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
135  clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
136  standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
137  clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
138  clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
139  clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
140  clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
141  clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
142  clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
143 
144  clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
145  emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
146  clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
147  clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
148  clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
149  standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
150  clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
151  clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
152  clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
153  standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
154  clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
155  clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
156  clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
157  clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
158  clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
159  usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
160  clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
161  clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
162  clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
163  clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
164  clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
165  clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
166  clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
167  clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
168  clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
169  clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
170  clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
171  clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
172  clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
173  clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
174  clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
175  clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
176  clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
177  clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
178  clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
179  clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
180  clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
181  clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
182  clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
183  clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
184  clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
185  clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
186  clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
187  clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
188  clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
189  clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
190  clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
191  clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
192  clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
193  clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
194  clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
195  clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
196  clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
197  clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
198  clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
199  clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
200  clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
201  clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
202  clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
203  clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
204  clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
205  clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
206  clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
207  clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
208  clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
209  clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
210 
211  clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
212  clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
213  clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
214  clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
215  clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
216  clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
217  clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
218  clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
219  clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
220  clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
221  clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
222  clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
223  clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
224  clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
225  clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
226  clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
227  clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
228  clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
229  clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
230  clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
231  clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
232  clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
233  clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
234  clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
235  clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
236 
237  for (i = 0; i < ARRAY_SIZE(clk); i++)
238  if (IS_ERR(clk[i]))
239  pr_err("i.MX5 clk %d: register failed with %ld\n",
240  i, PTR_ERR(clk[i]));
241 
242  clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
243  clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
244  clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
245  clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
246  clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
247  clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
248  clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
249  clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
250  clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
251  clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
252  clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
253  clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
254  clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
255  clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
256  clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
257  clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
258  clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
259  clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
260  clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
261  clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
262  clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
263  clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
264  clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
265  clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
266  clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
267  clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
268  clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
269  clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
270  clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
271  clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
272  clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
273  clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
274  clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
275  clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
276  clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
277  clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
278  clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
279  clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
280  clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
281  clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
282  clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
283  clk_register_clkdev(clk[iim_gate], "iim", NULL);
284  clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
285  clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
286  clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
287  clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
288  clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
289  clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
290  clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
291  clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
292  clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
293  clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
294 
295  /* Set SDHC parents to be PLL2 */
296  clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
297  clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
298 
299  /* move usb phy clk to 24MHz */
300  clk_set_parent(clk[usb_phy_sel], clk[osc]);
301 
302  clk_prepare_enable(clk[gpc_dvfs]);
303  clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
304  clk_prepare_enable(clk[aips_tz1]);
305  clk_prepare_enable(clk[aips_tz2]); /* fec */
306  clk_prepare_enable(clk[spba]);
307  clk_prepare_enable(clk[emi_fast_gate]); /* fec */
308  clk_prepare_enable(clk[emi_slow_gate]); /* eim */
309  clk_prepare_enable(clk[tmax1]);
310  clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
311  clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
312 }
313 
314 int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
315  unsigned long rate_ckih1, unsigned long rate_ckih2)
316 {
317  int i;
318 
319  clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
320  clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
321  clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
322  clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
323  mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
324  clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
325  mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
326  clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
327  mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
328  clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
329  clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
330  clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
331  clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
332  clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
333  clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
334  clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
335  clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
336  clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
337  clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
338  clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
339  clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
340 
341  for (i = 0; i < ARRAY_SIZE(clk); i++)
342  if (IS_ERR(clk[i]))
343  pr_err("i.MX51 clk %d: register failed with %ld\n",
344  i, PTR_ERR(clk[i]));
345 
346  mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
347 
348  clk_register_clkdev(clk[hsi2c_gate], NULL, "imx-i2c.2");
349  clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
350  clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
351  clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
352  clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
353  clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
354  clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
355  clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
356  clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
357  clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
358  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
359  clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
360  clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
361  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
362  clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
363  clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
364  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
365  clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
366  clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
367  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
368  clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
369  clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
370  clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
371  clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
372  clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
373 
374  /* set the usboh3 parent to pll2_sw */
375  clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
376 
377  /* set SDHC root clock to 166.25MHZ*/
378  clk_set_rate(clk[esdhc_a_podf], 166250000);
379  clk_set_rate(clk[esdhc_b_podf], 166250000);
380 
381  /* System timer */
382  mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
383 
384  clk_prepare_enable(clk[iim_gate]);
385  imx_print_silicon_rev("i.MX51", mx51_revision());
386  clk_disable_unprepare(clk[iim_gate]);
387 
388  return 0;
389 }
390 
391 int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
392  unsigned long rate_ckih1, unsigned long rate_ckih2)
393 {
394  int i;
395  unsigned long r;
396 
397  clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
398  clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
399  clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
400  clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
401 
402  clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
403  mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
404  clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
405  clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
406  clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
407  clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
408  mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
409  clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
410  clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
411  clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
412  clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
413  clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
414  mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
415  clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
416  mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
417  clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
418  mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
419  clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
420  clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
421  clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
422  clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
423  clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
424  clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
425  clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
426  clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
427  clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
428  mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
429  clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
430  clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
431  clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
432  clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
433  clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
434 
435  for (i = 0; i < ARRAY_SIZE(clk); i++)
436  if (IS_ERR(clk[i]))
437  pr_err("i.MX53 clk %d: register failed with %ld\n",
438  i, PTR_ERR(clk[i]));
439 
440  mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
441 
442  clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
443  clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
444  clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
445  clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
446  clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
447  clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
448  clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
449  clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
450  clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
451  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
452  clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
453  clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
454  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
455  clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
456  clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
457  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
458  clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
459  clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
460  clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
461  clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
462  clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
463  clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
464  clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
465  clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
466  clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
467  clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
468  clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
469  clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
470 
471  /* set SDHC root clock to 200MHZ*/
472  clk_set_rate(clk[esdhc_a_podf], 200000000);
473  clk_set_rate(clk[esdhc_b_podf], 200000000);
474 
475  /* System timer */
476  mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
477 
478  clk_prepare_enable(clk[iim_gate]);
479  imx_print_silicon_rev("i.MX53", mx53_revision());
480  clk_disable_unprepare(clk[iim_gate]);
481 
482  r = clk_round_rate(clk[usboh3_per_gate], 54000000);
483  clk_set_rate(clk[usboh3_per_gate], r);
484 
485  return 0;
486 }
487 
488 #ifdef CONFIG_OF
489 static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
490  unsigned long *ckih1, unsigned long *ckih2)
491 {
492  struct device_node *np;
493 
494  /* retrieve the freqency of fixed clocks from device tree */
495  for_each_compatible_node(np, NULL, "fixed-clock") {
496  u32 rate;
497  if (of_property_read_u32(np, "clock-frequency", &rate))
498  continue;
499 
500  if (of_device_is_compatible(np, "fsl,imx-ckil"))
501  *ckil = rate;
502  else if (of_device_is_compatible(np, "fsl,imx-osc"))
503  *osc = rate;
504  else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
505  *ckih1 = rate;
506  else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
507  *ckih2 = rate;
508  }
509 }
510 
511 int __init mx51_clocks_init_dt(void)
512 {
513  unsigned long ckil, osc, ckih1, ckih2;
514 
515  clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
516  return mx51_clocks_init(ckil, osc, ckih1, ckih2);
517 }
518 
519 int __init mx53_clocks_init_dt(void)
520 {
521  unsigned long ckil, osc, ckih1, ckih2;
522 
523  clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
524  return mx53_clocks_init(ckil, osc, ckih1, ckih2);
525 }
526 #endif
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