Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
clock-exynos4.c
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3  * http://www.samsung.com
4  *
5  * EXYNOS4 - Clock support
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10 */
11 
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/syscore_ops.h>
16 
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23 #include <plat/pm.h>
24 
25 #include <mach/map.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
28 
29 #include "common.h"
30 #include "clock-exynos4.h"
31 
32 #ifdef CONFIG_PM_SLEEP
33 static struct sleep_save exynos4_clock_save[] = {
34  SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35  SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36  SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37  SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38  SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39  SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40  SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41  SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42  SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43  SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44  SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45  SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46  SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47  SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48  SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49  SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50  SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51  SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52  SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53  SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54  SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55  SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56  SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57  SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58  SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59  SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60  SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61  SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62  SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63  SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64  SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65  SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74  SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75  SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76  SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77  SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78  SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79  SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80  SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81  SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82  SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83  SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84  SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85  SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86  SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87  SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88  SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89  SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90  SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91  SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92  SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93  SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94  SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95 };
96 #endif
97 
98 static struct clk exynos4_clk_sclk_hdmi27m = {
99  .name = "sclk_hdmi27m",
100  .rate = 27000000,
101 };
102 
103 static struct clk exynos4_clk_sclk_hdmiphy = {
104  .name = "sclk_hdmiphy",
105 };
106 
107 static struct clk exynos4_clk_sclk_usbphy0 = {
108  .name = "sclk_usbphy0",
109  .rate = 27000000,
110 };
111 
112 static struct clk exynos4_clk_sclk_usbphy1 = {
113  .name = "sclk_usbphy1",
114 };
115 
116 static struct clk dummy_apb_pclk = {
117  .name = "apb_pclk",
118  .id = -1,
119 };
120 
121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122 {
123  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124 }
125 
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127 {
128  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129 }
130 
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132 {
133  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134 }
135 
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137 {
138  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139 }
140 
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142 {
143  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144 }
145 
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147 {
148  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149 }
150 
151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152 {
153  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154 }
155 
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157 {
158  return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159 }
160 
161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162 {
163  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164 }
165 
166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167 {
168  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169 }
170 
171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172 {
173  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174 }
175 
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177 {
178  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179 }
180 
181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182 {
183  return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184 }
185 
186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187 {
188  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189 }
190 
191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192 {
193  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194 }
195 
196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197 {
198  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199 }
200 
201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
202 {
203  return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
204 }
205 
206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
207 {
208  return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
209 }
210 
211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
212 {
213  return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
214 }
215 
216 /* Core list of CMU_CPU side */
217 
218 static struct clksrc_clk exynos4_clk_mout_apll = {
219  .clk = {
220  .name = "mout_apll",
221  },
222  .sources = &clk_src_apll,
223  .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
224 };
225 
226 static struct clksrc_clk exynos4_clk_sclk_apll = {
227  .clk = {
228  .name = "sclk_apll",
229  .parent = &exynos4_clk_mout_apll.clk,
230  },
231  .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
232 };
233 
234 static struct clksrc_clk exynos4_clk_mout_epll = {
235  .clk = {
236  .name = "mout_epll",
237  },
238  .sources = &clk_src_epll,
239  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
240 };
241 
242 struct clksrc_clk exynos4_clk_mout_mpll = {
243  .clk = {
244  .name = "mout_mpll",
245  },
246  .sources = &clk_src_mpll,
247 
248  /* reg_src will be added in each SoCs' clock */
249 };
250 
251 static struct clk *exynos4_clkset_moutcore_list[] = {
252  [0] = &exynos4_clk_mout_apll.clk,
253  [1] = &exynos4_clk_mout_mpll.clk,
254 };
255 
256 static struct clksrc_sources exynos4_clkset_moutcore = {
257  .sources = exynos4_clkset_moutcore_list,
258  .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
259 };
260 
261 static struct clksrc_clk exynos4_clk_moutcore = {
262  .clk = {
263  .name = "moutcore",
264  },
265  .sources = &exynos4_clkset_moutcore,
266  .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
267 };
268 
269 static struct clksrc_clk exynos4_clk_coreclk = {
270  .clk = {
271  .name = "core_clk",
272  .parent = &exynos4_clk_moutcore.clk,
273  },
274  .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
275 };
276 
277 static struct clksrc_clk exynos4_clk_armclk = {
278  .clk = {
279  .name = "armclk",
280  .parent = &exynos4_clk_coreclk.clk,
281  },
282 };
283 
284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
285  .clk = {
286  .name = "aclk_corem0",
287  .parent = &exynos4_clk_coreclk.clk,
288  },
289  .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
290 };
291 
292 static struct clksrc_clk exynos4_clk_aclk_cores = {
293  .clk = {
294  .name = "aclk_cores",
295  .parent = &exynos4_clk_coreclk.clk,
296  },
297  .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
298 };
299 
300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
301  .clk = {
302  .name = "aclk_corem1",
303  .parent = &exynos4_clk_coreclk.clk,
304  },
305  .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
306 };
307 
308 static struct clksrc_clk exynos4_clk_periphclk = {
309  .clk = {
310  .name = "periphclk",
311  .parent = &exynos4_clk_coreclk.clk,
312  },
313  .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
314 };
315 
316 /* Core list of CMU_CORE side */
317 
318 static struct clk *exynos4_clkset_corebus_list[] = {
319  [0] = &exynos4_clk_mout_mpll.clk,
320  [1] = &exynos4_clk_sclk_apll.clk,
321 };
322 
323 struct clksrc_sources exynos4_clkset_mout_corebus = {
324  .sources = exynos4_clkset_corebus_list,
325  .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
326 };
327 
328 static struct clksrc_clk exynos4_clk_mout_corebus = {
329  .clk = {
330  .name = "mout_corebus",
331  },
332  .sources = &exynos4_clkset_mout_corebus,
333  .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
334 };
335 
336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
337  .clk = {
338  .name = "sclk_dmc",
339  .parent = &exynos4_clk_mout_corebus.clk,
340  },
341  .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
342 };
343 
344 static struct clksrc_clk exynos4_clk_aclk_cored = {
345  .clk = {
346  .name = "aclk_cored",
347  .parent = &exynos4_clk_sclk_dmc.clk,
348  },
349  .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
350 };
351 
352 static struct clksrc_clk exynos4_clk_aclk_corep = {
353  .clk = {
354  .name = "aclk_corep",
355  .parent = &exynos4_clk_aclk_cored.clk,
356  },
357  .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
358 };
359 
360 static struct clksrc_clk exynos4_clk_aclk_acp = {
361  .clk = {
362  .name = "aclk_acp",
363  .parent = &exynos4_clk_mout_corebus.clk,
364  },
365  .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
366 };
367 
368 static struct clksrc_clk exynos4_clk_pclk_acp = {
369  .clk = {
370  .name = "pclk_acp",
371  .parent = &exynos4_clk_aclk_acp.clk,
372  },
373  .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
374 };
375 
376 /* Core list of CMU_TOP side */
377 
378 struct clk *exynos4_clkset_aclk_top_list[] = {
379  [0] = &exynos4_clk_mout_mpll.clk,
380  [1] = &exynos4_clk_sclk_apll.clk,
381 };
382 
383 static struct clksrc_sources exynos4_clkset_aclk = {
384  .sources = exynos4_clkset_aclk_top_list,
385  .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
386 };
387 
388 static struct clksrc_clk exynos4_clk_aclk_200 = {
389  .clk = {
390  .name = "aclk_200",
391  },
392  .sources = &exynos4_clkset_aclk,
393  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
394  .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
395 };
396 
397 static struct clksrc_clk exynos4_clk_aclk_100 = {
398  .clk = {
399  .name = "aclk_100",
400  },
401  .sources = &exynos4_clkset_aclk,
402  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
403  .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
404 };
405 
406 static struct clksrc_clk exynos4_clk_aclk_160 = {
407  .clk = {
408  .name = "aclk_160",
409  },
410  .sources = &exynos4_clkset_aclk,
411  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
412  .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
413 };
414 
415 struct clksrc_clk exynos4_clk_aclk_133 = {
416  .clk = {
417  .name = "aclk_133",
418  },
419  .sources = &exynos4_clkset_aclk,
420  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
421  .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
422 };
423 
424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
425  [0] = &clk_fin_vpll,
426  [1] = &exynos4_clk_sclk_hdmi27m,
427 };
428 
429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
430  .sources = exynos4_clkset_vpllsrc_list,
431  .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
432 };
433 
434 static struct clksrc_clk exynos4_clk_vpllsrc = {
435  .clk = {
436  .name = "vpll_src",
437  .enable = exynos4_clksrc_mask_top_ctrl,
438  .ctrlbit = (1 << 0),
439  },
440  .sources = &exynos4_clkset_vpllsrc,
441  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
442 };
443 
444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
445  [0] = &exynos4_clk_vpllsrc.clk,
446  [1] = &clk_fout_vpll,
447 };
448 
449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
450  .sources = exynos4_clkset_sclk_vpll_list,
451  .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
452 };
453 
454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
455  .clk = {
456  .name = "sclk_vpll",
457  },
458  .sources = &exynos4_clkset_sclk_vpll,
459  .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
460 };
461 
462 static struct clk exynos4_init_clocks_off[] = {
463  {
464  .name = "timers",
465  .parent = &exynos4_clk_aclk_100.clk,
466  .enable = exynos4_clk_ip_peril_ctrl,
467  .ctrlbit = (1<<24),
468  }, {
469  .name = "csis",
470  .devname = "s5p-mipi-csis.0",
471  .enable = exynos4_clk_ip_cam_ctrl,
472  .ctrlbit = (1 << 4),
473  }, {
474  .name = "csis",
475  .devname = "s5p-mipi-csis.1",
476  .enable = exynos4_clk_ip_cam_ctrl,
477  .ctrlbit = (1 << 5),
478  }, {
479  .name = "jpeg",
480  .id = 0,
481  .enable = exynos4_clk_ip_cam_ctrl,
482  .ctrlbit = (1 << 6),
483  }, {
484  .name = "fimc",
485  .devname = "exynos4-fimc.0",
486  .enable = exynos4_clk_ip_cam_ctrl,
487  .ctrlbit = (1 << 0),
488  }, {
489  .name = "fimc",
490  .devname = "exynos4-fimc.1",
491  .enable = exynos4_clk_ip_cam_ctrl,
492  .ctrlbit = (1 << 1),
493  }, {
494  .name = "fimc",
495  .devname = "exynos4-fimc.2",
496  .enable = exynos4_clk_ip_cam_ctrl,
497  .ctrlbit = (1 << 2),
498  }, {
499  .name = "fimc",
500  .devname = "exynos4-fimc.3",
501  .enable = exynos4_clk_ip_cam_ctrl,
502  .ctrlbit = (1 << 3),
503  }, {
504  .name = "tsi",
505  .enable = exynos4_clk_ip_fsys_ctrl,
506  .ctrlbit = (1 << 4),
507  }, {
508  .name = "hsmmc",
509  .devname = "exynos4-sdhci.0",
510  .parent = &exynos4_clk_aclk_133.clk,
511  .enable = exynos4_clk_ip_fsys_ctrl,
512  .ctrlbit = (1 << 5),
513  }, {
514  .name = "hsmmc",
515  .devname = "exynos4-sdhci.1",
516  .parent = &exynos4_clk_aclk_133.clk,
517  .enable = exynos4_clk_ip_fsys_ctrl,
518  .ctrlbit = (1 << 6),
519  }, {
520  .name = "hsmmc",
521  .devname = "exynos4-sdhci.2",
522  .parent = &exynos4_clk_aclk_133.clk,
523  .enable = exynos4_clk_ip_fsys_ctrl,
524  .ctrlbit = (1 << 7),
525  }, {
526  .name = "hsmmc",
527  .devname = "exynos4-sdhci.3",
528  .parent = &exynos4_clk_aclk_133.clk,
529  .enable = exynos4_clk_ip_fsys_ctrl,
530  .ctrlbit = (1 << 8),
531  }, {
532  .name = "dwmmc",
533  .parent = &exynos4_clk_aclk_133.clk,
534  .enable = exynos4_clk_ip_fsys_ctrl,
535  .ctrlbit = (1 << 9),
536  }, {
537  .name = "onenand",
538  .enable = exynos4_clk_ip_fsys_ctrl,
539  .ctrlbit = (1 << 15),
540  }, {
541  .name = "nfcon",
542  .enable = exynos4_clk_ip_fsys_ctrl,
543  .ctrlbit = (1 << 16),
544  }, {
545  .name = "dac",
546  .devname = "s5p-sdo",
547  .enable = exynos4_clk_ip_tv_ctrl,
548  .ctrlbit = (1 << 2),
549  }, {
550  .name = "mixer",
551  .devname = "s5p-mixer",
552  .enable = exynos4_clk_ip_tv_ctrl,
553  .ctrlbit = (1 << 1),
554  }, {
555  .name = "vp",
556  .devname = "s5p-mixer",
557  .enable = exynos4_clk_ip_tv_ctrl,
558  .ctrlbit = (1 << 0),
559  }, {
560  .name = "hdmi",
561  .devname = "exynos4-hdmi",
562  .enable = exynos4_clk_ip_tv_ctrl,
563  .ctrlbit = (1 << 3),
564  }, {
565  .name = "hdmiphy",
566  .devname = "exynos4-hdmi",
567  .enable = exynos4_clk_hdmiphy_ctrl,
568  .ctrlbit = (1 << 0),
569  }, {
570  .name = "dacphy",
571  .devname = "s5p-sdo",
572  .enable = exynos4_clk_dac_ctrl,
573  .ctrlbit = (1 << 0),
574  }, {
575  .name = "adc",
576  .enable = exynos4_clk_ip_peril_ctrl,
577  .ctrlbit = (1 << 15),
578  }, {
579  .name = "keypad",
580  .enable = exynos4_clk_ip_perir_ctrl,
581  .ctrlbit = (1 << 16),
582  }, {
583  .name = "rtc",
584  .enable = exynos4_clk_ip_perir_ctrl,
585  .ctrlbit = (1 << 15),
586  }, {
587  .name = "watchdog",
588  .parent = &exynos4_clk_aclk_100.clk,
589  .enable = exynos4_clk_ip_perir_ctrl,
590  .ctrlbit = (1 << 14),
591  }, {
592  .name = "usbhost",
593  .enable = exynos4_clk_ip_fsys_ctrl ,
594  .ctrlbit = (1 << 12),
595  }, {
596  .name = "otg",
597  .enable = exynos4_clk_ip_fsys_ctrl,
598  .ctrlbit = (1 << 13),
599  }, {
600  .name = "spi",
601  .devname = "exynos4210-spi.0",
602  .enable = exynos4_clk_ip_peril_ctrl,
603  .ctrlbit = (1 << 16),
604  }, {
605  .name = "spi",
606  .devname = "exynos4210-spi.1",
607  .enable = exynos4_clk_ip_peril_ctrl,
608  .ctrlbit = (1 << 17),
609  }, {
610  .name = "spi",
611  .devname = "exynos4210-spi.2",
612  .enable = exynos4_clk_ip_peril_ctrl,
613  .ctrlbit = (1 << 18),
614  }, {
615  .name = "iis",
616  .devname = "samsung-i2s.0",
617  .enable = exynos4_clk_ip_peril_ctrl,
618  .ctrlbit = (1 << 19),
619  }, {
620  .name = "iis",
621  .devname = "samsung-i2s.1",
622  .enable = exynos4_clk_ip_peril_ctrl,
623  .ctrlbit = (1 << 20),
624  }, {
625  .name = "iis",
626  .devname = "samsung-i2s.2",
627  .enable = exynos4_clk_ip_peril_ctrl,
628  .ctrlbit = (1 << 21),
629  }, {
630  .name = "pcm",
631  .devname = "samsung-pcm.1",
632  .enable = exynos4_clk_ip_peril_ctrl,
633  .ctrlbit = (1 << 22),
634  }, {
635  .name = "pcm",
636  .devname = "samsung-pcm.2",
637  .enable = exynos4_clk_ip_peril_ctrl,
638  .ctrlbit = (1 << 23),
639  }, {
640  .name = "slimbus",
641  .enable = exynos4_clk_ip_peril_ctrl,
642  .ctrlbit = (1 << 25),
643  }, {
644  .name = "spdif",
645  .devname = "samsung-spdif",
646  .enable = exynos4_clk_ip_peril_ctrl,
647  .ctrlbit = (1 << 26),
648  }, {
649  .name = "ac97",
650  .devname = "samsung-ac97",
651  .enable = exynos4_clk_ip_peril_ctrl,
652  .ctrlbit = (1 << 27),
653  }, {
654  .name = "mfc",
655  .devname = "s5p-mfc",
656  .enable = exynos4_clk_ip_mfc_ctrl,
657  .ctrlbit = (1 << 0),
658  }, {
659  .name = "i2c",
660  .devname = "s3c2440-i2c.0",
661  .parent = &exynos4_clk_aclk_100.clk,
662  .enable = exynos4_clk_ip_peril_ctrl,
663  .ctrlbit = (1 << 6),
664  }, {
665  .name = "i2c",
666  .devname = "s3c2440-i2c.1",
667  .parent = &exynos4_clk_aclk_100.clk,
668  .enable = exynos4_clk_ip_peril_ctrl,
669  .ctrlbit = (1 << 7),
670  }, {
671  .name = "i2c",
672  .devname = "s3c2440-i2c.2",
673  .parent = &exynos4_clk_aclk_100.clk,
674  .enable = exynos4_clk_ip_peril_ctrl,
675  .ctrlbit = (1 << 8),
676  }, {
677  .name = "i2c",
678  .devname = "s3c2440-i2c.3",
679  .parent = &exynos4_clk_aclk_100.clk,
680  .enable = exynos4_clk_ip_peril_ctrl,
681  .ctrlbit = (1 << 9),
682  }, {
683  .name = "i2c",
684  .devname = "s3c2440-i2c.4",
685  .parent = &exynos4_clk_aclk_100.clk,
686  .enable = exynos4_clk_ip_peril_ctrl,
687  .ctrlbit = (1 << 10),
688  }, {
689  .name = "i2c",
690  .devname = "s3c2440-i2c.5",
691  .parent = &exynos4_clk_aclk_100.clk,
692  .enable = exynos4_clk_ip_peril_ctrl,
693  .ctrlbit = (1 << 11),
694  }, {
695  .name = "i2c",
696  .devname = "s3c2440-i2c.6",
697  .parent = &exynos4_clk_aclk_100.clk,
698  .enable = exynos4_clk_ip_peril_ctrl,
699  .ctrlbit = (1 << 12),
700  }, {
701  .name = "i2c",
702  .devname = "s3c2440-i2c.7",
703  .parent = &exynos4_clk_aclk_100.clk,
704  .enable = exynos4_clk_ip_peril_ctrl,
705  .ctrlbit = (1 << 13),
706  }, {
707  .name = "i2c",
708  .devname = "s3c2440-hdmiphy-i2c",
709  .parent = &exynos4_clk_aclk_100.clk,
710  .enable = exynos4_clk_ip_peril_ctrl,
711  .ctrlbit = (1 << 14),
712  }, {
713  .name = SYSMMU_CLOCK_NAME,
714  .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
715  .enable = exynos4_clk_ip_mfc_ctrl,
716  .ctrlbit = (1 << 1),
717  }, {
718  .name = SYSMMU_CLOCK_NAME,
719  .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
720  .enable = exynos4_clk_ip_mfc_ctrl,
721  .ctrlbit = (1 << 2),
722  }, {
723  .name = SYSMMU_CLOCK_NAME,
724  .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
725  .enable = exynos4_clk_ip_tv_ctrl,
726  .ctrlbit = (1 << 4),
727  }, {
728  .name = SYSMMU_CLOCK_NAME,
729  .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
730  .enable = exynos4_clk_ip_cam_ctrl,
731  .ctrlbit = (1 << 11),
732  }, {
733  .name = SYSMMU_CLOCK_NAME,
734  .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
735  .enable = exynos4_clk_ip_image_ctrl,
736  .ctrlbit = (1 << 4),
737  }, {
738  .name = SYSMMU_CLOCK_NAME,
739  .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
740  .enable = exynos4_clk_ip_cam_ctrl,
741  .ctrlbit = (1 << 7),
742  }, {
743  .name = SYSMMU_CLOCK_NAME,
744  .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
745  .enable = exynos4_clk_ip_cam_ctrl,
746  .ctrlbit = (1 << 8),
747  }, {
748  .name = SYSMMU_CLOCK_NAME,
749  .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
750  .enable = exynos4_clk_ip_cam_ctrl,
751  .ctrlbit = (1 << 9),
752  }, {
753  .name = SYSMMU_CLOCK_NAME,
754  .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
755  .enable = exynos4_clk_ip_cam_ctrl,
756  .ctrlbit = (1 << 10),
757  }, {
758  .name = SYSMMU_CLOCK_NAME,
759  .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
760  .enable = exynos4_clk_ip_lcd0_ctrl,
761  .ctrlbit = (1 << 4),
762  }
763 };
764 
765 static struct clk exynos4_init_clocks_on[] = {
766  {
767  .name = "uart",
768  .devname = "s5pv210-uart.0",
769  .enable = exynos4_clk_ip_peril_ctrl,
770  .ctrlbit = (1 << 0),
771  }, {
772  .name = "uart",
773  .devname = "s5pv210-uart.1",
774  .enable = exynos4_clk_ip_peril_ctrl,
775  .ctrlbit = (1 << 1),
776  }, {
777  .name = "uart",
778  .devname = "s5pv210-uart.2",
779  .enable = exynos4_clk_ip_peril_ctrl,
780  .ctrlbit = (1 << 2),
781  }, {
782  .name = "uart",
783  .devname = "s5pv210-uart.3",
784  .enable = exynos4_clk_ip_peril_ctrl,
785  .ctrlbit = (1 << 3),
786  }, {
787  .name = "uart",
788  .devname = "s5pv210-uart.4",
789  .enable = exynos4_clk_ip_peril_ctrl,
790  .ctrlbit = (1 << 4),
791  }, {
792  .name = "uart",
793  .devname = "s5pv210-uart.5",
794  .enable = exynos4_clk_ip_peril_ctrl,
795  .ctrlbit = (1 << 5),
796  }
797 };
798 
799 static struct clk exynos4_clk_pdma0 = {
800  .name = "dma",
801  .devname = "dma-pl330.0",
802  .enable = exynos4_clk_ip_fsys_ctrl,
803  .ctrlbit = (1 << 0),
804 };
805 
806 static struct clk exynos4_clk_pdma1 = {
807  .name = "dma",
808  .devname = "dma-pl330.1",
809  .enable = exynos4_clk_ip_fsys_ctrl,
810  .ctrlbit = (1 << 1),
811 };
812 
813 static struct clk exynos4_clk_mdma1 = {
814  .name = "dma",
815  .devname = "dma-pl330.2",
816  .enable = exynos4_clk_ip_image_ctrl,
817  .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
818 };
819 
820 static struct clk exynos4_clk_fimd0 = {
821  .name = "fimd",
822  .devname = "exynos4-fb.0",
823  .enable = exynos4_clk_ip_lcd0_ctrl,
824  .ctrlbit = (1 << 0),
825 };
826 
827 struct clk *exynos4_clkset_group_list[] = {
828  [0] = &clk_ext_xtal_mux,
829  [1] = &clk_xusbxti,
830  [2] = &exynos4_clk_sclk_hdmi27m,
831  [3] = &exynos4_clk_sclk_usbphy0,
832  [4] = &exynos4_clk_sclk_usbphy1,
833  [5] = &exynos4_clk_sclk_hdmiphy,
834  [6] = &exynos4_clk_mout_mpll.clk,
835  [7] = &exynos4_clk_mout_epll.clk,
836  [8] = &exynos4_clk_sclk_vpll.clk,
837 };
838 
839 struct clksrc_sources exynos4_clkset_group = {
840  .sources = exynos4_clkset_group_list,
841  .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
842 };
843 
844 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
845  [0] = &exynos4_clk_mout_mpll.clk,
846  [1] = &exynos4_clk_sclk_apll.clk,
847 };
848 
849 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
850  .sources = exynos4_clkset_mout_g2d0_list,
851  .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
852 };
853 
854 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
855  [0] = &exynos4_clk_mout_epll.clk,
856  [1] = &exynos4_clk_sclk_vpll.clk,
857 };
858 
859 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
860  .sources = exynos4_clkset_mout_g2d1_list,
861  .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
862 };
863 
864 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
865  [0] = &exynos4_clk_mout_mpll.clk,
866  [1] = &exynos4_clk_sclk_apll.clk,
867 };
868 
869 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
870  .sources = exynos4_clkset_mout_mfc0_list,
871  .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
872 };
873 
874 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
875  .clk = {
876  .name = "mout_mfc0",
877  },
878  .sources = &exynos4_clkset_mout_mfc0,
879  .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
880 };
881 
882 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
883  [0] = &exynos4_clk_mout_epll.clk,
884  [1] = &exynos4_clk_sclk_vpll.clk,
885 };
886 
887 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
888  .sources = exynos4_clkset_mout_mfc1_list,
889  .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
890 };
891 
892 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
893  .clk = {
894  .name = "mout_mfc1",
895  },
896  .sources = &exynos4_clkset_mout_mfc1,
897  .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
898 };
899 
900 static struct clk *exynos4_clkset_mout_mfc_list[] = {
901  [0] = &exynos4_clk_mout_mfc0.clk,
902  [1] = &exynos4_clk_mout_mfc1.clk,
903 };
904 
905 static struct clksrc_sources exynos4_clkset_mout_mfc = {
906  .sources = exynos4_clkset_mout_mfc_list,
907  .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
908 };
909 
910 static struct clk *exynos4_clkset_sclk_dac_list[] = {
911  [0] = &exynos4_clk_sclk_vpll.clk,
912  [1] = &exynos4_clk_sclk_hdmiphy,
913 };
914 
915 static struct clksrc_sources exynos4_clkset_sclk_dac = {
916  .sources = exynos4_clkset_sclk_dac_list,
917  .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
918 };
919 
920 static struct clksrc_clk exynos4_clk_sclk_dac = {
921  .clk = {
922  .name = "sclk_dac",
923  .enable = exynos4_clksrc_mask_tv_ctrl,
924  .ctrlbit = (1 << 8),
925  },
926  .sources = &exynos4_clkset_sclk_dac,
927  .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
928 };
929 
930 static struct clksrc_clk exynos4_clk_sclk_pixel = {
931  .clk = {
932  .name = "sclk_pixel",
933  .parent = &exynos4_clk_sclk_vpll.clk,
934  },
935  .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
936 };
937 
938 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
939  [0] = &exynos4_clk_sclk_pixel.clk,
940  [1] = &exynos4_clk_sclk_hdmiphy,
941 };
942 
943 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
944  .sources = exynos4_clkset_sclk_hdmi_list,
945  .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
946 };
947 
948 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
949  .clk = {
950  .name = "sclk_hdmi",
951  .enable = exynos4_clksrc_mask_tv_ctrl,
952  .ctrlbit = (1 << 0),
953  },
954  .sources = &exynos4_clkset_sclk_hdmi,
955  .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
956 };
957 
958 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
959  [0] = &exynos4_clk_sclk_dac.clk,
960  [1] = &exynos4_clk_sclk_hdmi.clk,
961 };
962 
963 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
964  .sources = exynos4_clkset_sclk_mixer_list,
965  .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
966 };
967 
968 static struct clksrc_clk exynos4_clk_sclk_mixer = {
969  .clk = {
970  .name = "sclk_mixer",
971  .enable = exynos4_clksrc_mask_tv_ctrl,
972  .ctrlbit = (1 << 4),
973  },
974  .sources = &exynos4_clkset_sclk_mixer,
975  .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
976 };
977 
978 static struct clksrc_clk *exynos4_sclk_tv[] = {
979  &exynos4_clk_sclk_dac,
980  &exynos4_clk_sclk_pixel,
981  &exynos4_clk_sclk_hdmi,
982  &exynos4_clk_sclk_mixer,
983 };
984 
985 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
986  .clk = {
987  .name = "dout_mmc0",
988  },
989  .sources = &exynos4_clkset_group,
990  .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
991  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
992 };
993 
994 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
995  .clk = {
996  .name = "dout_mmc1",
997  },
998  .sources = &exynos4_clkset_group,
999  .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
1000  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1001 };
1002 
1003 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1004  .clk = {
1005  .name = "dout_mmc2",
1006  },
1007  .sources = &exynos4_clkset_group,
1008  .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1009  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1010 };
1011 
1012 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1013  .clk = {
1014  .name = "dout_mmc3",
1015  },
1016  .sources = &exynos4_clkset_group,
1017  .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1018  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1019 };
1020 
1021 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1022  .clk = {
1023  .name = "dout_mmc4",
1024  },
1025  .sources = &exynos4_clkset_group,
1026  .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1027  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1028 };
1029 
1030 static struct clksrc_clk exynos4_clksrcs[] = {
1031  {
1032  .clk = {
1033  .name = "sclk_pwm",
1034  .enable = exynos4_clksrc_mask_peril0_ctrl,
1035  .ctrlbit = (1 << 24),
1036  },
1037  .sources = &exynos4_clkset_group,
1038  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1039  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1040  }, {
1041  .clk = {
1042  .name = "sclk_csis",
1043  .devname = "s5p-mipi-csis.0",
1044  .enable = exynos4_clksrc_mask_cam_ctrl,
1045  .ctrlbit = (1 << 24),
1046  },
1047  .sources = &exynos4_clkset_group,
1048  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1049  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1050  }, {
1051  .clk = {
1052  .name = "sclk_csis",
1053  .devname = "s5p-mipi-csis.1",
1054  .enable = exynos4_clksrc_mask_cam_ctrl,
1055  .ctrlbit = (1 << 28),
1056  },
1057  .sources = &exynos4_clkset_group,
1058  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1059  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1060  }, {
1061  .clk = {
1062  .name = "sclk_cam0",
1063  .enable = exynos4_clksrc_mask_cam_ctrl,
1064  .ctrlbit = (1 << 16),
1065  },
1066  .sources = &exynos4_clkset_group,
1067  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1068  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1069  }, {
1070  .clk = {
1071  .name = "sclk_cam1",
1072  .enable = exynos4_clksrc_mask_cam_ctrl,
1073  .ctrlbit = (1 << 20),
1074  },
1075  .sources = &exynos4_clkset_group,
1076  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1077  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1078  }, {
1079  .clk = {
1080  .name = "sclk_fimc",
1081  .devname = "exynos4-fimc.0",
1082  .enable = exynos4_clksrc_mask_cam_ctrl,
1083  .ctrlbit = (1 << 0),
1084  },
1085  .sources = &exynos4_clkset_group,
1086  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1087  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1088  }, {
1089  .clk = {
1090  .name = "sclk_fimc",
1091  .devname = "exynos4-fimc.1",
1092  .enable = exynos4_clksrc_mask_cam_ctrl,
1093  .ctrlbit = (1 << 4),
1094  },
1095  .sources = &exynos4_clkset_group,
1096  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1097  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1098  }, {
1099  .clk = {
1100  .name = "sclk_fimc",
1101  .devname = "exynos4-fimc.2",
1102  .enable = exynos4_clksrc_mask_cam_ctrl,
1103  .ctrlbit = (1 << 8),
1104  },
1105  .sources = &exynos4_clkset_group,
1106  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1107  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1108  }, {
1109  .clk = {
1110  .name = "sclk_fimc",
1111  .devname = "exynos4-fimc.3",
1112  .enable = exynos4_clksrc_mask_cam_ctrl,
1113  .ctrlbit = (1 << 12),
1114  },
1115  .sources = &exynos4_clkset_group,
1116  .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1117  .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1118  }, {
1119  .clk = {
1120  .name = "sclk_fimd",
1121  .devname = "exynos4-fb.0",
1122  .enable = exynos4_clksrc_mask_lcd0_ctrl,
1123  .ctrlbit = (1 << 0),
1124  },
1125  .sources = &exynos4_clkset_group,
1126  .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1127  .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1128  }, {
1129  .clk = {
1130  .name = "sclk_mfc",
1131  .devname = "s5p-mfc",
1132  },
1133  .sources = &exynos4_clkset_mout_mfc,
1134  .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1135  .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1136  }, {
1137  .clk = {
1138  .name = "sclk_dwmmc",
1139  .parent = &exynos4_clk_dout_mmc4.clk,
1140  .enable = exynos4_clksrc_mask_fsys_ctrl,
1141  .ctrlbit = (1 << 16),
1142  },
1143  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1144  }
1145 };
1146 
1147 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1148  .clk = {
1149  .name = "uclk1",
1150  .devname = "exynos4210-uart.0",
1151  .enable = exynos4_clksrc_mask_peril0_ctrl,
1152  .ctrlbit = (1 << 0),
1153  },
1154  .sources = &exynos4_clkset_group,
1155  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1156  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1157 };
1158 
1159 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1160  .clk = {
1161  .name = "uclk1",
1162  .devname = "exynos4210-uart.1",
1163  .enable = exynos4_clksrc_mask_peril0_ctrl,
1164  .ctrlbit = (1 << 4),
1165  },
1166  .sources = &exynos4_clkset_group,
1167  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1168  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1169 };
1170 
1171 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1172  .clk = {
1173  .name = "uclk1",
1174  .devname = "exynos4210-uart.2",
1175  .enable = exynos4_clksrc_mask_peril0_ctrl,
1176  .ctrlbit = (1 << 8),
1177  },
1178  .sources = &exynos4_clkset_group,
1179  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1180  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1181 };
1182 
1183 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1184  .clk = {
1185  .name = "uclk1",
1186  .devname = "exynos4210-uart.3",
1187  .enable = exynos4_clksrc_mask_peril0_ctrl,
1188  .ctrlbit = (1 << 12),
1189  },
1190  .sources = &exynos4_clkset_group,
1191  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1192  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1193 };
1194 
1195 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1196  .clk = {
1197  .name = "sclk_mmc",
1198  .devname = "exynos4-sdhci.0",
1199  .parent = &exynos4_clk_dout_mmc0.clk,
1200  .enable = exynos4_clksrc_mask_fsys_ctrl,
1201  .ctrlbit = (1 << 0),
1202  },
1203  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1204 };
1205 
1206 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1207  .clk = {
1208  .name = "sclk_mmc",
1209  .devname = "exynos4-sdhci.1",
1210  .parent = &exynos4_clk_dout_mmc1.clk,
1211  .enable = exynos4_clksrc_mask_fsys_ctrl,
1212  .ctrlbit = (1 << 4),
1213  },
1214  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1215 };
1216 
1217 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1218  .clk = {
1219  .name = "sclk_mmc",
1220  .devname = "exynos4-sdhci.2",
1221  .parent = &exynos4_clk_dout_mmc2.clk,
1222  .enable = exynos4_clksrc_mask_fsys_ctrl,
1223  .ctrlbit = (1 << 8),
1224  },
1225  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1226 };
1227 
1228 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1229  .clk = {
1230  .name = "sclk_mmc",
1231  .devname = "exynos4-sdhci.3",
1232  .parent = &exynos4_clk_dout_mmc3.clk,
1233  .enable = exynos4_clksrc_mask_fsys_ctrl,
1234  .ctrlbit = (1 << 12),
1235  },
1236  .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1237 };
1238 
1239 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1240  .clk = {
1241  .name = "mdout_spi",
1242  .devname = "exynos4210-spi.0",
1243  },
1244  .sources = &exynos4_clkset_group,
1245  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1246  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1247 };
1248 
1249 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1250  .clk = {
1251  .name = "mdout_spi",
1252  .devname = "exynos4210-spi.1",
1253  },
1254  .sources = &exynos4_clkset_group,
1255  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1256  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1257 };
1258 
1259 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1260  .clk = {
1261  .name = "mdout_spi",
1262  .devname = "exynos4210-spi.2",
1263  },
1264  .sources = &exynos4_clkset_group,
1265  .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1266  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1267 };
1268 
1269 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1270  .clk = {
1271  .name = "sclk_spi",
1272  .devname = "exynos4210-spi.0",
1273  .parent = &exynos4_clk_mdout_spi0.clk,
1274  .enable = exynos4_clksrc_mask_peril1_ctrl,
1275  .ctrlbit = (1 << 16),
1276  },
1277  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1278 };
1279 
1280 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1281  .clk = {
1282  .name = "sclk_spi",
1283  .devname = "exynos4210-spi.1",
1284  .parent = &exynos4_clk_mdout_spi1.clk,
1285  .enable = exynos4_clksrc_mask_peril1_ctrl,
1286  .ctrlbit = (1 << 20),
1287  },
1288  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1289 };
1290 
1291 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1292  .clk = {
1293  .name = "sclk_spi",
1294  .devname = "exynos4210-spi.2",
1295  .parent = &exynos4_clk_mdout_spi2.clk,
1296  .enable = exynos4_clksrc_mask_peril1_ctrl,
1297  .ctrlbit = (1 << 24),
1298  },
1299  .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1300 };
1301 
1302 /* Clock initialization code */
1303 static struct clksrc_clk *exynos4_sysclks[] = {
1304  &exynos4_clk_mout_apll,
1305  &exynos4_clk_sclk_apll,
1306  &exynos4_clk_mout_epll,
1307  &exynos4_clk_mout_mpll,
1308  &exynos4_clk_moutcore,
1309  &exynos4_clk_coreclk,
1310  &exynos4_clk_armclk,
1311  &exynos4_clk_aclk_corem0,
1312  &exynos4_clk_aclk_cores,
1313  &exynos4_clk_aclk_corem1,
1314  &exynos4_clk_periphclk,
1315  &exynos4_clk_mout_corebus,
1316  &exynos4_clk_sclk_dmc,
1317  &exynos4_clk_aclk_cored,
1318  &exynos4_clk_aclk_corep,
1319  &exynos4_clk_aclk_acp,
1320  &exynos4_clk_pclk_acp,
1321  &exynos4_clk_vpllsrc,
1322  &exynos4_clk_sclk_vpll,
1323  &exynos4_clk_aclk_200,
1324  &exynos4_clk_aclk_100,
1325  &exynos4_clk_aclk_160,
1326  &exynos4_clk_aclk_133,
1327  &exynos4_clk_dout_mmc0,
1328  &exynos4_clk_dout_mmc1,
1329  &exynos4_clk_dout_mmc2,
1330  &exynos4_clk_dout_mmc3,
1331  &exynos4_clk_dout_mmc4,
1332  &exynos4_clk_mout_mfc0,
1333  &exynos4_clk_mout_mfc1,
1334 };
1335 
1336 static struct clk *exynos4_clk_cdev[] = {
1337  &exynos4_clk_pdma0,
1338  &exynos4_clk_pdma1,
1339  &exynos4_clk_mdma1,
1340  &exynos4_clk_fimd0,
1341 };
1342 
1343 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1344  &exynos4_clk_sclk_uart0,
1345  &exynos4_clk_sclk_uart1,
1346  &exynos4_clk_sclk_uart2,
1347  &exynos4_clk_sclk_uart3,
1348  &exynos4_clk_sclk_mmc0,
1349  &exynos4_clk_sclk_mmc1,
1350  &exynos4_clk_sclk_mmc2,
1351  &exynos4_clk_sclk_mmc3,
1352  &exynos4_clk_sclk_spi0,
1353  &exynos4_clk_sclk_spi1,
1354  &exynos4_clk_sclk_spi2,
1355  &exynos4_clk_mdout_spi0,
1356  &exynos4_clk_mdout_spi1,
1357  &exynos4_clk_mdout_spi2,
1358 };
1359 
1360 static struct clk_lookup exynos4_clk_lookup[] = {
1361  CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1362  CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1363  CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1364  CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1365  CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1366  CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1367  CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1368  CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1369  CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1370  CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1371  CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1372  CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1373  CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1374  CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1375  CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1376 };
1377 
1378 static int xtal_rate;
1379 
1380 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1381 {
1382  if (soc_is_exynos4210())
1383  return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1384  pll_4508);
1385  else if (soc_is_exynos4212() || soc_is_exynos4412())
1386  return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1387  else
1388  return 0;
1389 }
1390 
1391 static struct clk_ops exynos4_fout_apll_ops = {
1392  .get_rate = exynos4_fout_apll_get_rate,
1393 };
1394 
1395 static u32 exynos4_vpll_div[][8] = {
1396  { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1397  { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1398 };
1399 
1400 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1401 {
1402  return clk->rate;
1403 }
1404 
1405 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1406 {
1407  unsigned int vpll_con0, vpll_con1 = 0;
1408  unsigned int i;
1409 
1410  /* Return if nothing changed */
1411  if (clk->rate == rate)
1412  return 0;
1413 
1414  vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1415  vpll_con0 &= ~(0x1 << 27 | \
1416  PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1417  PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1418  PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1419 
1420  vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1421  vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1422  PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1423  PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1424 
1425  for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1426  if (exynos4_vpll_div[i][0] == rate) {
1427  vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1428  vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1429  vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1430  vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1431  vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1432  vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1433  vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1434  break;
1435  }
1436  }
1437 
1438  if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1439  printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1440  __func__);
1441  return -EINVAL;
1442  }
1443 
1444  __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1445  __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1446 
1447  /* Wait for VPLL lock */
1448  while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1449  continue;
1450 
1451  clk->rate = rate;
1452  return 0;
1453 }
1454 
1455 static struct clk_ops exynos4_vpll_ops = {
1456  .get_rate = exynos4_vpll_get_rate,
1457  .set_rate = exynos4_vpll_set_rate,
1458 };
1459 
1460 void __init_or_cpufreq exynos4_setup_clocks(void)
1461 {
1462  struct clk *xtal_clk;
1463  unsigned long apll = 0;
1464  unsigned long mpll = 0;
1465  unsigned long epll = 0;
1466  unsigned long vpll = 0;
1467  unsigned long vpllsrc;
1468  unsigned long xtal;
1469  unsigned long armclk;
1470  unsigned long sclk_dmc;
1471  unsigned long aclk_200;
1472  unsigned long aclk_100;
1473  unsigned long aclk_160;
1474  unsigned long aclk_133;
1475  unsigned int ptr;
1476 
1477  printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1478 
1479  xtal_clk = clk_get(NULL, "xtal");
1480  BUG_ON(IS_ERR(xtal_clk));
1481 
1482  xtal = clk_get_rate(xtal_clk);
1483 
1484  xtal_rate = xtal;
1485 
1486  clk_put(xtal_clk);
1487 
1488  printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1489 
1490  if (soc_is_exynos4210()) {
1491  apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1492  pll_4508);
1493  mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1494  pll_4508);
1495  epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1496  __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1497 
1498  vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1499  vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1500  __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1501  } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1502  apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1503  mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1504  epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1505  __raw_readl(EXYNOS4_EPLL_CON1));
1506 
1507  vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1508  vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1509  __raw_readl(EXYNOS4_VPLL_CON1));
1510  } else {
1511  /* nothing */
1512  }
1513 
1514  clk_fout_apll.ops = &exynos4_fout_apll_ops;
1515  clk_fout_mpll.rate = mpll;
1516  clk_fout_epll.rate = epll;
1517  clk_fout_vpll.ops = &exynos4_vpll_ops;
1518  clk_fout_vpll.rate = vpll;
1519 
1520  printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1521  apll, mpll, epll, vpll);
1522 
1523  armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1524  sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1525 
1526  aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1527  aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1528  aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1529  aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1530 
1531  printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1532  "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1533  armclk, sclk_dmc, aclk_200,
1534  aclk_100, aclk_160, aclk_133);
1535 
1536  clk_f.rate = armclk;
1537  clk_h.rate = sclk_dmc;
1538  clk_p.rate = aclk_100;
1539 
1540  for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1541  s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1542 }
1543 
1544 static struct clk *exynos4_clks[] __initdata = {
1545  &exynos4_clk_sclk_hdmi27m,
1546  &exynos4_clk_sclk_hdmiphy,
1547  &exynos4_clk_sclk_usbphy0,
1548  &exynos4_clk_sclk_usbphy1,
1549 };
1550 
1551 #ifdef CONFIG_PM_SLEEP
1552 static int exynos4_clock_suspend(void)
1553 {
1554  s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1555  return 0;
1556 }
1557 
1558 static void exynos4_clock_resume(void)
1559 {
1560  s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1561 }
1562 
1563 #else
1564 #define exynos4_clock_suspend NULL
1565 #define exynos4_clock_resume NULL
1566 #endif
1567 
1568 static struct syscore_ops exynos4_clock_syscore_ops = {
1569  .suspend = exynos4_clock_suspend,
1570  .resume = exynos4_clock_resume,
1571 };
1572 
1573 void __init exynos4_register_clocks(void)
1574 {
1575  int ptr;
1576 
1577  s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1578 
1579  for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1580  s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1581 
1582  for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1583  s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1584 
1585  for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1586  s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1587 
1588  s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1589  s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1590 
1591  s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1592  for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1593  s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1594 
1595  s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1596  s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1597  clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1598 
1599  register_syscore_ops(&exynos4_clock_syscore_ops);
1600  s3c24xx_register_clock(&dummy_apb_pclk);
1601 
1602  s3c_pwmclk_init();
1603 }
Generated on Thu Jan 10 2013 12:58:54 for Linux Kernel by   doxygen 1.8.2