clock-r8a7740.c File Reference

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/common.h>
#include <mach/r8a7740.h>

Go to the source code of this file.

Macros
#define	FRQCRA   IOMEM(0xe6150000)
#define	FRQCRB   IOMEM(0xe6150004)
#define	VCLKCR1   IOMEM(0xE6150008)
#define	VCLKCR2   IOMEM(0xE615000c)
#define	FRQCRC   IOMEM(0xe61500e0)
#define	FSIACKCR   IOMEM(0xe6150018)
#define	PLLC01CR   IOMEM(0xe6150028)
#define	SUBCKCR   IOMEM(0xe6150080)
#define	USBCKCR   IOMEM(0xe615008c)
#define	MSTPSR0   IOMEM(0xe6150030)
#define	MSTPSR1   IOMEM(0xe6150038)
#define	MSTPSR2   IOMEM(0xe6150040)
#define	MSTPSR3   IOMEM(0xe6150048)
#define	MSTPSR4   IOMEM(0xe615004c)
#define	FSIBCKCR   IOMEM(0xe6150090)
#define	HDMICKCR   IOMEM(0xe6150094)
#define	SMSTPCR0   IOMEM(0xe6150130)
#define	SMSTPCR1   IOMEM(0xe6150134)
#define	SMSTPCR2   IOMEM(0xe6150138)
#define	SMSTPCR3   IOMEM(0xe615013c)
#define	SMSTPCR4   IOMEM(0xe6150140)

Enumerations
enum	{   DIV6_HDMI, DIV6_VCLK1, DIV6_VCLK2, DIV6_FSIA,   DIV6_FSIB, DIV6_REPARENT_NR }
enum	{   DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1,   DIV4_HP, DIV4_HPP, DIV4_USBP, DIV4_S,   DIV4_ZB, DIV4_M3, DIV4_CP, DIV4_NR }
enum	{ DIV6_SUB, DIV6_NR }
enum	{   MSTP128, MSTP127, MSTP125, MSTP116,   MSTP111, MSTP100, MSTP117, MSTP230,   MSTP222, MSTP218, MSTP217, MSTP216,   MSTP214, MSTP207, MSTP206, MSTP204,   MSTP203, MSTP202, MSTP201, MSTP200,   MSTP329, MSTP328, MSTP323, MSTP320,   MSTP314, MSTP313, MSTP312, MSTP309,   MSTP416, MSTP415, MSTP407, MSTP406,   MSTP_NR }

Functions
void __init	r8a7740_clock_init (u8 md_ck)

Variables
struct clk *	main_clks []
struct clk	div4_clks [DIV4_NR]

Macro Definition Documentation

#define FRQCRA   IOMEM(0xe6150000)

Definition at line 44 of file clock-r8a7740.c.

#define FRQCRB   IOMEM(0xe6150004)

Definition at line 45 of file clock-r8a7740.c.

#define FRQCRC   IOMEM(0xe61500e0)

Definition at line 48 of file clock-r8a7740.c.

#define FSIACKCR   IOMEM(0xe6150018)

Definition at line 49 of file clock-r8a7740.c.

#define FSIBCKCR   IOMEM(0xe6150090)

Definition at line 60 of file clock-r8a7740.c.

#define HDMICKCR   IOMEM(0xe6150094)

Definition at line 61 of file clock-r8a7740.c.

#define MSTPSR0   IOMEM(0xe6150030)

Definition at line 55 of file clock-r8a7740.c.

#define MSTPSR1   IOMEM(0xe6150038)

Definition at line 56 of file clock-r8a7740.c.

#define MSTPSR2   IOMEM(0xe6150040)

Definition at line 57 of file clock-r8a7740.c.

#define MSTPSR3   IOMEM(0xe6150048)

Definition at line 58 of file clock-r8a7740.c.

#define MSTPSR4   IOMEM(0xe615004c)

Definition at line 59 of file clock-r8a7740.c.

#define PLLC01CR   IOMEM(0xe6150028)

Definition at line 50 of file clock-r8a7740.c.

#define SMSTPCR0   IOMEM(0xe6150130)

Definition at line 62 of file clock-r8a7740.c.

#define SMSTPCR1   IOMEM(0xe6150134)

Definition at line 63 of file clock-r8a7740.c.

#define SMSTPCR2   IOMEM(0xe6150138)

Definition at line 64 of file clock-r8a7740.c.

#define SMSTPCR3   IOMEM(0xe615013c)

Definition at line 65 of file clock-r8a7740.c.

#define SMSTPCR4   IOMEM(0xe6150140)

Definition at line 66 of file clock-r8a7740.c.

#define SUBCKCR   IOMEM(0xe6150080)

Definition at line 52 of file clock-r8a7740.c.

#define USBCKCR   IOMEM(0xe615008c)

Definition at line 53 of file clock-r8a7740.c.

#define VCLKCR1   IOMEM(0xE6150008)

Definition at line 46 of file clock-r8a7740.c.

#define VCLKCR2   IOMEM(0xE615000c)

Definition at line 47 of file clock-r8a7740.c.

Enumeration Type Documentation

anonymous enum

Enumerator:

DIV6_HDMI
DIV6_VCLK1
DIV6_VCLK2
DIV6_FSIA
DIV6_FSIB
DIV6_REPARENT_NR

Definition at line 331 of file clock-r8a7740.c.

anonymous enum

Enumerator:

DIV4_I
DIV4_ZG
DIV4_B
DIV4_M1
DIV4_HP
DIV4_HPP
DIV4_USBP
DIV4_S
DIV4_ZB
DIV4_M3
DIV4_CP
DIV4_NR

Definition at line 431 of file clock-r8a7740.c.

anonymous enum

Enumerator:

DIV6_SUB
DIV6_NR

Definition at line 451 of file clock-r8a7740.c.

anonymous enum

Enumerator:

MSTP128
MSTP127
MSTP125
MSTP116
MSTP111
MSTP100
MSTP117
MSTP230
MSTP222
MSTP218
MSTP217
MSTP216
MSTP214
MSTP207
MSTP206
MSTP204
MSTP203
MSTP202
MSTP201
MSTP200
MSTP329
MSTP328
MSTP323
MSTP320
MSTP314
MSTP313
MSTP312
MSTP309
MSTP416
MSTP415
MSTP407
MSTP406
MSTP_NR

Definition at line 460 of file clock-r8a7740.c.

Function Documentation

void __init r8a7740_clock_init

(

u8

md_ck

)

Definition at line 601 of file clock-r8a7740.c.

Variable Documentation

struct clk div4_clks[DIV4_NR]

Initial value:

= {
    [DIV4_I]    = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
    [DIV4_ZG]   = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
    [DIV4_B]    = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
    [DIV4_M1]   = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  4, 0x6fff, CLK_ENABLE_ON_INIT),
    [DIV4_HP]   = SH_CLK_DIV4(&pllc1_clk, FRQCRB,  4, 0x6fff, 0),
    [DIV4_HPP]  = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
    [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
    [DIV4_S]    = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
    [DIV4_ZB]   = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  8, 0x6fff, 0),
    [DIV4_M3]   = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  4, 0x6fff, 0),
    [DIV4_CP]   = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  0, 0x6fff, 0),
}

Definition at line 437 of file clock-r8a7740.c.

struct clk* main_clks[]

Initial value:

= {
    &extalr_clk,
    &extal1_clk,
    &extal2_clk,
    &extal1_div2_clk,
    &extal1_div1024_clk,
    &extal1_div2048_clk,
    &extal2_div2_clk,
    &dv_clk,
    &system_clk,
    &system_div2_clk,
    &r_clk,
    &pllc0_clk,
    &pllc1_clk,
    &pllc1_div2_clk,
    &usb24s_clk,
    &usb24_clk,
    &fsiack_clk,
    &fsibck_clk,
}

Definition at line 286 of file clock-r8a7740.c.