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clock-r8a7740.c
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1 /*
2  * R8A7740 processor support
3  *
4  * Copyright (C) 2011 Renesas Solutions Corp.
5  * Copyright (C) 2011 Kuninori Morimoto <[email protected]>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19  */
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/io.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/common.h>
26 #include <mach/r8a7740.h>
27 
28 /*
29  * | MDx | XTAL1/EXTAL1 | System | EXTALR |
30  * Clock |-------+-----------------+ clock | 32.768 | RCLK
31  * Mode | 2/1/0 | src MHz | source | KHz | source
32  * -------+-------+-----------------+-----------+--------+----------
33  * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
34  * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
35  * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
36  * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
37  * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
38  * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
39  * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
40  * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
41  */
42 
43 /* CPG registers */
44 #define FRQCRA IOMEM(0xe6150000)
45 #define FRQCRB IOMEM(0xe6150004)
46 #define VCLKCR1 IOMEM(0xE6150008)
47 #define VCLKCR2 IOMEM(0xE615000c)
48 #define FRQCRC IOMEM(0xe61500e0)
49 #define FSIACKCR IOMEM(0xe6150018)
50 #define PLLC01CR IOMEM(0xe6150028)
51 
52 #define SUBCKCR IOMEM(0xe6150080)
53 #define USBCKCR IOMEM(0xe615008c)
54 
55 #define MSTPSR0 IOMEM(0xe6150030)
56 #define MSTPSR1 IOMEM(0xe6150038)
57 #define MSTPSR2 IOMEM(0xe6150040)
58 #define MSTPSR3 IOMEM(0xe6150048)
59 #define MSTPSR4 IOMEM(0xe615004c)
60 #define FSIBCKCR IOMEM(0xe6150090)
61 #define HDMICKCR IOMEM(0xe6150094)
62 #define SMSTPCR0 IOMEM(0xe6150130)
63 #define SMSTPCR1 IOMEM(0xe6150134)
64 #define SMSTPCR2 IOMEM(0xe6150138)
65 #define SMSTPCR3 IOMEM(0xe615013c)
66 #define SMSTPCR4 IOMEM(0xe6150140)
67 
68 /* Fixed 32 KHz root clock from EXTALR pin */
69 static struct clk extalr_clk = {
70  .rate = 32768,
71 };
72 
73 /*
74  * 25MHz default rate for the EXTAL1 root input clock.
75  * If needed, reset this with clk_set_rate() from the platform code.
76  */
77 static struct clk extal1_clk = {
78  .rate = 25000000,
79 };
80 
81 /*
82  * 48MHz default rate for the EXTAL2 root input clock.
83  * If needed, reset this with clk_set_rate() from the platform code.
84  */
85 static struct clk extal2_clk = {
86  .rate = 48000000,
87 };
88 
89 /*
90  * 27MHz default rate for the DV_CLKI root input clock.
91  * If needed, reset this with clk_set_rate() from the platform code.
92  */
93 static struct clk dv_clk = {
94  .rate = 27000000,
95 };
96 
97 static unsigned long div_recalc(struct clk *clk)
98 {
99  return clk->parent->rate / (int)(clk->priv);
100 }
101 
102 static struct sh_clk_ops div_clk_ops = {
103  .recalc = div_recalc,
104 };
105 
106 /* extal1 / 2 */
107 static struct clk extal1_div2_clk = {
108  .ops = &div_clk_ops,
109  .priv = (void *)2,
110  .parent = &extal1_clk,
111 };
112 
113 /* extal1 / 1024 */
114 static struct clk extal1_div1024_clk = {
115  .ops = &div_clk_ops,
116  .priv = (void *)1024,
117  .parent = &extal1_clk,
118 };
119 
120 /* extal1 / 2 / 1024 */
121 static struct clk extal1_div2048_clk = {
122  .ops = &div_clk_ops,
123  .priv = (void *)1024,
124  .parent = &extal1_div2_clk,
125 };
126 
127 /* extal2 / 2 */
128 static struct clk extal2_div2_clk = {
129  .ops = &div_clk_ops,
130  .priv = (void *)2,
131  .parent = &extal2_clk,
132 };
133 
134 static struct sh_clk_ops followparent_clk_ops = {
135  .recalc = followparent_recalc,
136 };
137 
138 /* Main clock */
139 static struct clk system_clk = {
140  .ops = &followparent_clk_ops,
141 };
142 
143 static struct clk system_div2_clk = {
144  .ops = &div_clk_ops,
145  .priv = (void *)2,
146  .parent = &system_clk,
147 };
148 
149 /* r_clk */
150 static struct clk r_clk = {
151  .ops = &followparent_clk_ops,
152 };
153 
154 /* PLLC0/PLLC1 */
155 static unsigned long pllc01_recalc(struct clk *clk)
156 {
157  unsigned long mult = 1;
158 
159  if (__raw_readl(PLLC01CR) & (1 << 14))
160  mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
161 
162  return clk->parent->rate * mult;
163 }
164 
165 static struct sh_clk_ops pllc01_clk_ops = {
166  .recalc = pllc01_recalc,
167 };
168 
169 static struct clk pllc0_clk = {
170  .ops = &pllc01_clk_ops,
171  .flags = CLK_ENABLE_ON_INIT,
172  .parent = &system_clk,
173  .enable_reg = (void __iomem *)FRQCRC,
174 };
175 
176 static struct clk pllc1_clk = {
177  .ops = &pllc01_clk_ops,
178  .flags = CLK_ENABLE_ON_INIT,
179  .parent = &system_div2_clk,
180  .enable_reg = (void __iomem *)FRQCRA,
181 };
182 
183 /* PLLC1 / 2 */
184 static struct clk pllc1_div2_clk = {
185  .ops = &div_clk_ops,
186  .priv = (void *)2,
187  .parent = &pllc1_clk,
188 };
189 
190 /* USB clock */
191 static struct clk *usb24s_parents[] = {
192  [0] = &system_clk,
193  [1] = &extal2_clk
194 };
195 
196 static int usb24s_enable(struct clk *clk)
197 {
198  __raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
199 
200  return 0;
201 }
202 
203 static void usb24s_disable(struct clk *clk)
204 {
205  __raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
206 }
207 
208 static int usb24s_set_parent(struct clk *clk, struct clk *parent)
209 {
210  int i, ret;
211  u32 val;
212 
213  if (!clk->parent_table || !clk->parent_num)
214  return -EINVAL;
215 
216  /* Search the parent */
217  for (i = 0; i < clk->parent_num; i++)
218  if (clk->parent_table[i] == parent)
219  break;
220 
221  if (i == clk->parent_num)
222  return -ENODEV;
223 
224  ret = clk_reparent(clk, parent);
225  if (ret < 0)
226  return ret;
227 
228  val = __raw_readl(USBCKCR);
229  val &= ~(1 << 7);
230  val |= i << 7;
231  __raw_writel(val, USBCKCR);
232 
233  return 0;
234 }
235 
236 static struct sh_clk_ops usb24s_clk_ops = {
237  .recalc = followparent_recalc,
238  .enable = usb24s_enable,
239  .disable = usb24s_disable,
240  .set_parent = usb24s_set_parent,
241 };
242 
243 static struct clk usb24s_clk = {
244  .ops = &usb24s_clk_ops,
245  .parent_table = usb24s_parents,
246  .parent_num = ARRAY_SIZE(usb24s_parents),
247  .parent = &system_clk,
248 };
249 
250 static unsigned long usb24_recalc(struct clk *clk)
251 {
252  return clk->parent->rate /
253  ((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
254 };
255 
256 static int usb24_set_rate(struct clk *clk, unsigned long rate)
257 {
258  u32 val;
259 
260  /* closer to which ? parent->rate or parent->rate/2 */
261  val = __raw_readl(USBCKCR);
262  val &= ~(1 << 6);
263  val |= (rate > (clk->parent->rate / 4) * 3) << 6;
264  __raw_writel(val, USBCKCR);
265 
266  return 0;
267 }
268 
269 static struct sh_clk_ops usb24_clk_ops = {
270  .recalc = usb24_recalc,
271  .set_rate = usb24_set_rate,
272 };
273 
274 static struct clk usb24_clk = {
275  .ops = &usb24_clk_ops,
276  .parent = &usb24s_clk,
277 };
278 
279 /* External FSIACK/FSIBCK clock */
280 static struct clk fsiack_clk = {
281 };
282 
283 static struct clk fsibck_clk = {
284 };
285 
286 struct clk *main_clks[] = {
287  &extalr_clk,
288  &extal1_clk,
289  &extal2_clk,
290  &extal1_div2_clk,
291  &extal1_div1024_clk,
292  &extal1_div2048_clk,
293  &extal2_div2_clk,
294  &dv_clk,
295  &system_clk,
296  &system_div2_clk,
297  &r_clk,
298  &pllc0_clk,
299  &pllc1_clk,
300  &pllc1_div2_clk,
301  &usb24s_clk,
302  &usb24_clk,
303  &fsiack_clk,
304  &fsibck_clk,
305 };
306 
307 static void div4_kick(struct clk *clk)
308 {
309  unsigned long value;
310 
311  /* set KICK bit in FRQCRB to update hardware setting */
312  value = __raw_readl(FRQCRB);
313  value |= (1 << 31);
314  __raw_writel(value, FRQCRB);
315 }
316 
317 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
318  24, 32, 36, 48, 0, 72, 96, 0 };
319 
320 static struct clk_div_mult_table div4_div_mult_table = {
321  .divisors = divisors,
322  .nr_divisors = ARRAY_SIZE(divisors),
323 };
324 
325 static struct clk_div4_table div4_table = {
326  .div_mult_table = &div4_div_mult_table,
327  .kick = div4_kick,
328 };
329 
330 /* DIV6 reparent */
331 enum {
336 };
337 
338 static struct clk *hdmi_parent[] = {
339  [0] = &pllc1_div2_clk,
340  [1] = &system_clk,
341  [2] = &dv_clk
342 };
343 
344 static struct clk *vclk_parents[8] = {
345  [0] = &pllc1_div2_clk,
346  [2] = &dv_clk,
347  [3] = &usb24s_clk,
348  [4] = &extal1_div2_clk,
349  [5] = &extalr_clk,
350 };
351 
352 static struct clk *fsia_parents[] = {
353  [0] = &pllc1_div2_clk,
354  [1] = &fsiack_clk, /* external clock */
355 };
356 
357 static struct clk *fsib_parents[] = {
358  [0] = &pllc1_div2_clk,
359  [1] = &fsibck_clk, /* external clock */
360 };
361 
362 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
364  hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
366  vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
368  vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
370  fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
372  fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
373 };
374 
375 /* HDMI1/2 clock */
376 static unsigned long hdmi12_recalc(struct clk *clk)
377 {
378  u32 val = __raw_readl(HDMICKCR);
379  int shift = (int)clk->priv;
380 
381  val >>= shift;
382  val &= 0x3;
383 
384  return clk->parent->rate / (1 << val);
385 };
386 
387 static int hdmi12_set_rate(struct clk *clk, unsigned long rate)
388 {
389  u32 val, mask;
390  int i, shift;
391 
392  for (i = 0; i < 3; i++)
393  if (rate == clk->parent->rate / (1 << i))
394  goto find;
395  return -ENODEV;
396 
397 find:
398  shift = (int)clk->priv;
399 
400  val = __raw_readl(HDMICKCR);
401  mask = ~(0x3 << shift);
402  val = (val & mask) | i << shift;
403  __raw_writel(val, HDMICKCR);
404 
405  return 0;
406 };
407 
408 static struct sh_clk_ops hdmi12_clk_ops = {
409  .recalc = hdmi12_recalc,
410  .set_rate = hdmi12_set_rate,
411 };
412 
413 static struct clk hdmi1_clk = {
414  .ops = &hdmi12_clk_ops,
415  .priv = (void *)9,
416  .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
417 };
418 
419 static struct clk hdmi2_clk = {
420  .ops = &hdmi12_clk_ops,
421  .priv = (void *)11,
422  .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
423 };
424 
425 static struct clk *late_main_clks[] = {
426  &hdmi1_clk,
427  &hdmi2_clk,
428 };
429 
430 /* MSTP */
431 enum {
435 };
436 
437 struct clk div4_clks[DIV4_NR] = {
438  [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
439  [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
440  [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
441  [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
442  [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
443  [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
444  [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
445  [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
446  [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
447  [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
448  [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
449 };
450 
451 enum {
454 };
455 
456 static struct clk div6_clks[DIV6_NR] = {
457  [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
458 };
459 
460 enum {
463 
468 
472 
474 
476 };
477 
478 static struct clk mstp_clks[MSTP_NR] = {
479  [MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 28, 0), /* CEU21 */
480  [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
481  [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
482  [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
483  [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
484  [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
485  [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
486 
487  [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
488  [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
489  [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
490  [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
491  [MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
492  [MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
493  [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
494  [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
495  [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
496  [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
497  [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
498  [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
499  [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
500 
501  [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
502  [MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */
503  [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
504  [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */
505  [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
506  [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
507  [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
508  [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */
509 
510  [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
511  [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
512  [MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */
513  [MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */
514 };
515 
516 static struct clk_lookup lookups[] = {
517  /* main clocks */
518  CLKDEV_CON_ID("extalr", &extalr_clk),
519  CLKDEV_CON_ID("extal1", &extal1_clk),
520  CLKDEV_CON_ID("extal2", &extal2_clk),
521  CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
522  CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
523  CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
524  CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
525  CLKDEV_CON_ID("dv_clk", &dv_clk),
526  CLKDEV_CON_ID("system_clk", &system_clk),
527  CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
528  CLKDEV_CON_ID("r_clk", &r_clk),
529  CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
530  CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
531  CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
532  CLKDEV_CON_ID("usb24s", &usb24s_clk),
533  CLKDEV_CON_ID("hdmi1", &hdmi1_clk),
534  CLKDEV_CON_ID("hdmi2", &hdmi2_clk),
535  CLKDEV_CON_ID("video1", &div6_reparent_clks[DIV6_VCLK1]),
536  CLKDEV_CON_ID("video2", &div6_reparent_clks[DIV6_VCLK2]),
537  CLKDEV_CON_ID("fsiack", &fsiack_clk),
538  CLKDEV_CON_ID("fsibck", &fsibck_clk),
539 
540  /* DIV4 clocks */
541  CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
542  CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
543  CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
544  CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
545  CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
546  CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
547  CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
548  CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
549  CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
550  CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
551 
552  /* DIV6 clocks */
553  CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
554 
555  /* MSTP32 clocks */
556  CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
557  CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
558  CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
559  CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
560  CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
561  CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]),
562  CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
563 
564  CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
565  CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
566  CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
567  CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
568  CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
569  CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
570  CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
571  CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
572  CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
573  CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
574  CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
575  CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
576  CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
577 
578  CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
579  CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
580  CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
581  CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
582  CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
583  CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
584  CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
585  CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
586 
587  CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
588 
589  /* ICK */
590  CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
591  CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]),
592  CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
593  CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]),
594  CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk),
595  CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
596 
597  CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
598  CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
599 };
600 
602 {
603  int k, ret = 0;
604 
605  /* detect system clock parent */
606  if (md_ck & MD_CK1)
607  system_clk.parent = &extal1_div2_clk;
608  else
609  system_clk.parent = &extal1_clk;
610 
611  /* detect RCLK parent */
612  switch (md_ck & (MD_CK2 | MD_CK1)) {
613  case MD_CK2 | MD_CK1:
614  r_clk.parent = &extal1_div2048_clk;
615  break;
616  case MD_CK2:
617  r_clk.parent = &extal1_div1024_clk;
618  break;
619  case MD_CK1:
620  default:
621  r_clk.parent = &extalr_clk;
622  break;
623  }
624 
625  for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
626  ret = clk_register(main_clks[k]);
627 
628  if (!ret)
629  ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
630 
631  if (!ret)
632  ret = sh_clk_div6_register(div6_clks, DIV6_NR);
633 
634  if (!ret)
635  ret = sh_clk_div6_reparent_register(div6_reparent_clks,
637 
638  if (!ret)
639  ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
640 
641  for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
642  ret = clk_register(late_main_clks[k]);
643 
644  clkdev_add_table(lookups, ARRAY_SIZE(lookups));
645 
646  if (!ret)
648  else
649  panic("failed to setup r8a7740 clocks\n");
650 }