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clock-sh7366.c File Reference
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/clock.h>

Go to the source code of this file.

Macros

#define FRQCR   0xa4150000
 
#define VCLKCR   0xa4150004
 
#define SCLKACR   0xa4150008
 
#define SCLKBCR   0xa415000c
 
#define PLLCR   0xa4150024
 
#define MSTPCR0   0xa4150030
 
#define MSTPCR1   0xa4150034
 
#define MSTPCR2   0xa4150038
 
#define DLLFRQ   0xa4150050
 
#define DIV4(_reg, _bit, _mask, _flags)   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
#define MSTP(_parent, _reg, _bit, _flags)   SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
 

Enumerations

enum  {
  DIV4_I, DIV4_U, DIV4_SH, DIV4_B,
  DIV4_B3, DIV4_P, DIV4_SIUA, DIV4_SIUB,
  DIV4_NR
}
 
enum  { DIV6_V, DIV6_NR }
 
enum  {
  MSTP031, MSTP030, MSTP029, MSTP028,
  MSTP026, MSTP023, MSTP022, MSTP021,
  MSTP020, MSTP019, MSTP018, MSTP017,
  MSTP016, MSTP015, MSTP014, MSTP013,
  MSTP012, MSTP011, MSTP010, MSTP007,
  MSTP006, MSTP005, MSTP002, MSTP001,
  MSTP109, MSTP100, MSTP227, MSTP226,
  MSTP224, MSTP223, MSTP222, MSTP218,
  MSTP217, MSTP211, MSTP207, MSTP205,
  MSTP204, MSTP203, MSTP202, MSTP201,
  MSTP200, MSTP_NR
}
 

Functions

int __init arch_clk_init (void)
 

Variables

struct clk extal_clk
 
struct clkmain_clks []
 
struct clk div4_clks [DIV4_NR]
 
struct clk div6_clks [DIV6_NR]
 

Macro Definition Documentation

#define DIV4 (   _reg,
  _bit,
  _mask,
  _flags 
)    SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

Definition at line 120 of file clock-sh7366.c.

#define DLLFRQ   0xa4150050

Definition at line 36 of file clock-sh7366.c.

#define FRQCR   0xa4150000

Definition at line 28 of file clock-sh7366.c.

#define MSTP (   _parent,
  _reg,
  _bit,
  _flags 
)    SH_CLK_MSTP32(_parent, _reg, _bit, _flags)

Definition at line 140 of file clock-sh7366.c.

#define MSTPCR0   0xa4150030

Definition at line 33 of file clock-sh7366.c.

#define MSTPCR1   0xa4150034

Definition at line 34 of file clock-sh7366.c.

#define MSTPCR2   0xa4150038

Definition at line 35 of file clock-sh7366.c.

#define PLLCR   0xa4150024

Definition at line 32 of file clock-sh7366.c.

#define SCLKACR   0xa4150008

Definition at line 30 of file clock-sh7366.c.

#define SCLKBCR   0xa415000c

Definition at line 31 of file clock-sh7366.c.

#define VCLKCR   0xa4150004

Definition at line 29 of file clock-sh7366.c.

Enumeration Type Documentation

anonymous enum
Enumerator:
DIV4_I 
DIV4_U 
DIV4_SH 
DIV4_B 
DIV4_B3 
DIV4_P 
DIV4_SIUA 
DIV4_SIUB 
DIV4_NR 

Definition at line 117 of file clock-sh7366.c.

anonymous enum
Enumerator:
DIV6_V 
DIV6_NR 

Definition at line 134 of file clock-sh7366.c.

anonymous enum
Enumerator:
MSTP031 
MSTP030 
MSTP029 
MSTP028 
MSTP026 
MSTP023 
MSTP022 
MSTP021 
MSTP020 
MSTP019 
MSTP018 
MSTP017 
MSTP016 
MSTP015 
MSTP014 
MSTP013 
MSTP012 
MSTP011 
MSTP010 
MSTP007 
MSTP006 
MSTP005 
MSTP002 
MSTP001 
MSTP109 
MSTP100 
MSTP227 
MSTP226 
MSTP224 
MSTP223 
MSTP222 
MSTP218 
MSTP217 
MSTP211 
MSTP207 
MSTP205 
MSTP204 
MSTP203 
MSTP202 
MSTP201 
MSTP200 
MSTP_NR 

Definition at line 143 of file clock-sh7366.c.

Function Documentation

int __init arch_clk_init ( void  )

Definition at line 257 of file clock-sh7366.c.

Variable Documentation

struct clk div4_clks[DIV4_NR]
Initial value:
= {
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
}

Definition at line 123 of file clock-sh7366.c.

struct clk div6_clks[DIV6_NR]
Initial value:
= {
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
}

Definition at line 136 of file clock-sh7366.c.

struct clk extal_clk
Initial value:
= {
.rate = 33333333,
}

Definition at line 47 of file clock-sh7366.c.

struct clk* main_clks[]
Initial value:
= {
&r_clk,
&dll_clk,
&pll_clk,
}

Definition at line 96 of file clock-sh7366.c.