#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/edac.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/gfp.h>
#include "edac_core.h"
#include "edac_module.h"

Data Structures
struct	cpc925_mc_pdata

struct	cpc925_dev_info

Macros
#define	CPC925_EDAC_REVISION " Ver: 1.0.0"

#define	CPC925_EDAC_MOD_STR "cpc925_edac"

#define	cpc925_printk(level, fmt, arg...) edac_printk(level, "CPC925", fmt, ##arg)

#define	cpc925_mc_printk(mci, level, fmt, arg...) edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)

#define	CPC925_BITS_PER_REG 32

#define	CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))

#define	CPC925_CPU_ERR_DEV "cpu"

#define	CPC925_HT_LINK_DEV "htlink"

#define	CPC925_REF_FREQ 0xFA69

#define	CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */

#define	CPC925_NR_CSROWS 8

#define	REG_APIMASK_OFFSET 0x30070

#define	APIMASK_ADI(n) CPC925_BIT(((n)+1))

#define	REG_APIEXCP_OFFSET 0x30060

#define	REG_MBCR_OFFSET 0x2190

#define	MBCR_64BITCFG_SHIFT 23

#define	MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT)

#define	MBCR_64BITBUS_SHIFT 22

#define	MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT)

#define	REG_MBMR_OFFSET 0x21C0

#define	MBMR_MODE_MAX_VALUE 0xF

#define	MBMR_MODE_SHIFT 25

#define	MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)

#define	MBMR_BBA_SHIFT 24

#define	MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT)

#define	REG_MBBAR_OFFSET 0x21D0

#define	MBBAR_BBA_MAX_VALUE 0xFF

#define	MBBAR_BBA_SHIFT 24

#define	MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)

#define	REG_MSCR_OFFSET 0x2400

#define	MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/

#define	MSCR_BACKGR_SCRUB 0x40000000 /* 01 */

#define	MSCR_SI_SHIFT 16 /* si - bit8:15*/

#define	MSCR_SI_MAX_VALUE 0xFF

#define	MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)

#define	REG_MSRSR_OFFSET 0x2410

#define	REG_MSRER_OFFSET 0x2420

#define	REG_MSPR_OFFSET 0x2430

#define	REG_MCCR_OFFSET 0x2440

#define	REG_MCRER_OFFSET 0x2450

#define	REG_MEAR_OFFSET 0x2460

#define	MEAR_BCNT_MAX_VALUE 0x3

#define	MEAR_BCNT_SHIFT 30

#define	MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)

#define	MEAR_RANK_MAX_VALUE 0x7

#define	MEAR_RANK_SHIFT 27

#define	MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)

#define	MEAR_COL_MAX_VALUE 0x7FF

#define	MEAR_COL_SHIFT 16

#define	MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)

#define	MEAR_BANK_MAX_VALUE 0x3

#define	MEAR_BANK_SHIFT 14

#define	MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)

#define	MEAR_ROW_MASK 0x00003FFF

#define	REG_MESR_OFFSET 0x2470

#define	MESR_ECC_SYN_H_MASK 0xFF00

#define	MESR_ECC_SYN_L_MASK 0x00FF

#define	REG_MMCR_OFFSET 0x2500

#define	REG_ERRCTRL_OFFSET 0x70140

#define	REG_LINKCTRL_OFFSET 0x70110

#define	REG_LINKERR_OFFSET 0x70120

#define	REG_BRGCTRL_OFFSET 0x70300

Enumerations
enum	apimask_bits { APIMASK_DART = CPC925_BIT(0), APIMASK_ADI0 = CPC925_BIT(1), APIMASK_ADI1 = CPC925_BIT(2), APIMASK_STAT = CPC925_BIT(3), APIMASK_DERR = CPC925_BIT(4), APIMASK_ADRS0 = CPC925_BIT(5), APIMASK_ADRS1 = CPC925_BIT(6), APIMASK_ECC_UE_H = CPC925_BIT(8), APIMASK_ECC_CE_H = CPC925_BIT(9), APIMASK_ECC_UE_L = CPC925_BIT(10), APIMASK_ECC_CE_L = CPC925_BIT(11), CPU_MASK_ENABLE, ECC_MASK_ENABLE }

enum	apiexcp_bits { APIEXCP_DART = CPC925_BIT(0), APIEXCP_ADI0 = CPC925_BIT(1), APIEXCP_ADI1 = CPC925_BIT(2), APIEXCP_STAT = CPC925_BIT(3), APIEXCP_DERR = CPC925_BIT(4), APIEXCP_ADRS0 = CPC925_BIT(5), APIEXCP_ADRS1 = CPC925_BIT(6), APIEXCP_ECC_UE_H = CPC925_BIT(8), APIEXCP_ECC_CE_H = CPC925_BIT(9), APIEXCP_ECC_UE_L = CPC925_BIT(10), APIEXCP_ECC_CE_L = CPC925_BIT(11), CPU_EXCP_DETECTED, UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H \| APIEXCP_ECC_UE_L), CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H \| APIEXCP_ECC_CE_L), ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED \| CECC_EXCP_DETECTED) }

enum	mccr_bits { MCCR_ECC_EN = CPC925_BIT(0) }

enum	mmcr_bits { MMCR_REG_DIMM_MODE = CPC925_BIT(3) }

enum	errctrl_bits { ERRCTRL_SERR_NF = CPC925_BIT(0), ERRCTRL_CRC_NF = CPC925_BIT(1), ERRCTRL_RSP_NF = CPC925_BIT(2), ERRCTRL_EOC_NF = CPC925_BIT(3), ERRCTRL_OVF_NF = CPC925_BIT(4), ERRCTRL_PROT_NF = CPC925_BIT(5), ERRCTRL_RSP_ERR = CPC925_BIT(6), ERRCTRL_CHN_FAL = CPC925_BIT(7), HT_ERRCTRL_ENABLE, HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR \| ERRCTRL_CHN_FAL) }

enum	linkctrl_bits { LINKCTRL_CRC_ERR = (CPC925_BIT(22) \| CPC925_BIT(23)), LINKCTRL_LINK_FAIL = CPC925_BIT(27), HT_LINKCTRL_DETECTED = (LINKCTRL_CRC_ERR \| LINKCTRL_LINK_FAIL) }

enum	linkerr_bits { LINKERR_EOC_ERR = CPC925_BIT(17), LINKERR_OVF_ERR = CPC925_BIT(18), LINKERR_PROT_ERR = CPC925_BIT(19), HT_LINKERR_DETECTED }

enum	brgctrl_bits { BRGCTRL_DETSERR = CPC925_BIT(0), BRGCTRL_SECBUSRESET = CPC925_BIT(9) }

Functions
	module_init (cpc925_edac_init)

	module_exit (cpc925_edac_exit)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Cao Qingtao <[email protected]>")

	MODULE_DESCRIPTION ("IBM CPC925 Bridge and MC EDAC kernel module")

Macro Definition Documentation

#define APIMASK_ADI ( n ) CPC925_BIT(((n)+1))

Definition at line 93 of file cpc925_edac.c.

#define CPC925_BIT ( nr ) (1UL << (CPC925_BITS_PER_REG - 1 - nr))

Definition at line 47 of file cpc925_edac.c.

#define CPC925_BITS_PER_REG 32

Definition at line 46 of file cpc925_edac.c.

#define CPC925_CPU_ERR_DEV "cpu"

Definition at line 53 of file cpc925_edac.c.

#define CPC925_EDAC_MOD_STR "cpc925_edac"

Definition at line 34 of file cpc925_edac.c.

#define CPC925_EDAC_REVISION " Ver: 1.0.0"

Definition at line 33 of file cpc925_edac.c.

#define CPC925_HT_LINK_DEV "htlink"

Definition at line 54 of file cpc925_edac.c.

#define cpc925_mc_printk	(	mci,
		level,
		fmt,
		arg...
	)	edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)

Definition at line 39 of file cpc925_edac.c.

#define CPC925_NR_CSROWS 8

Definition at line 59 of file cpc925_edac.c.

#define cpc925_printk	(	level,
		fmt,
		arg...
	)	edac_printk(level, "CPC925", fmt, ##arg)

Definition at line 36 of file cpc925_edac.c.

#define CPC925_REF_FREQ 0xFA69

Definition at line 57 of file cpc925_edac.c.

#define CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */

Definition at line 58 of file cpc925_edac.c.

#define MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)

Definition at line 146 of file cpc925_edac.c.

#define MBBAR_BBA_MAX_VALUE 0xFF

Definition at line 144 of file cpc925_edac.c.

#define MBBAR_BBA_SHIFT 24

Definition at line 145 of file cpc925_edac.c.

#define MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT)

Definition at line 128 of file cpc925_edac.c.

#define MBCR_64BITBUS_SHIFT 22

Definition at line 127 of file cpc925_edac.c.

#define MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT)

Definition at line 126 of file cpc925_edac.c.

#define MBCR_64BITCFG_SHIFT 23

Definition at line 125 of file cpc925_edac.c.

#define MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT)

Definition at line 138 of file cpc925_edac.c.

#define MBMR_BBA_SHIFT 24

Definition at line 137 of file cpc925_edac.c.

#define MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)

Definition at line 136 of file cpc925_edac.c.

#define MBMR_MODE_MAX_VALUE 0xF

Definition at line 134 of file cpc925_edac.c.

#define MBMR_MODE_SHIFT 25

Definition at line 135 of file cpc925_edac.c.

#define MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)

Definition at line 201 of file cpc925_edac.c.

#define MEAR_BANK_MAX_VALUE 0x3

Definition at line 199 of file cpc925_edac.c.

#define MEAR_BANK_SHIFT 14

Definition at line 200 of file cpc925_edac.c.

#define MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)

Definition at line 192 of file cpc925_edac.c.

#define MEAR_BCNT_MAX_VALUE 0x3

Definition at line 190 of file cpc925_edac.c.

#define MEAR_BCNT_SHIFT 30

Definition at line 191 of file cpc925_edac.c.

#define MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)

Definition at line 198 of file cpc925_edac.c.

#define MEAR_COL_MAX_VALUE 0x7FF

Definition at line 196 of file cpc925_edac.c.

#define MEAR_COL_SHIFT 16

Definition at line 197 of file cpc925_edac.c.

#define MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)

Definition at line 195 of file cpc925_edac.c.

#define MEAR_RANK_MAX_VALUE 0x7

Definition at line 193 of file cpc925_edac.c.

#define MEAR_RANK_SHIFT 27

Definition at line 194 of file cpc925_edac.c.

#define MEAR_ROW_MASK 0x00003FFF

Definition at line 202 of file cpc925_edac.c.

#define MESR_ECC_SYN_H_MASK 0xFF00

Definition at line 208 of file cpc925_edac.c.

#define MESR_ECC_SYN_L_MASK 0x00FF

Definition at line 209 of file cpc925_edac.c.

#define MSCR_BACKGR_SCRUB 0x40000000 /* 01 */

Definition at line 153 of file cpc925_edac.c.

#define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/

Definition at line 152 of file cpc925_edac.c.

#define MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)

Definition at line 156 of file cpc925_edac.c.

#define MSCR_SI_MAX_VALUE 0xFF

Definition at line 155 of file cpc925_edac.c.

#define MSCR_SI_SHIFT 16 /* si - bit8:15*/

Definition at line 154 of file cpc925_edac.c.

#define REG_APIEXCP_OFFSET 0x30060

Definition at line 98 of file cpc925_edac.c.

#define REG_APIMASK_OFFSET 0x30070

Definition at line 72 of file cpc925_edac.c.

#define REG_BRGCTRL_OFFSET 0x70300

Definition at line 270 of file cpc925_edac.c.

#define REG_ERRCTRL_OFFSET 0x70140

Definition at line 225 of file cpc925_edac.c.

#define REG_LINKCTRL_OFFSET 0x70110

Definition at line 246 of file cpc925_edac.c.

#define REG_LINKERR_OFFSET 0x70120

Definition at line 257 of file cpc925_edac.c.

#define REG_MBBAR_OFFSET 0x21D0

Definition at line 143 of file cpc925_edac.c.

#define REG_MBCR_OFFSET 0x2190

Definition at line 124 of file cpc925_edac.c.

#define REG_MBMR_OFFSET 0x21C0

Definition at line 133 of file cpc925_edac.c.

#define REG_MCCR_OFFSET 0x2440

Definition at line 176 of file cpc925_edac.c.

#define REG_MCRER_OFFSET 0x2450

Definition at line 184 of file cpc925_edac.c.

#define REG_MEAR_OFFSET 0x2460

Definition at line 189 of file cpc925_edac.c.

#define REG_MESR_OFFSET 0x2470

Definition at line 207 of file cpc925_edac.c.

#define REG_MMCR_OFFSET 0x2500

Definition at line 214 of file cpc925_edac.c.

#define REG_MSCR_OFFSET 0x2400

Definition at line 151 of file cpc925_edac.c.

#define REG_MSPR_OFFSET 0x2430

Definition at line 171 of file cpc925_edac.c.

#define REG_MSRER_OFFSET 0x2420

Definition at line 166 of file cpc925_edac.c.

#define REG_MSRSR_OFFSET 0x2410

Definition at line 161 of file cpc925_edac.c.

Enumeration Type Documentation

enum apiexcp_bits

Enumerator:

APIEXCP_DART
APIEXCP_ADI0
APIEXCP_ADI1
APIEXCP_STAT
APIEXCP_DERR
APIEXCP_ADRS0
APIEXCP_ADRS1
APIEXCP_ECC_UE_H
APIEXCP_ECC_CE_H
APIEXCP_ECC_UE_L
APIEXCP_ECC_CE_L
CPU_EXCP_DETECTED
UECC_EXCP_DETECTED
CECC_EXCP_DETECTED
ECC_EXCP_DETECTED

Definition at line 99 of file cpc925_edac.c.

enum apimask_bits

Enumerator:

APIMASK_DART
APIMASK_ADI0
APIMASK_ADI1
APIMASK_STAT
APIMASK_DERR
APIMASK_ADRS0
APIMASK_ADRS1
APIMASK_ECC_UE_H
APIMASK_ECC_CE_H
APIMASK_ECC_UE_L
APIMASK_ECC_CE_L
CPU_MASK_ENABLE
ECC_MASK_ENABLE

Definition at line 73 of file cpc925_edac.c.

enum brgctrl_bits

Enumerator:

BRGCTRL_DETSERR
BRGCTRL_SECBUSRESET

Definition at line 271 of file cpc925_edac.c.

enum errctrl_bits

Enumerator:

ERRCTRL_SERR_NF
ERRCTRL_CRC_NF
ERRCTRL_RSP_NF
ERRCTRL_EOC_NF
ERRCTRL_OVF_NF
ERRCTRL_PROT_NF
ERRCTRL_RSP_ERR
ERRCTRL_CHN_FAL
HT_ERRCTRL_ENABLE
HT_ERRCTRL_DETECTED