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cs5520.c
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1 /*
2  * IDE tuning and bus mastering support for the CS5510/CS5520
3  * chipsets
4  *
5  * The CS5510/CS5520 are slightly unusual devices. Unlike the
6  * typical IDE controllers they do bus mastering with the drive in
7  * PIO mode and smarter silicon.
8  *
9  * The practical upshot of this is that we must always tune the
10  * drive for the right PIO mode. We must also ignore all the blacklists
11  * and the drive bus mastering DMA information.
12  *
13  * *** This driver is strictly experimental ***
14  *
15  * (c) Copyright Red Hat Inc 2002
16  *
17  * This program is free software; you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation; either version 2, or (at your option) any
20  * later version.
21  *
22  * This program is distributed in the hope that it will be useful, but
23  * WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25  * General Public License for more details.
26  *
27  * For the avoidance of doubt the "preferred form" of this code is one which
28  * is in an open non patent encumbered format. Where cryptographic key signing
29  * forms part of the process of creating an executable the information
30  * including keys needed to generate an equivalently functional executable
31  * are deemed to be part of the source code.
32  *
33  */
34 
35 #include <linux/module.h>
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/ide.h>
41 #include <linux/dma-mapping.h>
42 
43 #define DRV_NAME "cs5520"
44 
45 struct pio_clocks
46 {
47  int address;
48  int assert;
49  int recovery;
50 };
51 
52 static struct pio_clocks cs5520_pio_clocks[]={
53  {3, 6, 11},
54  {2, 5, 6},
55  {1, 4, 3},
56  {1, 3, 2},
57  {1, 2, 1}
58 };
59 
60 static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
61 {
62  struct pci_dev *pdev = to_pci_dev(hwif->dev);
63  int controller = drive->dn > 1 ? 1 : 0;
64  const u8 pio = drive->pio_mode - XFER_PIO_0;
65 
66  /* 8bit CAT/CRT - 8bit command timing for channel */
67  pci_write_config_byte(pdev, 0x62 + controller,
68  (cs5520_pio_clocks[pio].recovery << 4) |
69  (cs5520_pio_clocks[pio].assert));
70 
71  /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
72 
73  /* FIXME: should these use address ? */
74  /* Data read timing */
75  pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
76  (cs5520_pio_clocks[pio].recovery << 4) |
77  (cs5520_pio_clocks[pio].assert));
78  /* Write command timing */
79  pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
80  (cs5520_pio_clocks[pio].recovery << 4) |
81  (cs5520_pio_clocks[pio].assert));
82 }
83 
84 static void cs5520_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85 {
86  printk(KERN_ERR "cs55x0: bad ide timing.\n");
87 
88  drive->pio_mode = XFER_PIO_0 + 0;
89  cs5520_set_pio_mode(hwif, drive);
90 }
91 
92 static const struct ide_port_ops cs5520_port_ops = {
93  .set_pio_mode = cs5520_set_pio_mode,
94  .set_dma_mode = cs5520_set_dma_mode,
95 };
96 
97 static const struct ide_port_info cyrix_chipset __devinitconst = {
98  .name = DRV_NAME,
99  .enablebits = { { 0x60, 0x01, 0x01 }, { 0x60, 0x02, 0x02 } },
100  .port_ops = &cs5520_port_ops,
101  .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_CS5520,
102  .pio_mask = ATA_PIO4,
103 };
104 
105 /*
106  * The 5510/5520 are a bit weird. They don't quite set up the way
107  * the PCI helper layer expects so we must do much of the set up
108  * work longhand.
109  */
110 
111 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
112 {
113  const struct ide_port_info *d = &cyrix_chipset;
114  struct ide_hw hw[2], *hws[] = { NULL, NULL };
115 
116  ide_setup_pci_noise(dev, d);
117 
118  /* We must not grab the entire device, it has 'ISA' space in its
119  * BARS too and we will freak out other bits of the kernel
120  */
121  if (pci_enable_device_io(dev)) {
122  printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
123  return -ENODEV;
124  }
125  pci_set_master(dev);
126  if (pci_set_dma_mask(dev, DMA_BIT_MASK(32))) {
127  printk(KERN_WARNING "%s: No suitable DMA available.\n",
128  d->name);
129  return -ENODEV;
130  }
131 
132  /*
133  * Now the chipset is configured we can let the core
134  * do all the device setup for us
135  */
136 
137  ide_pci_setup_ports(dev, d, &hw[0], &hws[0]);
138  hw[0].irq = 14;
139  hw[1].irq = 15;
140 
141  return ide_host_add(d, hws, 2, NULL);
142 }
143 
144 static const struct pci_device_id cs5520_pci_tbl[] = {
145  { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
146  { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
147  { 0, },
148 };
149 MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
150 
151 static struct pci_driver cs5520_pci_driver = {
152  .name = "Cyrix_IDE",
153  .id_table = cs5520_pci_tbl,
154  .probe = cs5520_init_one,
155  .suspend = ide_pci_suspend,
156  .resume = ide_pci_resume,
157 };
158 
159 static int __init cs5520_ide_init(void)
160 {
161  return ide_pci_register_driver(&cs5520_pci_driver);
162 }
163 
164 module_init(cs5520_ide_init);
165 
166 MODULE_AUTHOR("Alan Cox");
167 MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
168 MODULE_LICENSE("GPL");