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22 #include <linux/pci.h>
23 #include <linux/i2c.h>
25 #include <linux/videodev2.h>
26 #include <linux/kdev_t.h>
45 #define CX88_VERSION "0.0.9"
49 #define CX88_MAXBOARDS 8
52 #define MAX_CX88_INPUT 8
58 #define CX88_NORMS (V4L2_STD_ALL \
60 & ~V4L2_STD_NTSC_M_KR \
63 #define FORMAT_FLAGS_PACKED 0x01
64 #define FORMAT_FLAGS_PLANAR 0x02
66 #define VBI_LINE_COUNT 17
67 #define VBI_LINE_LENGTH 2048
69 #define AUD_RDS_LINES 4
72 #define SHADOW_AUD_VOL_CTL 1
73 #define SHADOW_AUD_BAL_CTL 2
149 #define CX88_BOARD_NOAUTO UNSET
150 #define CX88_BOARD_UNKNOWN 0
151 #define CX88_BOARD_HAUPPAUGE 1
152 #define CX88_BOARD_GDI 2
153 #define CX88_BOARD_PIXELVIEW 3
154 #define CX88_BOARD_ATI_WONDER_PRO 4
155 #define CX88_BOARD_WINFAST2000XP_EXPERT 5
156 #define CX88_BOARD_AVERTV_STUDIO_303 6
157 #define CX88_BOARD_MSI_TVANYWHERE_MASTER 7
158 #define CX88_BOARD_WINFAST_DV2000 8
159 #define CX88_BOARD_LEADTEK_PVR2000 9
160 #define CX88_BOARD_IODATA_GVVCP3PCI 10
161 #define CX88_BOARD_PROLINK_PLAYTVPVR 11
162 #define CX88_BOARD_ASUS_PVR_416 12
163 #define CX88_BOARD_MSI_TVANYWHERE 13
164 #define CX88_BOARD_KWORLD_DVB_T 14
165 #define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1 15
166 #define CX88_BOARD_KWORLD_LTV883 16
167 #define CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q 17
168 #define CX88_BOARD_HAUPPAUGE_DVB_T1 18
169 #define CX88_BOARD_CONEXANT_DVB_T1 19
170 #define CX88_BOARD_PROVIDEO_PV259 20
171 #define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS 21
172 #define CX88_BOARD_PCHDTV_HD3000 22
173 #define CX88_BOARD_DNTV_LIVE_DVB_T 23
174 #define CX88_BOARD_HAUPPAUGE_ROSLYN 24
175 #define CX88_BOARD_DIGITALLOGIC_MEC 25
176 #define CX88_BOARD_IODATA_GVBCTV7E 26
177 #define CX88_BOARD_PIXELVIEW_PLAYTV_ULTRA_PRO 27
178 #define CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T 28
179 #define CX88_BOARD_ADSTECH_DVB_T_PCI 29
180 #define CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1 30
181 #define CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD 31
182 #define CX88_BOARD_AVERMEDIA_ULTRATV_MC_550 32
183 #define CX88_BOARD_KWORLD_VSTREAM_EXPERT_DVD 33
184 #define CX88_BOARD_ATI_HDTVWONDER 34
185 #define CX88_BOARD_WINFAST_DTV1000 35
186 #define CX88_BOARD_AVERTV_303 36
187 #define CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1 37
188 #define CX88_BOARD_HAUPPAUGE_NOVASE2_S1 38
189 #define CX88_BOARD_KWORLD_DVBS_100 39
190 #define CX88_BOARD_HAUPPAUGE_HVR1100 40
191 #define CX88_BOARD_HAUPPAUGE_HVR1100LP 41
192 #define CX88_BOARD_DNTV_LIVE_DVB_T_PRO 42
193 #define CX88_BOARD_KWORLD_DVB_T_CX22702 43
194 #define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL 44
195 #define CX88_BOARD_KWORLD_HARDWARE_MPEG_TV_XPERT 45
196 #define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID 46
197 #define CX88_BOARD_PCHDTV_HD5500 47
198 #define CX88_BOARD_KWORLD_MCE200_DELUXE 48
199 #define CX88_BOARD_PIXELVIEW_PLAYTV_P7000 49
200 #define CX88_BOARD_NPGTECH_REALTV_TOP10FM 50
201 #define CX88_BOARD_WINFAST_DTV2000H 51
202 #define CX88_BOARD_GENIATECH_DVBS 52
203 #define CX88_BOARD_HAUPPAUGE_HVR3000 53
204 #define CX88_BOARD_NORWOOD_MICRO 54
205 #define CX88_BOARD_TE_DTV_250_OEM_SWANN 55
206 #define CX88_BOARD_HAUPPAUGE_HVR1300 56
207 #define CX88_BOARD_ADSTECH_PTV_390 57
208 #define CX88_BOARD_PINNACLE_PCTV_HD_800i 58
209 #define CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO 59
210 #define CX88_BOARD_PINNACLE_HYBRID_PCTV 60
211 #define CX88_BOARD_WINFAST_TV2000_XP_GLOBAL 61
212 #define CX88_BOARD_POWERCOLOR_REAL_ANGEL 62
213 #define CX88_BOARD_GENIATECH_X8000_MT 63
214 #define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO 64
215 #define CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD 65
216 #define CX88_BOARD_PROLINK_PV_8000GT 66
217 #define CX88_BOARD_KWORLD_ATSC_120 67
218 #define CX88_BOARD_HAUPPAUGE_HVR4000 68
219 #define CX88_BOARD_HAUPPAUGE_HVR4000LITE 69
220 #define CX88_BOARD_TEVII_S460 70
221 #define CX88_BOARD_OMICOM_SS4_PCI 71
222 #define CX88_BOARD_TBS_8920 72
223 #define CX88_BOARD_TEVII_S420 73
224 #define CX88_BOARD_PROLINK_PV_GLOBAL_XTREME 74
225 #define CX88_BOARD_PROF_7300 75
226 #define CX88_BOARD_SATTRADE_ST4200 76
227 #define CX88_BOARD_TBS_8910 77
228 #define CX88_BOARD_PROF_6200 78
229 #define CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII 79
230 #define CX88_BOARD_HAUPPAUGE_IRONLY 80
231 #define CX88_BOARD_WINFAST_DTV1800H 81
232 #define CX88_BOARD_WINFAST_DTV2000H_J 82
233 #define CX88_BOARD_PROF_7301 83
234 #define CX88_BOARD_SAMSUNG_SMT_7020 84
235 #define CX88_BOARD_TWINHAN_VP1027_DVBS 85
236 #define CX88_BOARD_TEVII_S464 86
237 #define CX88_BOARD_WINFAST_DTV2000H_PLUS 87
238 #define CX88_BOARD_WINFAST_DTV1800H_XC4000 88
239 #define CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36 89
240 #define CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43 90
299 #define INPUT(nr) (core->board.input[nr])
304 #define RESOURCE_OVERLAY 1
305 #define RESOURCE_VIDEO 2
306 #define RESOURCE_VBI 4
308 #define BUFFER_TIMEOUT msecs_to_jiffies(2000)
366 #if defined(CONFIG_VIDEO_CX88_DVB) || defined(CONFIG_VIDEO_CX88_DVB_MODULE)
408 #define call_hw(core, grpid, o, f, args...) \
410 if (!core->i2c_rc) { \
411 if (core->gate_ctrl) \
412 core->gate_ctrl(core, 1); \
413 v4l2_device_call_all(&core->v4l2_dev, grpid, o, f, ##args); \
414 if (core->gate_ctrl) \
415 core->gate_ctrl(core, 0); \
419 #define call_all(core, o, f, args...) call_hw(core, 0, o, f, ##args)
421 #define WM8775_GID (1 << 0)
423 #define wm8775_s_ctrl(core, id, val) \
425 struct v4l2_ctrl *ctrl_ = \
426 v4l2_ctrl_find(core->sd_wm8775->ctrl_handler, id); \
427 if (ctrl_ && !core->i2c_rc) { \
428 if (core->gate_ctrl) \
429 core->gate_ctrl(core, 1); \
430 v4l2_ctrl_s_ctrl(ctrl_, val); \
431 if (core->gate_ctrl) \
432 core->gate_ctrl(core, 0); \
436 #define wm8775_g_ctrl(core, id) \
438 struct v4l2_ctrl *ctrl_ = \
439 v4l2_ctrl_find(core->sd_wm8775->ctrl_handler, id); \
441 if (ctrl_ && !core->i2c_rc) { \
442 if (core->gate_ctrl) \
443 core->gate_ctrl(core, 1); \
444 val = v4l2_ctrl_g_ctrl(ctrl_); \
445 if (core->gate_ctrl) \
446 core->gate_ctrl(core, 0); \
565 #if defined(CONFIG_VIDEO_CX88_BLACKBIRD) || \
566 defined(CONFIG_VIDEO_CX88_BLACKBIRD_MODULE)
571 unsigned char mpeg_active;
577 #if defined(CONFIG_VIDEO_CX88_DVB) || defined(CONFIG_VIDEO_CX88_DVB_MODULE)
582 #if defined(CONFIG_VIDEO_CX88_VP3054) || \
583 defined(CONFIG_VIDEO_CX88_VP3054_MODULE)
598 #define cx_read(reg) readl(core->lmmio + ((reg)>>2))
599 #define cx_write(reg,value) writel((value), core->lmmio + ((reg)>>2))
600 #define cx_writeb(reg,value) writeb((value), core->bmmio + (reg))
602 #define cx_andor(reg,mask,value) \
603 writel((readl(core->lmmio+((reg)>>2)) & ~(mask)) |\
604 ((value) & (mask)), core->lmmio+((reg)>>2))
605 #define cx_set(reg,bit) cx_andor((reg),(bit),(bit))
606 #define cx_clear(reg,bit) cx_andor((reg),(bit),0)
608 #define cx_wait(d) { if (need_resched()) schedule(); else udelay(d); }
611 #define cx_sread(sreg) (core->shadow[sreg])
612 #define cx_swrite(sreg,reg,value) \
613 (core->shadow[sreg] = value, \
614 writel(core->shadow[sreg], core->lmmio + ((reg)>>2)))
615 #define cx_sandor(sreg,reg,mask,value) \
616 (core->shadow[sreg] = (core->shadow[sreg] & ~(mask)) | ((value) & (mask)), \
617 writel(core->shadow[sreg], core->lmmio + ((reg)>>2)))
634 unsigned int top_offset,
unsigned int bottom_offset,
635 unsigned int bpl,
unsigned int padding,
unsigned int lines);
639 unsigned int lines,
unsigned int lpi);
650 unsigned int bpl,
u32 risc);