#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/cpufreq.h>
#include <linux/mmc/host.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/edma.h>
#include <linux/mmc/mmc.h>
#include <linux/platform_data/mmc-davinci.h>

Data Structures
struct	mmc_davinci_host

Macros
#define	DAVINCI_MMCCTL 0x00 /* Control Register */

#define	DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */

#define	DAVINCI_MMCST0 0x08 /* Status Register 0 */

#define	DAVINCI_MMCST1 0x0C /* Status Register 1 */

#define	DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */

#define	DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */

#define	DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */

#define	DAVINCI_MMCBLEN 0x1C /* Block Length Register */

#define	DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */

#define	DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */

#define	DAVINCI_MMCDRR 0x28 /* Data Receive Register */

#define	DAVINCI_MMCDXR 0x2C /* Data Transmit Register */

#define	DAVINCI_MMCCMD 0x30 /* Command Register */

#define	DAVINCI_MMCARGHL 0x34 /* Argument Register */

#define	DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */

#define	DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */

#define	DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */

#define	DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */

#define	DAVINCI_MMCDRSP 0x48 /* Data Response Register */

#define	DAVINCI_MMCETOK 0x4C

#define	DAVINCI_MMCCIDX 0x50 /* Command Index Register */

#define	DAVINCI_MMCCKC 0x54

#define	DAVINCI_MMCTORC 0x58

#define	DAVINCI_MMCTODC 0x5C

#define	DAVINCI_MMCBLNC 0x60

#define	DAVINCI_SDIOCTL 0x64

#define	DAVINCI_SDIOST0 0x68

#define	DAVINCI_SDIOIEN 0x6C

#define	DAVINCI_SDIOIST 0x70

#define	DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */

#define	MMCCTL_DATRST (1 << 0)

#define	MMCCTL_CMDRST (1 << 1)

#define	MMCCTL_WIDTH_8_BIT (1 << 8)

#define	MMCCTL_WIDTH_4_BIT (1 << 2)

#define	MMCCTL_DATEG_DISABLED (0 << 6)

#define	MMCCTL_DATEG_RISING (1 << 6)

#define	MMCCTL_DATEG_FALLING (2 << 6)

#define	MMCCTL_DATEG_BOTH (3 << 6)

#define	MMCCTL_PERMDR_LE (0 << 9)

#define	MMCCTL_PERMDR_BE (1 << 9)

#define	MMCCTL_PERMDX_LE (0 << 10)

#define	MMCCTL_PERMDX_BE (1 << 10)

#define	MMCCLK_CLKEN (1 << 8)

#define	MMCCLK_CLKRT_MASK (0xFF << 0)

#define	MMCST0_DATDNE BIT(0) /* data done */

#define	MMCST0_BSYDNE BIT(1) /* busy done */

#define	MMCST0_RSPDNE BIT(2) /* command done */

#define	MMCST0_TOUTRD BIT(3) /* data read timeout */

#define	MMCST0_TOUTRS BIT(4) /* command response timeout */

#define	MMCST0_CRCWR BIT(5) /* data write CRC error */

#define	MMCST0_CRCRD BIT(6) /* data read CRC error */

#define	MMCST0_CRCRS BIT(7) /* command response CRC error */

#define	MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */

#define	MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/

#define	MMCST0_DATED BIT(11) /* DAT3 edge detect */

#define	MMCST0_TRNDNE BIT(12) /* transfer done */

#define	MMCST1_BUSY (1 << 0)

#define	MMCCMD_CMD_MASK (0x3F << 0)

#define	MMCCMD_PPLEN (1 << 7)

#define	MMCCMD_BSYEXP (1 << 8)

#define	MMCCMD_RSPFMT_MASK (3 << 9)

#define	MMCCMD_RSPFMT_NONE (0 << 9)

#define	MMCCMD_RSPFMT_R1456 (1 << 9)

#define	MMCCMD_RSPFMT_R2 (2 << 9)

#define	MMCCMD_RSPFMT_R3 (3 << 9)

#define	MMCCMD_DTRW (1 << 11)

#define	MMCCMD_STRMTP (1 << 12)

#define	MMCCMD_WDATX (1 << 13)

#define	MMCCMD_INITCK (1 << 14)

#define	MMCCMD_DCLR (1 << 15)

#define	MMCCMD_DMATRIG (1 << 16)

#define	MMCFIFOCTL_FIFORST (1 << 0)

#define	MMCFIFOCTL_FIFODIR_WR (1 << 1)

#define	MMCFIFOCTL_FIFODIR_RD (0 << 1)

#define	MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */

#define	MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */

#define	MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */

#define	MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */

#define	MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */

#define	SDIOST0_DAT1_HI BIT(0)

#define	SDIOIEN_IOINTEN BIT(0)

#define	SDIOIST_IOINT BIT(0)

#define	MMCSD_INIT_CLOCK 200000

#define	MAX_CCNT ((1 << 16) - 1)

#define	MAX_NR_SG 16

#define	DAVINCI_MMC_DATADIR_NONE 0

#define	DAVINCI_MMC_DATADIR_READ 1

#define	DAVINCI_MMC_DATADIR_WRITE 2

#define	davinci_mmcsd_pm_ops NULL

Functions
	module_param (rw_threshold, uint, S_IRUGO)

	MODULE_PARM_DESC (rw_threshold,"Read/Write threshold. Default = 32")

	module_param (poll_threshold, uint, S_IRUGO)

	MODULE_PARM_DESC (poll_threshold,"Polling transaction size threshold. Default = 128")

	module_param (poll_loopcount, uint, S_IRUGO)

	MODULE_PARM_DESC (poll_loopcount,"Maximum polling loop count. Default = 32")

	module_param (use_dma, uint, 0)

	MODULE_PARM_DESC (use_dma,"Whether to use DMA or not. Default = 1")

	module_init (davinci_mmcsd_init)

	module_exit (davinci_mmcsd_exit)

	MODULE_AUTHOR ("Texas Instruments India")

	MODULE_LICENSE ("GPL")

	MODULE_DESCRIPTION ("MMC/SD driver for Davinci MMC controller")

	MODULE_ALIAS ("platform:davinci_mmc")

Macro Definition Documentation

#define DAVINCI_MMC_DATADIR_NONE 0

Definition at line 189 of file davinci_mmc.c.

#define DAVINCI_MMC_DATADIR_READ 1

Definition at line 190 of file davinci_mmc.c.

#define DAVINCI_MMC_DATADIR_WRITE 2

Definition at line 191 of file davinci_mmc.c.

#define DAVINCI_MMCARGHL 0x34 /* Argument Register */

Definition at line 56 of file davinci_mmc.c.

#define DAVINCI_MMCBLEN 0x1C /* Block Length Register */

Definition at line 50 of file davinci_mmc.c.

#define DAVINCI_MMCBLNC 0x60

Definition at line 67 of file davinci_mmc.c.

#define DAVINCI_MMCCIDX 0x50 /* Command Index Register */

Definition at line 63 of file davinci_mmc.c.

#define DAVINCI_MMCCKC 0x54

Definition at line 64 of file davinci_mmc.c.

#define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */

Definition at line 44 of file davinci_mmc.c.

#define DAVINCI_MMCCMD 0x30 /* Command Register */

Definition at line 55 of file davinci_mmc.c.

#define DAVINCI_MMCCTL 0x00 /* Control Register */

Definition at line 43 of file davinci_mmc.c.

#define DAVINCI_MMCDRR 0x28 /* Data Receive Register */

Definition at line 53 of file davinci_mmc.c.

#define DAVINCI_MMCDRSP 0x48 /* Data Response Register */

Definition at line 61 of file davinci_mmc.c.

#define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */

Definition at line 54 of file davinci_mmc.c.

#define DAVINCI_MMCETOK 0x4C

Definition at line 62 of file davinci_mmc.c.

#define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */

Definition at line 72 of file davinci_mmc.c.

#define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */

Definition at line 47 of file davinci_mmc.c.

#define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */

Definition at line 52 of file davinci_mmc.c.

#define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */

Definition at line 51 of file davinci_mmc.c.

#define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */

Definition at line 57 of file davinci_mmc.c.

#define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */

Definition at line 58 of file davinci_mmc.c.

#define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */

Definition at line 59 of file davinci_mmc.c.

#define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */

Definition at line 60 of file davinci_mmc.c.

#define davinci_mmcsd_pm_ops NULL

Definition at line 1401 of file davinci_mmc.c.

#define DAVINCI_MMCST0 0x08 /* Status Register 0 */

Definition at line 45 of file davinci_mmc.c.

#define DAVINCI_MMCST1 0x0C /* Status Register 1 */

Definition at line 46 of file davinci_mmc.c.

#define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */

Definition at line 49 of file davinci_mmc.c.

#define DAVINCI_MMCTODC 0x5C

Definition at line 66 of file davinci_mmc.c.

#define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */

Definition at line 48 of file davinci_mmc.c.

#define DAVINCI_MMCTORC 0x58

Definition at line 65 of file davinci_mmc.c.

#define DAVINCI_SDIOCTL 0x64

Definition at line 68 of file davinci_mmc.c.

#define DAVINCI_SDIOIEN 0x6C

Definition at line 70 of file davinci_mmc.c.

#define DAVINCI_SDIOIST 0x70

Definition at line 71 of file davinci_mmc.c.

#define DAVINCI_SDIOST0 0x68

Definition at line 69 of file davinci_mmc.c.

#define MAX_CCNT ((1 << 16) - 1)

Definition at line 155 of file davinci_mmc.c.

#define MAX_NR_SG 16

Definition at line 157 of file davinci_mmc.c.

#define MMCCLK_CLKEN (1 << 8)

Definition at line 89 of file davinci_mmc.c.

#define MMCCLK_CLKRT_MASK (0xFF << 0)

Definition at line 90 of file davinci_mmc.c.

#define MMCCMD_BSYEXP (1 << 8)

Definition at line 112 of file davinci_mmc.c.

#define MMCCMD_CMD_MASK (0x3F << 0)

Definition at line 110 of file davinci_mmc.c.

#define MMCCMD_DCLR (1 << 15)

Definition at line 122 of file davinci_mmc.c.

#define MMCCMD_DMATRIG (1 << 16)

Definition at line 123 of file davinci_mmc.c.

#define MMCCMD_DTRW (1 << 11)

Definition at line 118 of file davinci_mmc.c.

#define MMCCMD_INITCK (1 << 14)

Definition at line 121 of file davinci_mmc.c.

#define MMCCMD_PPLEN (1 << 7)

Definition at line 111 of file davinci_mmc.c.

#define MMCCMD_RSPFMT_MASK (3 << 9)

Definition at line 113 of file davinci_mmc.c.

#define MMCCMD_RSPFMT_NONE (0 << 9)

Definition at line 114 of file davinci_mmc.c.

#define MMCCMD_RSPFMT_R1456 (1 << 9)

Definition at line 115 of file davinci_mmc.c.

#define MMCCMD_RSPFMT_R2 (2 << 9)

Definition at line 116 of file davinci_mmc.c.

#define MMCCMD_RSPFMT_R3 (3 << 9)

Definition at line 117 of file davinci_mmc.c.

#define MMCCMD_STRMTP (1 << 12)

Definition at line 119 of file davinci_mmc.c.

#define MMCCMD_WDATX (1 << 13)

Definition at line 120 of file davinci_mmc.c.

#define MMCCTL_CMDRST (1 << 1)

Definition at line 76 of file davinci_mmc.c.

#define MMCCTL_DATEG_BOTH (3 << 6)

Definition at line 82 of file davinci_mmc.c.

#define MMCCTL_DATEG_DISABLED (0 << 6)

Definition at line 79 of file davinci_mmc.c.

#define MMCCTL_DATEG_FALLING (2 << 6)

Definition at line 81 of file davinci_mmc.c.

#define MMCCTL_DATEG_RISING (1 << 6)

Definition at line 80 of file davinci_mmc.c.

#define MMCCTL_DATRST (1 << 0)

Definition at line 75 of file davinci_mmc.c.

#define MMCCTL_PERMDR_BE (1 << 9)

Definition at line 84 of file davinci_mmc.c.

#define MMCCTL_PERMDR_LE (0 << 9)

Definition at line 83 of file davinci_mmc.c.

#define MMCCTL_PERMDX_BE (1 << 10)

Definition at line 86 of file davinci_mmc.c.

#define MMCCTL_PERMDX_LE (0 << 10)

Definition at line 85 of file davinci_mmc.c.

#define MMCCTL_WIDTH_4_BIT (1 << 2)

Definition at line 78 of file davinci_mmc.c.

#define MMCCTL_WIDTH_8_BIT (1 << 8)

Definition at line 77 of file davinci_mmc.c.

#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */

Definition at line 133 of file davinci_mmc.c.

#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */

Definition at line 132 of file davinci_mmc.c.

#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */

Definition at line 131 of file davinci_mmc.c.

#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */

Definition at line 130 of file davinci_mmc.c.

#define MMCFIFOCTL_FIFODIR_RD (0 << 1)

Definition at line 128 of file davinci_mmc.c.

#define MMCFIFOCTL_FIFODIR_WR (1 << 1)

Definition at line 127 of file davinci_mmc.c.

#define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */

Definition at line 129 of file davinci_mmc.c.

#define MMCFIFOCTL_FIFORST (1 << 0)

Definition at line 126 of file davinci_mmc.c.

#define MMCSD_INIT_CLOCK 200000

Definition at line 145 of file davinci_mmc.c.

#define MMCST0_BSYDNE BIT(1) /* busy done */

Definition at line 94 of file davinci_mmc.c.

#define MMCST0_CRCRD BIT(6) /* data read CRC error */

Definition at line 99 of file davinci_mmc.c.

#define MMCST0_CRCRS BIT(7) /* command response CRC error */

Definition at line 100 of file davinci_mmc.c.

#define MMCST0_CRCWR BIT(5) /* data write CRC error */

Definition at line 98 of file davinci_mmc.c.

#define MMCST0_DATDNE BIT(0) /* data done */

Definition at line 93 of file davinci_mmc.c.

#define MMCST0_DATED BIT(11) /* DAT3 edge detect */

Definition at line 103 of file davinci_mmc.c.

#define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/

Definition at line 102 of file davinci_mmc.c.

#define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */

Definition at line 101 of file davinci_mmc.c.

#define MMCST0_RSPDNE BIT(2) /* command done */

Definition at line 95 of file davinci_mmc.c.

#define MMCST0_TOUTRD BIT(3) /* data read timeout */

Definition at line 96 of file davinci_mmc.c.

#define MMCST0_TOUTRS BIT(4) /* command response timeout */

Definition at line 97 of file davinci_mmc.c.

#define MMCST0_TRNDNE BIT(12) /* transfer done */

Definition at line 104 of file davinci_mmc.c.

#define MMCST1_BUSY (1 << 0)

Definition at line 107 of file davinci_mmc.c.

#define SDIOIEN_IOINTEN BIT(0)

Definition at line 139 of file davinci_mmc.c.

#define SDIOIST_IOINT BIT(0)

Definition at line 142 of file davinci_mmc.c.

#define SDIOST0_DAT1_HI BIT(0)

Definition at line 136 of file davinci_mmc.c.

Function Documentation

MODULE_ALIAS ( "platform:davinci_mmc" )

MODULE_AUTHOR ( "Texas Instruments India" )

MODULE_DESCRIPTION ( "MMC/SD driver for Davinci MMC controller" )

module_exit ( davinci_mmcsd_exit )

module_init ( davinci_mmcsd_init )

MODULE_LICENSE ( "GPL" )

module_param	(	rw_threshold	,
		uint	,
		S_IRUGO
	)

module_param	(	poll_threshold	,
		uint	,
		S_IRUGO
	)

module_param	(	poll_loopcount	,
		uint	,
		S_IRUGO
	)

module_param	(	use_dma	,
		uint	,
		0
	)

MODULE_PARM_DESC ( rw_threshold )

MODULE_PARM_DESC ( poll_threshold )

MODULE_PARM_DESC ( poll_loopcount )

MODULE_PARM_DESC ( use_dma )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation