#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/if_arp.h>
#include <linux/in.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/netdevice.h>
#include <linux/slab.h>
#include <linux/rtnetlink.h>
#include <linux/sockios.h>
#include <linux/workqueue.h>
#include <linux/atomic.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <net/ax25.h>
#include "z8530.h"

Data Structures
struct	scc_param

struct	scc_hardware

struct	scc_priv

struct	scc_info

Macros
#define	NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (min. 2 recommended) */

#define	NUM_RX_BUF 6 /* NUM_RX_BUF >= 1 (min. 2 recommended) */

#define	BUF_SIZE 1576 /* BUF_SIZE >= mtu + hard_header_len */

#define	HW_PI

#define	HW_PI2

#define	HW_TWIN

#define	HW_S5

#define	HARDWARE { HW_PI, HW_PI2, HW_TWIN, HW_S5 }

#define	TMR_0_HZ 25600 /* Frequency of timer 0 */

#define	TYPE_PI 0

#define	TYPE_PI2 1

#define	TYPE_TWIN 2

#define	TYPE_S5 3

#define	NUM_TYPES 4

#define	MAX_NUM_DEVS 32

#define	Z8530 0

#define	Z85C30 1

#define	Z85230 2

#define	CHIPNAMES { "Z8530", "Z85C30", "Z85230" }

#define	SCCB_CMD 0x00

#define	SCCB_DATA 0x01

#define	SCCA_CMD 0x02

#define	SCCA_DATA 0x03

#define	TMR_CNT0 0x00

#define	TMR_CNT1 0x01

#define	TMR_CNT2 0x02

#define	TMR_CTRL 0x03

#define	PI_DREQ_MASK 0x04

#define	TWIN_INT_REG 0x08

#define	TWIN_CLR_TMR1 0x09

#define	TWIN_CLR_TMR2 0x0a

#define	TWIN_SPARE_1 0x0b

#define	TWIN_DMA_CFG 0x08

#define	TWIN_SERIAL_CFG 0x09

#define	TWIN_DMA_CLR_FF 0x0a

#define	TWIN_SPARE_2 0x0b

#define	TWIN_SCC_MSK 0x01

#define	TWIN_TMR1_MSK 0x02

#define	TWIN_TMR2_MSK 0x04

#define	TWIN_INT_MSK 0x07

#define	TWIN_DTRA_ON 0x01

#define	TWIN_DTRB_ON 0x02

#define	TWIN_EXTCLKA 0x04

#define	TWIN_EXTCLKB 0x08

#define	TWIN_LOOPA_ON 0x10

#define	TWIN_LOOPB_ON 0x20

#define	TWIN_EI 0x80

#define	TWIN_DMA_HDX_T1 0x08

#define	TWIN_DMA_HDX_R1 0x0a

#define	TWIN_DMA_HDX_T3 0x14

#define	TWIN_DMA_HDX_R3 0x16

#define	TWIN_DMA_FDX_T3R1 0x1b

#define	TWIN_DMA_FDX_T1R3 0x1d

#define	IDLE 0

#define	TX_HEAD 1

#define	TX_DATA 2

#define	TX_PAUSE 3

#define	TX_TAIL 4

#define	RTS_OFF 5

#define	WAIT 6

#define	DCD_ON 7

#define	RX_ON 8

#define	DCD_OFF 9

#define	SIOCGSCCPARAM SIOCDEVPRIVATE

#define	SIOCSSCCPARAM (SIOCDEVPRIVATE+1)

Functions
	MODULE_AUTHOR ("Klaus Kudielka")

	MODULE_DESCRIPTION ("Driver for high-speed SCC boards")

	module_param_array (io, int, NULL, 0)

	MODULE_LICENSE ("GPL")

	module_init (dmascc_init)

	module_exit (dmascc_exit)

Macro Definition Documentation

#define BUF_SIZE 1576 /* BUF_SIZE >= mtu + hard_header_len */

Definition at line 52 of file dmascc.c.

#define CHIPNAMES { "Z8530", "Z85C30", "Z85230" }

Definition at line 85 of file dmascc.c.

#define DCD_OFF 9

Definition at line 153 of file dmascc.c.

#define DCD_ON 7

Definition at line 151 of file dmascc.c.

#define HARDWARE { HW_PI, HW_PI2, HW_TWIN, HW_S5 }

Definition at line 66 of file dmascc.c.

#define HW_PI

Value:

{ "Ottawa PI", 0x300, 0x20, 0x10, 8, \

0, 8, 1843200, 3686400 }

Definition at line 57 of file dmascc.c.

#define HW_PI2

Value:

{ "Ottawa PI2", 0x300, 0x20, 0x10, 8, \

0, 8, 3686400, 7372800 }

Definition at line 59 of file dmascc.c.

#define HW_S5

Value:

{ "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \

0, 8, 4915200, 9830400 }

Definition at line 63 of file dmascc.c.

#define HW_TWIN

Value:

{ "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \

0, 4, 6144000, 6144000 }

Definition at line 61 of file dmascc.c.

#define IDLE 0

Definition at line 144 of file dmascc.c.

#define MAX_NUM_DEVS 32

Definition at line 76 of file dmascc.c.

#define NUM_RX_BUF 6 /* NUM_RX_BUF >= 1 (min. 2 recommended) */

Definition at line 51 of file dmascc.c.

#define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (min. 2 recommended) */

Definition at line 50 of file dmascc.c.

#define NUM_TYPES 4

Definition at line 74 of file dmascc.c.

#define PI_DREQ_MASK 0x04

Definition at line 103 of file dmascc.c.

#define RTS_OFF 5

Definition at line 149 of file dmascc.c.

#define RX_ON 8

Definition at line 152 of file dmascc.c.

#define SCCA_CMD 0x02

Definition at line 93 of file dmascc.c.

#define SCCA_DATA 0x03

Definition at line 94 of file dmascc.c.

#define SCCB_CMD 0x00

Definition at line 91 of file dmascc.c.

#define SCCB_DATA 0x01

Definition at line 92 of file dmascc.c.

#define SIOCGSCCPARAM SIOCDEVPRIVATE

Definition at line 158 of file dmascc.c.

#define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)

Definition at line 159 of file dmascc.c.

#define TMR_0_HZ 25600 /* Frequency of timer 0 */

Definition at line 68 of file dmascc.c.

#define TMR_CNT0 0x00

Definition at line 97 of file dmascc.c.

#define TMR_CNT1 0x01

Definition at line 98 of file dmascc.c.

#define TMR_CNT2 0x02

Definition at line 99 of file dmascc.c.

#define TMR_CTRL 0x03

Definition at line 100 of file dmascc.c.

#define TWIN_CLR_TMR1 0x09

Definition at line 107 of file dmascc.c.

#define TWIN_CLR_TMR2 0x0a

Definition at line 108 of file dmascc.c.

#define TWIN_DMA_CFG 0x08

Definition at line 110 of file dmascc.c.

#define TWIN_DMA_CLR_FF 0x0a

Definition at line 112 of file dmascc.c.

#define TWIN_DMA_FDX_T1R3 0x1d

Definition at line 139 of file dmascc.c.

#define TWIN_DMA_FDX_T3R1 0x1b

Definition at line 138 of file dmascc.c.

#define TWIN_DMA_HDX_R1 0x0a

Definition at line 135 of file dmascc.c.

#define TWIN_DMA_HDX_R3 0x16

Definition at line 137 of file dmascc.c.

#define TWIN_DMA_HDX_T1 0x08

Definition at line 134 of file dmascc.c.

#define TWIN_DMA_HDX_T3 0x14

Definition at line 136 of file dmascc.c.

#define TWIN_DTRA_ON 0x01

Definition at line 125 of file dmascc.c.

#define TWIN_DTRB_ON 0x02

Definition at line 126 of file dmascc.c.

#define TWIN_EI 0x80

Definition at line 131 of file dmascc.c.

#define TWIN_EXTCLKA 0x04

Definition at line 127 of file dmascc.c.

#define TWIN_EXTCLKB 0x08

Definition at line 128 of file dmascc.c.

#define TWIN_INT_MSK 0x07

Definition at line 122 of file dmascc.c.

#define TWIN_INT_REG 0x08

Definition at line 106 of file dmascc.c.

#define TWIN_LOOPA_ON 0x10

Definition at line 129 of file dmascc.c.

#define TWIN_LOOPB_ON 0x20

Definition at line 130 of file dmascc.c.

#define TWIN_SCC_MSK 0x01

Definition at line 119 of file dmascc.c.

#define TWIN_SERIAL_CFG 0x09

Definition at line 111 of file dmascc.c.

#define TWIN_SPARE_1 0x0b

Definition at line 109 of file dmascc.c.

#define TWIN_SPARE_2 0x0b

Definition at line 113 of file dmascc.c.

#define TWIN_TMR1_MSK 0x02

Definition at line 120 of file dmascc.c.

#define TWIN_TMR2_MSK 0x04

Definition at line 121 of file dmascc.c.

#define TX_DATA 2

Definition at line 146 of file dmascc.c.

#define TX_HEAD 1

Definition at line 145 of file dmascc.c.

#define TX_PAUSE 3

Definition at line 147 of file dmascc.c.

#define TX_TAIL 4

Definition at line 148 of file dmascc.c.

#define TYPE_PI 0

Definition at line 70 of file dmascc.c.

#define TYPE_PI2 1

Definition at line 71 of file dmascc.c.

#define TYPE_S5 3

Definition at line 73 of file dmascc.c.

#define TYPE_TWIN 2

Definition at line 72 of file dmascc.c.

#define WAIT 6

Definition at line 150 of file dmascc.c.

#define Z85230 2

Definition at line 83 of file dmascc.c.

#define Z8530 0

Definition at line 81 of file dmascc.c.

#define Z85C30 1

Definition at line 82 of file dmascc.c.

Function Documentation

MODULE_AUTHOR ( "Klaus Kudielka" )

MODULE_DESCRIPTION ( "Driver for high-speed SCC boards" )

module_exit ( dmascc_exit )

module_init ( dmascc_init )

MODULE_LICENSE ( "GPL" )

module_param_array	(	io	,
		int	,
		NULL	,
		0
	)

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation