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phy.h
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1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012 Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <[email protected]>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <[email protected]>
27  *
28  *****************************************************************************/
29 
30 #ifndef __RTL92D_PHY_H__
31 #define __RTL92D_PHY_H__
32 
33 #define MAX_PRECMD_CNT 16
34 #define MAX_RFDEPENDCMD_CNT 16
35 #define MAX_POSTCMD_CNT 16
36 
37 #define MAX_DOZE_WAITING_TIMES_9x 64
38 
39 #define RT_CANNOT_IO(hw) false
40 #define HIGHPOWER_RADIOA_ARRAYLEN 22
41 
42 #define IQK_ADDA_REG_NUM 16
43 #define MAX_TOLERANCE 5
44 #define IQK_DELAY_TIME 1
45 
46 #define APK_BB_REG_NUM 5
47 #define APK_AFE_REG_NUM 16
48 #define APK_CURVE_REG_NUM 4
49 #define PATH_NUM 2
50 
51 #define LOOP_LIMIT 5
52 #define MAX_STALL_TIME 50
53 #define ANTENNA_DIVERSITY_VALUE 0x80
54 #define MAX_TXPWR_IDX_NMODE_92S 63
55 #define RESET_CNT_LIMIT 3
56 
57 #define IQK_ADDA_REG_NUM 16
58 #define IQK_BB_REG_NUM 10
59 #define IQK_BB_REG_NUM_test 6
60 #define IQK_MAC_REG_NUM 4
61 #define RX_INDEX_MAPPING_NUM 15
62 
63 #define IQK_DELAY_TIME 1
64 
65 #define CT_OFFSET_MAC_ADDR 0X16
66 
67 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
68 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
69 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
70 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
71 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
72 
73 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
74 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
75 
76 #define CT_OFFSET_CHANNEL_PLAH 0x75
77 #define CT_OFFSET_THERMAL_METER 0x78
78 #define CT_OFFSET_RF_OPTION 0x79
79 #define CT_OFFSET_VERSION 0x7E
80 #define CT_OFFSET_CUSTOMER_ID 0x7F
81 
82 enum swchnlcmd_id {
83  CMDID_END,
84  CMDID_SET_TXPOWEROWER_LEVEL,
85  CMDID_BBREGWRITE10,
86  CMDID_WRITEPORT_ULONG,
87  CMDID_WRITEPORT_USHORT,
88  CMDID_WRITEPORT_UCHAR,
89  CMDID_RF_WRITEREG,
90 };
91 
92 struct swchnlcmd {
93  enum swchnlcmd_id cmdid;
94  u32 para1;
95  u32 para2;
96  u32 msdelay;
97 };
98 
99 enum baseband_config_type {
100  BASEBAND_CONFIG_PHY_REG = 0,
101  BASEBAND_CONFIG_AGC_TAB = 1,
102 };
103 
104 enum rf_content {
105  radioa_txt = 0,
106  radiob_txt = 1,
107  radioc_txt = 2,
108  radiod_txt = 3
109 };
110 
111 static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
112  unsigned long *flag)
113 {
114  struct rtl_priv *rtlpriv = rtl_priv(hw);
115 
116  if (rtlpriv->rtlhal.interfaceindex == 1)
117  spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
118 }
119 
120 static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
121  unsigned long *flag)
122 {
123  struct rtl_priv *rtlpriv = rtl_priv(hw);
124 
125  if (rtlpriv->rtlhal.interfaceindex == 1)
126  spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
127  *flag);
128 }
129 
130 extern u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
131  u32 regaddr, u32 bitmask);
132 extern void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
133  u32 regaddr, u32 bitmask, u32 data);
134 extern u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
135  enum radio_path rfpath, u32 regaddr,
136  u32 bitmask);
137 extern void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
138  enum radio_path rfpath, u32 regaddr,
139  u32 bitmask, u32 data);
140 extern bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
141 extern bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
142 extern bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
143 extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
144  enum radio_path rfpath);
145 extern void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
146 extern void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
147 extern void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw,
148  u8 operation);
149 extern void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
150  enum nl80211_channel_type ch_type);
151 extern u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
152 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
153  enum rf_content content,
154  enum radio_path rfpath);
155 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
156 extern bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
157  enum rf_pwrstate rfpwr_state);
158 
159 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
160 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
161 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
162 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
163 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
164 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
165 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
166 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
167 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
168 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
169 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
170 void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
171  unsigned long *flag);
172 void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
173  unsigned long *flag);
174 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
175 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
176 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
177 
178 #endif
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