Go to the source code of this file.
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enum | swchnlcmd_id {
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG,
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG,
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG,
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG
} |
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enum | hw90_block_e {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4,
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4
} |
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enum | baseband_config_type {
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1,
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1,
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1,
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1
} |
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enum | ra_offset_area {
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK
} |
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enum | antenna_path {
ANTENNA_NONE,
ANTENNA_D,
ANTENNA_C,
ANTENNA_CD,
ANTENNA_B,
ANTENNA_BD,
ANTENNA_BC,
ANTENNA_BCD,
ANTENNA_A,
ANTENNA_AD,
ANTENNA_AC,
ANTENNA_ACD,
ANTENNA_AB,
ANTENNA_ABD,
ANTENNA_ABC,
ANTENNA_ABCD,
ANTENNA_NONE,
ANTENNA_D,
ANTENNA_C,
ANTENNA_CD,
ANTENNA_B,
ANTENNA_BD,
ANTENNA_BC,
ANTENNA_BCD,
ANTENNA_A,
ANTENNA_AD,
ANTENNA_AC,
ANTENNA_ACD,
ANTENNA_AB,
ANTENNA_ABD,
ANTENNA_ABC,
ANTENNA_ABCD
} |
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u32 | rtl92c_phy_query_bb_reg (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) |
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void | rtl92c_phy_set_bb_reg (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, u32 data) |
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u32 | rtl92c_phy_query_rf_reg (struct ieee80211_hw *hw, enum radio_path rfpath, u32 regaddr, u32 bitmask) |
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bool | rtl92c_phy_mac_config (struct ieee80211_hw *hw) |
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bool | rtl92c_phy_bb_config (struct ieee80211_hw *hw) |
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bool | rtl92c_phy_rf_config (struct ieee80211_hw *hw) |
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bool | rtl92c_phy_config_rf_with_feaderfile (struct ieee80211_hw *hw, enum radio_path rfpath) |
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void | rtl92c_phy_get_hw_reg_originalvalue (struct ieee80211_hw *hw) |
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void | rtl92c_phy_get_txpower_level (struct ieee80211_hw *hw, long *powerlevel) |
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void | rtl92c_phy_set_txpower_level (struct ieee80211_hw *hw, u8 channel) |
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bool | rtl92c_phy_update_txpower_dbm (struct ieee80211_hw *hw, long power_indbm) |
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void | rtl92c_phy_scan_operation_backup (struct ieee80211_hw *hw, u8 operation) |
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void | rtl92c_phy_set_bw_mode (struct ieee80211_hw *hw, enum nl80211_channel_type ch_type) |
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void | rtl92c_phy_sw_chnl_callback (struct ieee80211_hw *hw) |
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u8 | rtl92c_phy_sw_chnl (struct ieee80211_hw *hw) |
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void | rtl92c_phy_iq_calibrate (struct ieee80211_hw *hw, bool b_recovery) |
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void | rtl92c_phy_set_beacon_hw_reg (struct ieee80211_hw *hw, u16 beaconinterval) |
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void | rtl92c_phy_ap_calibrate (struct ieee80211_hw *hw, char delta) |
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void | rtl92c_phy_lc_calibrate (struct ieee80211_hw *hw) |
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void | rtl92c_phy_set_rfpath_switch (struct ieee80211_hw *hw, bool bmain) |
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bool | rtl92c_phy_config_rf_with_headerfile (struct ieee80211_hw *hw, enum radio_path rfpath) |
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bool | rtl8192_phy_check_is_legal_rfpath (struct ieee80211_hw *hw, u32 rfpath) |
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bool | rtl92c_phy_set_rf_power_state (struct ieee80211_hw *hw, enum rf_pwrstate rfpwr_state) |
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void | rtl92ce_phy_set_rf_on (struct ieee80211_hw *hw) |
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void | rtl92c_phy_set_io (struct ieee80211_hw *hw) |
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void | rtl92c_bb_block_on (struct ieee80211_hw *hw) |
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u32 | _rtl92c_phy_calculate_bit_shift (u32 bitmask) |
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long | _rtl92c_phy_txpwr_idx_to_dbm (struct ieee80211_hw *hw, enum wireless_mode wirelessmode, u8 txpwridx) |
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u8 | _rtl92c_phy_dbm_to_txpwr_Idx (struct ieee80211_hw *hw, enum wireless_mode wirelessmode, long power_indbm) |
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void | _rtl92c_phy_init_bb_rf_register_definition (struct ieee80211_hw *hw) |
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void | _rtl92c_phy_set_rf_sleep (struct ieee80211_hw *hw) |
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bool | _rtl92c_phy_sw_chnl_step_by_step (struct ieee80211_hw *hw, u8 channel, u8 *stage, u8 *step, u32 *delay) |
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u8 | rtl92c_bt_rssi_state_change (struct ieee80211_hw *hw) |
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u32 | _rtl92c_phy_fw_rf_serial_read (struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset) |
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void | _rtl92c_phy_fw_rf_serial_write (struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data) |
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u32 | _rtl92c_phy_rf_serial_read (struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset) |
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void | _rtl92c_phy_rf_serial_write (struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data) |
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bool | _rtl92c_phy_bb8192c_config_parafile (struct ieee80211_hw *hw) |
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void | _rtl92c_store_pwrIndex_diffrate_offset (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, u32 data) |
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bool | rtl92c_phy_set_io_cmd (struct ieee80211_hw *hw, enum io_type iotype) |
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#define AntennaDiversityValue 0x80 |
#define APK_AFE_REG_NUM 16 |
#define APK_CURVE_REG_NUM 4 |
#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A |
#define CT_OFFSET_CHANNEL_PLAH 0x75 |
#define CT_OFFSET_CUSTOMER_ID 0x7F |
#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72 |
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69 |
#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60 |
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66 |
#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F |
#define CT_OFFSET_MAC_ADDR 0X16 |
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C |
#define CT_OFFSET_RF_OPTION 0x79 |
#define CT_OFFSET_THERMAL_METER 0x78 |
#define CT_OFFSET_VERSION 0x7E |
#define HIGHPOWER_RADIOA_ARRAYLEN 22 |
#define IQK_ADDA_REG_NUM 16 |
#define IQK_ADDA_REG_NUM 16 |
#define IQK_MAC_REG_NUM 4 |
#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255 |
#define MAX_DOZE_WAITING_TIMES_9x 64 |
#define MAX_POSTCMD_CNT 16 |
#define MAX_PRECMD_CNT 16 |
#define MAX_RFDEPENDCMD_CNT 16 |
#define MAX_STALL_TIME 50 |
#define MAX_TXPWR_IDX_NMODE_92S 63 |
#define Reset_Cnt_Limit 3 |
#define RTL92C_MAX_PATH_NUM 2 |
- Enumerator:
ANTENNA_NONE |
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ANTENNA_D |
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ANTENNA_C |
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ANTENNA_CD |
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ANTENNA_B |
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ANTENNA_BD |
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ANTENNA_BC |
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ANTENNA_BCD |
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ANTENNA_A |
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ANTENNA_AD |
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ANTENNA_AC |
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ANTENNA_ACD |
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ANTENNA_AB |
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ANTENNA_ABD |
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ANTENNA_ABC |
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ANTENNA_ABCD |
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ANTENNA_NONE |
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ANTENNA_D |
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ANTENNA_C |
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ANTENNA_CD |
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ANTENNA_B |
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ANTENNA_BD |
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ANTENNA_BC |
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ANTENNA_BCD |
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ANTENNA_A |
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ANTENNA_AD |
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ANTENNA_AC |
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ANTENNA_ACD |
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ANTENNA_AB |
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ANTENNA_ABD |
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ANTENNA_ABC |
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ANTENNA_ABCD |
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Definition at line 123 of file phy_common.h.
- Enumerator:
BASEBAND_CONFIG_PHY_REG |
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BASEBAND_CONFIG_AGC_TAB |
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BASEBAND_CONFIG_PHY_REG |
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BASEBAND_CONFIG_AGC_TAB |
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BASEBAND_CONFIG_PHY_REG |
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BASEBAND_CONFIG_AGC_TAB |
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BASEBAND_CONFIG_PHY_REG |
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BASEBAND_CONFIG_AGC_TAB |
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Definition at line 108 of file phy_common.h.
- Enumerator:
HW90_BLOCK_MAC |
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HW90_BLOCK_PHY0 |
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HW90_BLOCK_PHY1 |
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HW90_BLOCK_RF |
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HW90_BLOCK_MAXIMUM |
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HW90_BLOCK_MAC |
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HW90_BLOCK_PHY0 |
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HW90_BLOCK_PHY1 |
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HW90_BLOCK_RF |
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HW90_BLOCK_MAXIMUM |
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Definition at line 100 of file phy_common.h.
- Enumerator:
RA_OFFSET_LEGACY_OFDM1 |
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RA_OFFSET_LEGACY_OFDM2 |
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RA_OFFSET_HT_OFDM1 |
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RA_OFFSET_HT_OFDM2 |
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RA_OFFSET_HT_OFDM3 |
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RA_OFFSET_HT_OFDM4 |
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RA_OFFSET_HT_CCK |
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RA_OFFSET_LEGACY_OFDM1 |
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RA_OFFSET_LEGACY_OFDM2 |
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RA_OFFSET_HT_OFDM1 |
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RA_OFFSET_HT_OFDM2 |
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RA_OFFSET_HT_OFDM3 |
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RA_OFFSET_HT_OFDM4 |
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RA_OFFSET_HT_CCK |
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Definition at line 113 of file phy_common.h.
- Enumerator:
CMDID_END |
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CMDID_SET_TXPOWEROWER_LEVEL |
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CMDID_BBREGWRITE10 |
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CMDID_WRITEPORT_ULONG |
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CMDID_WRITEPORT_USHORT |
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CMDID_WRITEPORT_UCHAR |
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CMDID_RF_WRITEREG |
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CMDID_END |
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CMDID_SET_TXPOWEROWER_LEVEL |
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CMDID_BBREGWRITE10 |
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CMDID_WRITEPORT_ULONG |
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CMDID_WRITEPORT_USHORT |
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CMDID_WRITEPORT_UCHAR |
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CMDID_RF_WRITEREG |
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CMDID_END |
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CMDID_SET_TXPOWEROWER_LEVEL |
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CMDID_BBREGWRITE10 |
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CMDID_WRITEPORT_ULONG |
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CMDID_WRITEPORT_USHORT |
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CMDID_WRITEPORT_UCHAR |
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CMDID_RF_WRITEREG |
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CMDID_END |
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CMDID_SET_TXPOWEROWER_LEVEL |
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CMDID_BBREGWRITE10 |
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CMDID_WRITEPORT_ULONG |
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CMDID_WRITEPORT_USHORT |
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CMDID_WRITEPORT_UCHAR |
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CMDID_RF_WRITEREG |
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Definition at line 83 of file phy_common.h.
u32 _rtl92c_phy_calculate_bit_shift |
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u32 |
bitmask | ) |
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Definition at line 88 of file phy.c.
Definition at line 76 of file phy.c.
Definition at line 43 of file phy.c.