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#define | DSS_SUBSYS_NAME "DSI" |
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#define | DSI_CATCH_MISSING_TE |
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#define | DSI_REG(idx) ((const struct dsi_reg) { idx }) |
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#define | DSI_SZ_REGS SZ_1K |
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#define | DSI_REVISION DSI_REG(0x0000) |
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#define | DSI_SYSCONFIG DSI_REG(0x0010) |
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#define | DSI_SYSSTATUS DSI_REG(0x0014) |
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#define | DSI_IRQSTATUS DSI_REG(0x0018) |
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#define | DSI_IRQENABLE DSI_REG(0x001C) |
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#define | DSI_CTRL DSI_REG(0x0040) |
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#define | DSI_GNQ DSI_REG(0x0044) |
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#define | DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
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#define | DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) |
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#define | DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) |
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#define | DSI_CLK_CTRL DSI_REG(0x0054) |
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#define | DSI_TIMING1 DSI_REG(0x0058) |
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#define | DSI_TIMING2 DSI_REG(0x005C) |
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#define | DSI_VM_TIMING1 DSI_REG(0x0060) |
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#define | DSI_VM_TIMING2 DSI_REG(0x0064) |
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#define | DSI_VM_TIMING3 DSI_REG(0x0068) |
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#define | DSI_CLK_TIMING DSI_REG(0x006C) |
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#define | DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) |
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#define | DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) |
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#define | DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) |
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#define | DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) |
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#define | DSI_VM_TIMING4 DSI_REG(0x0080) |
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#define | DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) |
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#define | DSI_VM_TIMING5 DSI_REG(0x0088) |
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#define | DSI_VM_TIMING6 DSI_REG(0x008C) |
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#define | DSI_VM_TIMING7 DSI_REG(0x0090) |
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#define | DSI_STOPCLK_TIMING DSI_REG(0x0094) |
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#define | DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) |
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#define | DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) |
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#define | DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) |
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#define | DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) |
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#define | DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) |
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#define | DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) |
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#define | DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) |
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#define | DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) |
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#define | DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) |
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#define | DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) |
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#define | DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) |
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#define | DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
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#define | DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) |
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#define | DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) |
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#define | DSI_PLL_GO DSI_REG(0x300 + 0x0008) |
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#define | DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) |
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#define | DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) |
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#define | REG_GET(dsidev, idx, start, end) FLD_GET(dsi_read_reg(dsidev, idx), start, end) |
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#define | REG_FLD_MOD(dsidev, idx, val, start, end) dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) |
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#define | DSI_IRQ_VC0 (1 << 0) |
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#define | DSI_IRQ_VC1 (1 << 1) |
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#define | DSI_IRQ_VC2 (1 << 2) |
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#define | DSI_IRQ_VC3 (1 << 3) |
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#define | DSI_IRQ_WAKEUP (1 << 4) |
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#define | DSI_IRQ_RESYNC (1 << 5) |
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#define | DSI_IRQ_PLL_LOCK (1 << 7) |
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#define | DSI_IRQ_PLL_UNLOCK (1 << 8) |
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#define | DSI_IRQ_PLL_RECALL (1 << 9) |
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#define | DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
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#define | DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
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#define | DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
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#define | DSI_IRQ_TE_TRIGGER (1 << 16) |
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#define | DSI_IRQ_ACK_TRIGGER (1 << 17) |
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#define | DSI_IRQ_SYNC_LOST (1 << 18) |
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#define | DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
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#define | DSI_IRQ_TA_TIMEOUT (1 << 20) |
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#define | DSI_IRQ_ERROR_MASK |
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#define | DSI_IRQ_CHANNEL_MASK 0xf |
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#define | DSI_VC_IRQ_CS (1 << 0) |
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#define | DSI_VC_IRQ_ECC_CORR (1 << 1) |
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#define | DSI_VC_IRQ_PACKET_SENT (1 << 2) |
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#define | DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
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#define | DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
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#define | DSI_VC_IRQ_BTA (1 << 5) |
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#define | DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
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#define | DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
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#define | DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
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#define | DSI_VC_IRQ_ERROR_MASK |
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#define | DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
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#define | DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
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#define | DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
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#define | DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
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#define | DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) |
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#define | DSI_CIO_IRQ_ERRESC1 (1 << 5) |
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#define | DSI_CIO_IRQ_ERRESC2 (1 << 6) |
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#define | DSI_CIO_IRQ_ERRESC3 (1 << 7) |
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#define | DSI_CIO_IRQ_ERRESC4 (1 << 8) |
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#define | DSI_CIO_IRQ_ERRESC5 (1 << 9) |
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#define | DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
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#define | DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
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#define | DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
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#define | DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
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#define | DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) |
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#define | DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
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#define | DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
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#define | DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
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#define | DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
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#define | DSI_CIO_IRQ_STATEULPS5 (1 << 19) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) |
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#define | DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) |
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#define | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
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#define | DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
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#define | DSI_CIO_IRQ_ERROR_MASK |
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#define | DSI_MAX_NR_ISRS 2 |
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#define | DSI_MAX_NR_LANES 5 |
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#define | PIS(x) |
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#define | PIS(x) |
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#define | PIS(x) |
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#define | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
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#define | _dsi_print_reset_status(x) |
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#define | DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
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struct platform_device * | dsi_get_dsidev_from_id (int module) |
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void | dsi_bus_lock (struct omap_dss_device *dssdev) |
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| EXPORT_SYMBOL (dsi_bus_lock) |
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void | dsi_bus_unlock (struct omap_dss_device *dssdev) |
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| EXPORT_SYMBOL (dsi_bus_unlock) |
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u8 | dsi_get_pixel_size (enum omap_dss_dsi_pixel_format fmt) |
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int | dsi_runtime_get (struct platform_device *dsidev) |
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void | dsi_runtime_put (struct platform_device *dsidev) |
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unsigned long | dsi_get_pll_hsdiv_dispc_rate (struct platform_device *dsidev) |
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int | dsi_pll_calc_clock_div_pck (struct platform_device *dsidev, unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, struct dispc_clock_info *dispc_cinfo) |
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int | dsi_pll_set_clock_div (struct platform_device *dsidev, struct dsi_clock_info *cinfo) |
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int | dsi_pll_init (struct platform_device *dsidev, bool enable_hsclk, bool enable_hsdiv) |
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void | dsi_pll_uninit (struct platform_device *dsidev, bool disconnect_lanes) |
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void | dsi_dump_clocks (struct seq_file *s) |
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void | omapdss_dsi_vc_enable_hs (struct omap_dss_device *dssdev, int channel, bool enable) |
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| EXPORT_SYMBOL (omapdss_dsi_vc_enable_hs) |
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int | dsi_vc_send_bta_sync (struct omap_dss_device *dssdev, int channel) |
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| EXPORT_SYMBOL (dsi_vc_send_bta_sync) |
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int | dsi_vc_send_null (struct omap_dss_device *dssdev, int channel) |
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| EXPORT_SYMBOL (dsi_vc_send_null) |
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int | dsi_vc_dcs_write_nosync (struct omap_dss_device *dssdev, int channel, u8 *data, int len) |
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| EXPORT_SYMBOL (dsi_vc_dcs_write_nosync) |
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int | dsi_vc_generic_write_nosync (struct omap_dss_device *dssdev, int channel, u8 *data, int len) |
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| EXPORT_SYMBOL (dsi_vc_generic_write_nosync) |
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int | dsi_vc_dcs_write (struct omap_dss_device *dssdev, int channel, u8 *data, int len) |
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| EXPORT_SYMBOL (dsi_vc_dcs_write) |
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int | dsi_vc_generic_write (struct omap_dss_device *dssdev, int channel, u8 *data, int len) |
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| EXPORT_SYMBOL (dsi_vc_generic_write) |
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int | dsi_vc_dcs_write_0 (struct omap_dss_device *dssdev, int channel, u8 dcs_cmd) |
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| EXPORT_SYMBOL (dsi_vc_dcs_write_0) |
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int | dsi_vc_generic_write_0 (struct omap_dss_device *dssdev, int channel) |
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| EXPORT_SYMBOL (dsi_vc_generic_write_0) |
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int | dsi_vc_dcs_write_1 (struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, u8 param) |
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| EXPORT_SYMBOL (dsi_vc_dcs_write_1) |
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int | dsi_vc_generic_write_1 (struct omap_dss_device *dssdev, int channel, u8 param) |
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| EXPORT_SYMBOL (dsi_vc_generic_write_1) |
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int | dsi_vc_generic_write_2 (struct omap_dss_device *dssdev, int channel, u8 param1, u8 param2) |
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| EXPORT_SYMBOL (dsi_vc_generic_write_2) |
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int | dsi_vc_dcs_read (struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, u8 *buf, int buflen) |
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| EXPORT_SYMBOL (dsi_vc_dcs_read) |
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int | dsi_vc_generic_read_0 (struct omap_dss_device *dssdev, int channel, u8 *buf, int buflen) |
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| EXPORT_SYMBOL (dsi_vc_generic_read_0) |
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int | dsi_vc_generic_read_1 (struct omap_dss_device *dssdev, int channel, u8 param, u8 *buf, int buflen) |
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| EXPORT_SYMBOL (dsi_vc_generic_read_1) |
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int | dsi_vc_generic_read_2 (struct omap_dss_device *dssdev, int channel, u8 param1, u8 param2, u8 *buf, int buflen) |
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| EXPORT_SYMBOL (dsi_vc_generic_read_2) |
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int | dsi_vc_set_max_rx_packet_size (struct omap_dss_device *dssdev, int channel, u16 len) |
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| EXPORT_SYMBOL (dsi_vc_set_max_rx_packet_size) |
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int | omapdss_dsi_configure_pins (struct omap_dss_device *dssdev, const struct omap_dsi_pin_config *pin_cfg) |
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| EXPORT_SYMBOL (omapdss_dsi_configure_pins) |
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int | omapdss_dsi_set_clocks (struct omap_dss_device *dssdev, unsigned long ddr_clk, unsigned long lp_clk) |
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| EXPORT_SYMBOL (omapdss_dsi_set_clocks) |
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int | dsi_enable_video_output (struct omap_dss_device *dssdev, int channel) |
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| EXPORT_SYMBOL (dsi_enable_video_output) |
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void | dsi_disable_video_output (struct omap_dss_device *dssdev, int channel) |
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| EXPORT_SYMBOL (dsi_disable_video_output) |
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int | omap_dsi_update (struct omap_dss_device *dssdev, int channel, void(*callback)(int, void *), void *data) |
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| EXPORT_SYMBOL (omap_dsi_update) |
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int | omapdss_dsi_display_enable (struct omap_dss_device *dssdev) |
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| EXPORT_SYMBOL (omapdss_dsi_display_enable) |
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void | omapdss_dsi_display_disable (struct omap_dss_device *dssdev, bool disconnect_lanes, bool enter_ulps) |
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| EXPORT_SYMBOL (omapdss_dsi_display_disable) |
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int | omapdss_dsi_enable_te (struct omap_dss_device *dssdev, bool enable) |
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| EXPORT_SYMBOL (omapdss_dsi_enable_te) |
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void | omapdss_dsi_set_timings (struct omap_dss_device *dssdev, struct omap_video_timings *timings) |
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| EXPORT_SYMBOL (omapdss_dsi_set_timings) |
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void | omapdss_dsi_set_size (struct omap_dss_device *dssdev, u16 w, u16 h) |
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| EXPORT_SYMBOL (omapdss_dsi_set_size) |
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void | omapdss_dsi_set_pixel_format (struct omap_dss_device *dssdev, enum omap_dss_dsi_pixel_format fmt) |
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| EXPORT_SYMBOL (omapdss_dsi_set_pixel_format) |
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void | omapdss_dsi_set_operation_mode (struct omap_dss_device *dssdev, enum omap_dss_dsi_mode mode) |
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| EXPORT_SYMBOL (omapdss_dsi_set_operation_mode) |
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void | omapdss_dsi_set_videomode_timings (struct omap_dss_device *dssdev, struct omap_dss_dsi_videomode_timings *timings) |
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| EXPORT_SYMBOL (omapdss_dsi_set_videomode_timings) |
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int | omap_dsi_request_vc (struct omap_dss_device *dssdev, int *channel) |
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| EXPORT_SYMBOL (omap_dsi_request_vc) |
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int | omap_dsi_set_vc_id (struct omap_dss_device *dssdev, int channel, int vc_id) |
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| EXPORT_SYMBOL (omap_dsi_set_vc_id) |
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void | omap_dsi_release_vc (struct omap_dss_device *dssdev, int channel) |
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| EXPORT_SYMBOL (omap_dsi_release_vc) |
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void | dsi_wait_pll_hsdiv_dispc_active (struct platform_device *dsidev) |
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void | dsi_wait_pll_hsdiv_dsi_active (struct platform_device *dsidev) |
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int __init | dsi_init_platform_driver (void) |
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void __exit | dsi_uninit_platform_driver (void) |
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