#include <linux/phy.h>
#include "common.h"

Macros
#define	GMAC_CONTROL 0x00000000 /* Configuration */

#define	GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */

#define	GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */

#define	GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */

#define	GMAC_MII_ADDR 0x00000010 /* MII Address */

#define	GMAC_MII_DATA 0x00000014 /* MII Data */

#define	GMAC_FLOW_CTRL 0x00000018 /* Flow Control */

#define	GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */

#define	GMAC_VERSION 0x00000020 /* GMAC CORE Version */

#define	GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */

#define	GMAC_INT_STATUS 0x00000038 /* interrupt status register */

#define	GMAC_INT_MASK 0x0000003c /* interrupt mask register */

#define	GMAC_PMT 0x0000002c

#define	LPI_CTRL_STATUS 0x0030

#define	LPI_TIMER_CTRL 0x0034

#define	LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */

#define	LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */

#define	LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */

#define	LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */

#define	LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */

#define	LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */

#define	LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */

#define	LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */

#define	LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */

#define	LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */

#define	GMAC_ADDR_HIGH(reg)

#define	GMAC_ADDR_LOW(reg)

#define	GMAC_MAX_PERFECT_ADDRESSES 32

#define	GMAC_AN_CTRL 0x000000c0 /* AN control */

#define	GMAC_AN_STATUS 0x000000c4 /* AN status */

#define	GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */

#define	GMAC_ANE_LINK 0x000000cc /* Auto-Neg. link partener ability */

#define	GMAC_ANE_EXP 0x000000d0 /* ANE expansion */

#define	GMAC_TBI 0x000000d4 /* TBI extend status */

#define	GMAC_GMII_STATUS 0x000000d8 /* S/R-GMII status */

#define	GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */

#define	GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */

#define	GMAC_CONTROL_JD 0x00400000 /* Jabber disable */

#define	GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */

#define	GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */

#define	GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense during tx */

#define	GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */

#define	GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */

#define	GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */

#define	GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */

#define	GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */

#define	GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */

#define	GMAC_CONTROL_DR 0x00000200 /* Disable Retry */

#define	GMAC_CONTROL_LUD 0x00000100 /* Link up/down */

#define	GMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Stripping */

#define	GMAC_CONTROL_DC 0x00000010 /* Deferral Check */

#define	GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */

#define	GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */

#define	GMAC_CORE_INIT

#define	GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */

#define	GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */

#define	GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */

#define	GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */

#define	GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */

#define	GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */

#define	GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */

#define	GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */

#define	GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */

#define	GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */

#define	GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */

#define	GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */

#define	GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */

#define	GMAC_FLOW_CTRL_PT_SHIFT 16

#define	GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */

#define	GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */

#define	GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */

#define	DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */

#define	DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */

#define	DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */

#define	DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */

#define	DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */

#define	DMA_BUS_MODE_PBL_SHIFT 8

#define	DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */

#define	DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */

#define	DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */

#define	DMA_BUS_MODE_RPBL_SHIFT 17

#define	DMA_BUS_MODE_USP 0x00800000

#define	DMA_BUS_MODE_PBL 0x01000000

#define	DMA_BUS_MODE_AAL 0x02000000

#define	DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */

#define	DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */

#define	DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */

#define	DMA_BUS_PR_RATIO_SHIFT 14

#define	DMA_BUS_FB 0x00010000 /* Fixed Burst */

#define	DMA_CONTROL_DT 0x04000000 /* Disable Drop TCP/IP csum error */

#define	DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */

#define	DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */

#define	DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */

#define	DMA_CONTROL_TC_TX_MASK 0xfffe3fff

#define	DMA_CONTROL_EFC 0x00000100

#define	DMA_CONTROL_FEF 0x00000080

#define	DMA_CONTROL_FUF 0x00000040

#define	DMA_CONTROL_TC_RX_MASK 0xffffffe7

#define	DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */

#define	GMAC_MMC_CTRL 0x100

#define	GMAC_MMC_RX_INTR 0x104

#define	GMAC_MMC_TX_INTR 0x108

#define	GMAC_MMC_RX_CSUM_OFFLOAD 0x208

#define	DWMAC_CORE_3_40 0x34

Enumerations
enum	dwmac1000_irq_status { lpiis_irq = 0x400, time_stamp_irq = 0x0200, mmc_rx_csum_offload_irq = 0x0080, mmc_tx_irq = 0x0040, mmc_rx_irq = 0x0020, mmc_irq = 0x0010, pmt_irq = 0x0008, pcs_ane_irq = 0x0004, pcs_link_irq = 0x0002, rgmii_irq = 0x0001 }

enum	power_event { pointer_reset = 0x80000000, global_unicast = 0x00000200, wake_up_rx_frame = 0x00000040, magic_frame = 0x00000020, wake_up_frame_en = 0x00000004, magic_pkt_en = 0x00000002, power_down = 0x00000001 }

enum	inter_frame_gap { GMAC_CONTROL_IFG_88 = 0x00040000, GMAC_CONTROL_IFG_80 = 0x00020000, GMAC_CONTROL_IFG_40 = 0x000e0000 }

enum	rx_tx_priority_ratio { double_ratio = 0x00004000, triple_ratio = 0x00008000, quadruple_ratio = 0x0000c000 }

enum	rfa { act_full_minus_1 = 0x00800000, act_full_minus_2 = 0x00800200, act_full_minus_3 = 0x00800400, act_full_minus_4 = 0x00800600 }

enum	rfd { deac_full_minus_1 = 0x00400000, deac_full_minus_2 = 0x00400800, deac_full_minus_3 = 0x00401000, deac_full_minus_4 = 0x00401800 }

enum	ttc_control { DMA_CONTROL_TTC_DEFAULT = 0x00000000, DMA_CONTROL_TTC_64 = 0x00004000, DMA_CONTROL_TTC_128 = 0x00008000, DMA_CONTROL_TTC_256 = 0x0000c000, DMA_CONTROL_TTC_18 = 0x00400000, DMA_CONTROL_TTC_24 = 0x00404000, DMA_CONTROL_TTC_32 = 0x00408000, DMA_CONTROL_TTC_40 = 0x0040c000, DMA_CONTROL_SE = 0x00000008, DMA_CONTROL_OSF = 0x00000004, DMA_CONTROL_TTC_64 = 0x00000000, DMA_CONTROL_TTC_128 = 0x00004000, DMA_CONTROL_TTC_192 = 0x00008000, DMA_CONTROL_TTC_256 = 0x0000c000, DMA_CONTROL_TTC_40 = 0x00010000, DMA_CONTROL_TTC_32 = 0x00014000, DMA_CONTROL_TTC_24 = 0x00018000, DMA_CONTROL_TTC_16 = 0x0001c000 }

enum	rtc_control { DMA_CONTROL_RTC_64 = 0x00000000, DMA_CONTROL_RTC_32 = 0x00000008, DMA_CONTROL_RTC_96 = 0x00000010, DMA_CONTROL_RTC_128 = 0x00000018 }

Variables
struct stmmac_dma_ops	dwmac1000_dma_ops

Macro Definition Documentation

#define DMA_BUS_FB 0x00010000 /* Fixed Burst */

Definition at line 179 of file dwmac1000.h.

#define DMA_BUS_MODE_AAL 0x02000000

Definition at line 171 of file dwmac1000.h.

#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */

Definition at line 152 of file dwmac1000.h.

#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */

Definition at line 153 of file dwmac1000.h.

#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */

Definition at line 154 of file dwmac1000.h.

#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */

Definition at line 165 of file dwmac1000.h.

#define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */

Definition at line 166 of file dwmac1000.h.

#define DMA_BUS_MODE_PBL 0x01000000

Definition at line 170 of file dwmac1000.h.

#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */

Definition at line 156 of file dwmac1000.h.

#define DMA_BUS_MODE_PBL_SHIFT 8

Definition at line 157 of file dwmac1000.h.

#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */

Definition at line 167 of file dwmac1000.h.

#define DMA_BUS_MODE_RPBL_SHIFT 17

Definition at line 168 of file dwmac1000.h.

#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */

Definition at line 151 of file dwmac1000.h.

#define DMA_BUS_MODE_USP 0x00800000

Definition at line 169 of file dwmac1000.h.

#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */

Definition at line 177 of file dwmac1000.h.

#define DMA_BUS_PR_RATIO_SHIFT 14

Definition at line 178 of file dwmac1000.h.

#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */

Definition at line 184 of file dwmac1000.h.

#define DMA_CONTROL_DT 0x04000000 /* Disable Drop TCP/IP csum error */

Definition at line 182 of file dwmac1000.h.

#define DMA_CONTROL_EFC 0x00000100

Definition at line 213 of file dwmac1000.h.

#define DMA_CONTROL_FEF 0x00000080

Definition at line 214 of file dwmac1000.h.

#define DMA_CONTROL_FUF 0x00000040

Definition at line 215 of file dwmac1000.h.

#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */

Definition at line 225 of file dwmac1000.h.

#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */

Definition at line 183 of file dwmac1000.h.

#define DMA_CONTROL_TC_RX_MASK 0xffffffe7

Definition at line 223 of file dwmac1000.h.

#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff

Definition at line 211 of file dwmac1000.h.

#define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */

Definition at line 199 of file dwmac1000.h.

#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */

Definition at line 175 of file dwmac1000.h.

#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */

Definition at line 174 of file dwmac1000.h.

#define DWMAC_CORE_3_40 0x34

Definition at line 234 of file dwmac1000.h.

#define GMAC_ADDR_HIGH ( reg )

Value:

(((reg > 15) ? 0x00000800 : 0x00000040) + \

(reg * 8))

Definition at line 86 of file dwmac1000.h.

#define GMAC_ADDR_LOW ( reg )

Value:

(((reg > 15) ? 0x00000804 : 0x00000044) + \

(reg * 8))

Definition at line 88 of file dwmac1000.h.

#define GMAC_AN_CTRL 0x000000c0 /* AN control */

Definition at line 92 of file dwmac1000.h.

#define GMAC_AN_STATUS 0x000000c4 /* AN status */

Definition at line 93 of file dwmac1000.h.

#define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */

Definition at line 94 of file dwmac1000.h.

#define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */

Definition at line 96 of file dwmac1000.h.

#define GMAC_ANE_LINK 0x000000cc /* Auto-Neg. link partener ability */

Definition at line 95 of file dwmac1000.h.

#define GMAC_CONTROL 0x00000000 /* Configuration */

Definition at line 28 of file dwmac1000.h.

#define GMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Stripping */

Definition at line 120 of file dwmac1000.h.

#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */

Definition at line 104 of file dwmac1000.h.

#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */

Definition at line 121 of file dwmac1000.h.

#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense during tx */

Definition at line 111 of file dwmac1000.h.

#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */

Definition at line 116 of file dwmac1000.h.

#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */

Definition at line 114 of file dwmac1000.h.

#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */

Definition at line 118 of file dwmac1000.h.

#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */

Definition at line 113 of file dwmac1000.h.

#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */

Definition at line 117 of file dwmac1000.h.

#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */

Definition at line 103 of file dwmac1000.h.

#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */

Definition at line 105 of file dwmac1000.h.

#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */

Definition at line 115 of file dwmac1000.h.

#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */

Definition at line 119 of file dwmac1000.h.

#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */

Definition at line 112 of file dwmac1000.h.

#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */

Definition at line 123 of file dwmac1000.h.

#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */

Definition at line 101 of file dwmac1000.h.

#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */

Definition at line 122 of file dwmac1000.h.

#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */

Definition at line 102 of file dwmac1000.h.

#define GMAC_CORE_INIT

Value:

(GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \

GMAC_CONTROL_JE | GMAC_CONTROL_BE)

Definition at line 125 of file dwmac1000.h.

#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */

Definition at line 34 of file dwmac1000.h.

#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */

Definition at line 147 of file dwmac1000.h.

#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */

Definition at line 143 of file dwmac1000.h.

#define GMAC_FLOW_CTRL_PT_SHIFT 16

Definition at line 144 of file dwmac1000.h.

#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */

Definition at line 145 of file dwmac1000.h.

#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */

Definition at line 146 of file dwmac1000.h.

#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */

Definition at line 29 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */

Definition at line 132 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */

Definition at line 134 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */

Definition at line 131 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */

Definition at line 137 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */

Definition at line 130 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */

Definition at line 133 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */

Definition at line 129 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */

Definition at line 138 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */

Definition at line 136 of file dwmac1000.h.

#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */

Definition at line 135 of file dwmac1000.h.

#define GMAC_GMII_STATUS 0x000000d8 /* S/R-GMII status */

Definition at line 98 of file dwmac1000.h.

#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */

Definition at line 30 of file dwmac1000.h.

#define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */

Definition at line 31 of file dwmac1000.h.

#define GMAC_INT_MASK 0x0000003c /* interrupt mask register */

Definition at line 52 of file dwmac1000.h.

#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */

Definition at line 39 of file dwmac1000.h.

#define GMAC_MAX_PERFECT_ADDRESSES 32

Definition at line 90 of file dwmac1000.h.

#define GMAC_MII_ADDR 0x00000010 /* MII Address */

Definition at line 32 of file dwmac1000.h.

#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */

Definition at line 141 of file dwmac1000.h.

#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */

Definition at line 140 of file dwmac1000.h.

#define GMAC_MII_DATA 0x00000014 /* MII Data */

Definition at line 33 of file dwmac1000.h.

#define GMAC_MMC_CTRL 0x100

Definition at line 228 of file dwmac1000.h.

#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208

Definition at line 231 of file dwmac1000.h.

#define GMAC_MMC_RX_INTR 0x104

Definition at line 229 of file dwmac1000.h.

#define GMAC_MMC_TX_INTR 0x108

Definition at line 230 of file dwmac1000.h.

#define GMAC_PMT 0x0000002c

Definition at line 55 of file dwmac1000.h.

#define GMAC_TBI 0x000000d4 /* TBI extend status */

Definition at line 97 of file dwmac1000.h.

#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */

Definition at line 36 of file dwmac1000.h.

#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */

Definition at line 35 of file dwmac1000.h.

#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */

Definition at line 37 of file dwmac1000.h.

#define LPI_CTRL_STATUS 0x0030

Definition at line 70 of file dwmac1000.h.

#define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */

Definition at line 77 of file dwmac1000.h.

#define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */

Definition at line 74 of file dwmac1000.h.

#define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */

Definition at line 76 of file dwmac1000.h.

#define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */

Definition at line 75 of file dwmac1000.h.

#define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */

Definition at line 81 of file dwmac1000.h.

#define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */

Definition at line 80 of file dwmac1000.h.

#define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */

Definition at line 78 of file dwmac1000.h.

#define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */

Definition at line 83 of file dwmac1000.h.

#define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */

Definition at line 82 of file dwmac1000.h.

#define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */

Definition at line 79 of file dwmac1000.h.

#define LPI_TIMER_CTRL 0x0034

Definition at line 71 of file dwmac1000.h.

Enumeration Type Documentation

enum dwmac1000_irq_status

Enumerator:

lpiis_irq
time_stamp_irq
mmc_rx_csum_offload_irq
mmc_tx_irq
mmc_rx_irq
mmc_irq
pmt_irq
pcs_ane_irq
pcs_link_irq
rgmii_irq

Definition at line 40 of file dwmac1000.h.

enum inter_frame_gap

Enumerator:

GMAC_CONTROL_IFG_88
GMAC_CONTROL_IFG_80
GMAC_CONTROL_IFG_40

Definition at line 106 of file dwmac1000.h.

enum power_event

Enumerator:

pointer_reset
global_unicast
wake_up_rx_frame
magic_frame
wake_up_frame_en
magic_pkt_en
power_down

Definition at line 56 of file dwmac1000.h.

enum rfa

Enumerator:

act_full_minus_1
act_full_minus_2
act_full_minus_3
act_full_minus_4

Definition at line 186 of file dwmac1000.h.

enum rfd

Enumerator:

deac_full_minus_1
deac_full_minus_2
deac_full_minus_3
deac_full_minus_4

Definition at line 193 of file dwmac1000.h.

enum rtc_control

Enumerator:

DMA_CONTROL_RTC_64
DMA_CONTROL_RTC_32
DMA_CONTROL_RTC_96
DMA_CONTROL_RTC_128

Definition at line 217 of file dwmac1000.h.

enum rx_tx_priority_ratio

Enumerator:

double_ratio
triple_ratio
quadruple_ratio

Definition at line 159 of file dwmac1000.h.

enum ttc_control

Enumerator:

DMA_CONTROL_TTC_DEFAULT
DMA_CONTROL_TTC_64
DMA_CONTROL_TTC_128
DMA_CONTROL_TTC_256
DMA_CONTROL_TTC_18
DMA_CONTROL_TTC_24
DMA_CONTROL_TTC_32
DMA_CONTROL_TTC_40
DMA_CONTROL_SE
DMA_CONTROL_OSF
DMA_CONTROL_TTC_64
DMA_CONTROL_TTC_128
DMA_CONTROL_TTC_192
DMA_CONTROL_TTC_256
DMA_CONTROL_TTC_40
DMA_CONTROL_TTC_32
DMA_CONTROL_TTC_24
DMA_CONTROL_TTC_16

Definition at line 201 of file dwmac1000.h.

Variable Documentation

struct stmmac_dma_ops dwmac1000_dma_ops

Definition at line 177 of file dwmac1000_dma.c.

Macros

Enumerations

Variables

Macro Definition Documentation

Enumeration Type Documentation

Variable Documentation