#include <linux/phy.h>
#include "common.h"

Macros
#define	MAC_CONTROL 0x00000000 /* MAC Control */

#define	MAC_ADDR_HIGH 0x00000004 /* MAC Address High */

#define	MAC_ADDR_LOW 0x00000008 /* MAC Address Low */

#define	MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */

#define	MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */

#define	MAC_MII_ADDR 0x00000014 /* MII Address */

#define	MAC_MII_DATA 0x00000018 /* MII Data */

#define	MAC_FLOW_CTRL 0x0000001c /* Flow Control */

#define	MAC_VLAN1 0x00000020 /* VLAN1 Tag */

#define	MAC_VLAN2 0x00000024 /* VLAN2 Tag */

#define	MAC_CONTROL_RA 0x80000000 /* Receive All Mode */

#define	MAC_CONTROL_BLE 0x40000000 /* Endian Mode */

#define	MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */

#define	MAC_CONTROL_PS 0x08000000 /* Port Select */

#define	MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */

#define	MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */

#define	MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */

#define	MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */

#define	MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */

#define	MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */

#define	MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */

#define	MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */

#define	MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */

#define	MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */

#define	MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */

#define	MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */

#define	MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */

#define	MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */

#define	MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */

#define	MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */

#define	MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */

#define	MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */

#define	MAC_CONTROL_DC 0x00000020 /* Deferral Check */

#define	MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */

#define	MAC_CONTROL_RE 0x00000004 /* Receiver Enable */

#define	MAC_CORE_INIT (MAC_CONTROL_HBD \| MAC_CONTROL_ASTP)

#define	MAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */

#define	MAC_FLOW_CTRL_PT_SHIFT 16

#define	MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */

#define	MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */

#define	MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */

#define	MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */

#define	MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */

#define	DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */

#define	DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */

#define	DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */

#define	DMA_BUS_MODE_PBL_SHIFT 8

#define	DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */

#define	DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */

#define	DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */

#define	DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */

#define	DMA_BUS_MODE_DEFAULT 0x00000000

#define	DMA_CONTROL_SF 0x00200000 /* Store And Forward */

#define	DMA_MISSED_FRAME_OVE 0x10000000 /* FIFO Overflow Overflow */

#define	DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000 /* Overflow Frame Counter */

#define	DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */

#define	DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */

Enumerations
enum	ttc_control { DMA_CONTROL_TTC_DEFAULT = 0x00000000, DMA_CONTROL_TTC_64 = 0x00004000, DMA_CONTROL_TTC_128 = 0x00008000, DMA_CONTROL_TTC_256 = 0x0000c000, DMA_CONTROL_TTC_18 = 0x00400000, DMA_CONTROL_TTC_24 = 0x00404000, DMA_CONTROL_TTC_32 = 0x00408000, DMA_CONTROL_TTC_40 = 0x0040c000, DMA_CONTROL_SE = 0x00000008, DMA_CONTROL_OSF = 0x00000004, DMA_CONTROL_TTC_64 = 0x00000000, DMA_CONTROL_TTC_128 = 0x00004000, DMA_CONTROL_TTC_192 = 0x00008000, DMA_CONTROL_TTC_256 = 0x0000c000, DMA_CONTROL_TTC_40 = 0x00010000, DMA_CONTROL_TTC_32 = 0x00014000, DMA_CONTROL_TTC_24 = 0x00018000, DMA_CONTROL_TTC_16 = 0x0001c000 }

Variables
struct stmmac_dma_ops	dwmac100_dma_ops

Macro Definition Documentation

#define DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */

Definition at line 97 of file dwmac100.h.

#define DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */

Definition at line 92 of file dwmac100.h.

#define DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */

Definition at line 91 of file dwmac100.h.

#define DMA_BUS_MODE_DEFAULT 0x00000000

Definition at line 99 of file dwmac100.h.

#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */

Definition at line 95 of file dwmac100.h.

#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */

Definition at line 96 of file dwmac100.h.

#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */

Definition at line 93 of file dwmac100.h.

#define DMA_BUS_MODE_PBL_SHIFT 8

Definition at line 94 of file dwmac100.h.

#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */

Definition at line 98 of file dwmac100.h.

#define DMA_CONTROL_SF 0x00200000 /* Store And Forward */

Definition at line 102 of file dwmac100.h.

#define DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */

Definition at line 122 of file dwmac100.h.

#define DMA_MISSED_FRAME_OVE 0x10000000 /* FIFO Overflow Overflow */

Definition at line 119 of file dwmac100.h.

#define DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000 /* Overflow Frame Counter */

Definition at line 120 of file dwmac100.h.

#define DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */

Definition at line 121 of file dwmac100.h.

#define MAC_ADDR_HIGH 0x00000004 /* MAC Address High */

Definition at line 36 of file dwmac100.h.

#define MAC_ADDR_LOW 0x00000008 /* MAC Address Low */

Definition at line 37 of file dwmac100.h.

#define MAC_CONTROL 0x00000000 /* MAC Control */

Definition at line 35 of file dwmac100.h.

#define MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */

Definition at line 64 of file dwmac100.h.

#define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */

Definition at line 48 of file dwmac100.h.

#define MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */

Definition at line 68 of file dwmac100.h.

#define MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */

Definition at line 65 of file dwmac100.h.

#define MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */

Definition at line 67 of file dwmac100.h.

#define MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */

Definition at line 66 of file dwmac100.h.

#define MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */

Definition at line 62 of file dwmac100.h.

#define MAC_CONTROL_DC 0x00000020 /* Deferral Check */

Definition at line 69 of file dwmac100.h.

#define MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */

Definition at line 51 of file dwmac100.h.

#define MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */

Definition at line 63 of file dwmac100.h.

#define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */

Definition at line 52 of file dwmac100.h.

#define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */

Definition at line 54 of file dwmac100.h.

#define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */

Definition at line 49 of file dwmac100.h.

#define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */

Definition at line 59 of file dwmac100.h.

#define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */

Definition at line 60 of file dwmac100.h.

#define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */

Definition at line 57 of file dwmac100.h.

#define MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */

Definition at line 61 of file dwmac100.h.

#define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */

Definition at line 53 of file dwmac100.h.

#define MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */

Definition at line 58 of file dwmac100.h.

#define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */

Definition at line 55 of file dwmac100.h.

#define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */

Definition at line 56 of file dwmac100.h.

#define MAC_CONTROL_PS 0x08000000 /* Port Select */

Definition at line 50 of file dwmac100.h.

#define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */

Definition at line 47 of file dwmac100.h.

#define MAC_CONTROL_RE 0x00000004 /* Receiver Enable */

Definition at line 71 of file dwmac100.h.

#define MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */

Definition at line 70 of file dwmac100.h.

#define MAC_CORE_INIT (MAC_CONTROL_HBD | MAC_CONTROL_ASTP)

Definition at line 73 of file dwmac100.h.

#define MAC_FLOW_CTRL 0x0000001c /* Flow Control */

Definition at line 42 of file dwmac100.h.

#define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */

Definition at line 79 of file dwmac100.h.

#define MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */

Definition at line 78 of file dwmac100.h.

#define MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */

Definition at line 80 of file dwmac100.h.

#define MAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */

Definition at line 76 of file dwmac100.h.

#define MAC_FLOW_CTRL_PT_SHIFT 16

Definition at line 77 of file dwmac100.h.

#define MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */

Definition at line 38 of file dwmac100.h.

#define MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */

Definition at line 39 of file dwmac100.h.

#define MAC_MII_ADDR 0x00000014 /* MII Address */

Definition at line 40 of file dwmac100.h.

#define MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */

Definition at line 84 of file dwmac100.h.

#define MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */

Definition at line 83 of file dwmac100.h.

#define MAC_MII_DATA 0x00000018 /* MII Data */

Definition at line 41 of file dwmac100.h.

#define MAC_VLAN1 0x00000020 /* VLAN1 Tag */

Definition at line 43 of file dwmac100.h.

#define MAC_VLAN2 0x00000024 /* VLAN2 Tag */

Definition at line 44 of file dwmac100.h.

Enumeration Type Documentation

enum ttc_control

Enumerator:

DMA_CONTROL_TTC_DEFAULT
DMA_CONTROL_TTC_64
DMA_CONTROL_TTC_128
DMA_CONTROL_TTC_256
DMA_CONTROL_TTC_18
DMA_CONTROL_TTC_24
DMA_CONTROL_TTC_32
DMA_CONTROL_TTC_40
DMA_CONTROL_SE
DMA_CONTROL_OSF
DMA_CONTROL_TTC_64
DMA_CONTROL_TTC_128
DMA_CONTROL_TTC_192
DMA_CONTROL_TTC_256
DMA_CONTROL_TTC_40
DMA_CONTROL_TTC_32
DMA_CONTROL_TTC_24
DMA_CONTROL_TTC_16

Definition at line 105 of file dwmac100.h.

Variable Documentation

struct stmmac_dma_ops dwmac100_dma_ops

Definition at line 131 of file dwmac100_dma.c.

Macros

Enumerations

Variables

Macro Definition Documentation

Enumeration Type Documentation

Variable Documentation