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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | esp_cmd_priv |
| struct | esp_cmd_entry |
| struct | esp_lun_data |
| struct | esp_target_data |
| struct | esp_event_ent |
| struct | esp_driver_ops |
| struct | esp |
Macros | |
| #define | ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */ |
| #define | ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */ |
| #define | ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */ |
| #define | ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */ |
| #define | ESP_STATUS 0x04UL /* ro ESP status register 0x10 */ |
| #define | ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */ |
| #define | ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */ |
| #define | ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */ |
| #define | ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */ |
| #define | ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */ |
| #define | ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */ |
| #define | ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */ |
| #define | ESP_CFG1 0x08UL /* rw First cfg register 0x20 */ |
| #define | ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */ |
| #define | ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */ |
| #define | ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */ |
| #define | ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */ |
| #define | ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */ |
| #define | ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */ |
| #define | ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */ |
| #define | FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */ |
| #define | ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */ |
| #define | FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */ |
| #define | SBUS_ESP_REG_SIZE 0x40UL |
| #define | ESP_CONFIG1_ID 0x07 /* My BUS ID bits */ |
| #define | ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */ |
| #define | ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */ |
| #define | ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */ |
| #define | ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */ |
| #define | ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */ |
| #define | ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */ |
| #define | ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */ |
| #define | ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */ |
| #define | ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */ |
| #define | ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */ |
| #define | ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */ |
| #define | ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */ |
| #define | ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */ |
| #define | ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */ |
| #define | ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */ |
| #define | ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */ |
| #define | ESP_CONFIG2_HME32 0x80 /* HME 32 extended */ |
| #define | ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */ |
| #define | ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */ |
| #define | ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */ |
| #define | ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */ |
| #define | ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */ |
| #define | ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */ |
| #define | ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */ |
| #define | ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */ |
| #define | ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */ |
| #define | ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */ |
| #define | ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */ |
| #define | ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */ |
| #define | ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */ |
| #define | ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */ |
| #define | ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */ |
| #define | ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ |
| #define | ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ |
| #define | ESP_CMD_NULL 0x00 /* Null command, ie. a nop */ |
| #define | ESP_CMD_FLUSH 0x01 /* FIFO Flush */ |
| #define | ESP_CMD_RC 0x02 /* Chip reset */ |
| #define | ESP_CMD_RS 0x03 /* SCSI bus reset */ |
| #define | ESP_CMD_TI 0x10 /* Transfer Information */ |
| #define | ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */ |
| #define | ESP_CMD_MOK 0x12 /* Message okie-dokie */ |
| #define | ESP_CMD_TPAD 0x18 /* Transfer Pad */ |
| #define | ESP_CMD_SATN 0x1a /* Set ATN */ |
| #define | ESP_CMD_RATN 0x1b /* De-assert ATN */ |
| #define | ESP_CMD_SMSG 0x20 /* Send message */ |
| #define | ESP_CMD_SSTAT 0x21 /* Send status */ |
| #define | ESP_CMD_SDATA 0x22 /* Send data */ |
| #define | ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */ |
| #define | ESP_CMD_TSEQ 0x24 /* Terminate Sequence */ |
| #define | ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */ |
| #define | ESP_CMD_DCNCT 0x27 /* Disconnect */ |
| #define | ESP_CMD_RMSG 0x28 /* Receive Message */ |
| #define | ESP_CMD_RCMD 0x29 /* Receive Command */ |
| #define | ESP_CMD_RDATA 0x2a /* Receive Data */ |
| #define | ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */ |
| #define | ESP_CMD_RSEL 0x40 /* Reselect */ |
| #define | ESP_CMD_SEL 0x41 /* Select w/o ATN */ |
| #define | ESP_CMD_SELA 0x42 /* Select w/ATN */ |
| #define | ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */ |
| #define | ESP_CMD_ESEL 0x44 /* Enable selection */ |
| #define | ESP_CMD_DSEL 0x45 /* Disable selections */ |
| #define | ESP_CMD_SA3 0x46 /* Select w/ATN3 */ |
| #define | ESP_CMD_RSEL3 0x47 /* Reselect3 */ |
| #define | ESP_CMD_DMA 0x80 /* Do DMA? */ |
| #define | ESP_STAT_PIO 0x01 /* IO phase bit */ |
| #define | ESP_STAT_PCD 0x02 /* CD phase bit */ |
| #define | ESP_STAT_PMSG 0x04 /* MSG phase bit */ |
| #define | ESP_STAT_PMASK 0x07 /* Mask of phase bits */ |
| #define | ESP_STAT_TDONE 0x08 /* Transfer Completed */ |
| #define | ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */ |
| #define | ESP_STAT_PERR 0x20 /* Parity error */ |
| #define | ESP_STAT_SPAM 0x40 /* Real bad error */ |
| #define | ESP_STAT_INTR 0x80 /* Interrupt */ |
| #define | ESP_DOP (0) /* Data Out */ |
| #define | ESP_DIP (ESP_STAT_PIO) /* Data In */ |
| #define | ESP_CMDP (ESP_STAT_PCD) /* Command */ |
| #define | ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */ |
| #define | ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */ |
| #define | ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */ |
| #define | ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */ |
| #define | ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */ |
| #define | ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */ |
| #define | ESP_STAT2_CREGA 0x08 /* The command reg is active now */ |
| #define | ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */ |
| #define | ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */ |
| #define | ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */ |
| #define | ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */ |
| #define | ESP_INTR_S 0x01 /* Select w/o ATN */ |
| #define | ESP_INTR_SATN 0x02 /* Select w/ATN */ |
| #define | ESP_INTR_RSEL 0x04 /* Reselected */ |
| #define | ESP_INTR_FDONE 0x08 /* Function done */ |
| #define | ESP_INTR_BSERV 0x10 /* Bus service */ |
| #define | ESP_INTR_DC 0x20 /* Disconnect */ |
| #define | ESP_INTR_IC 0x40 /* Illegal command given */ |
| #define | ESP_INTR_SR 0x80 /* SCSI bus reset detected */ |
| #define | ESP_STEP_VBITS 0x07 /* Valid bits */ |
| #define | ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */ |
| #define | ESP_STEP_SID 0x01 /* One msg byte sent */ |
| #define | ESP_STEP_NCMD 0x02 /* Was not in command phase */ |
| #define | ESP_STEP_PPC |
| #define | ESP_STEP_FINI4 0x04 /* Command was sent ok */ |
| #define | ESP_STEP_FINI5 0x05 |
| #define | ESP_STEP_FINI6 0x06 |
| #define | ESP_STEP_FINI7 0x07 |
| #define | ESP_TEST_TARG 0x01 /* Target test mode */ |
| #define | ESP_TEST_INI 0x02 /* Initiator test mode */ |
| #define | ESP_TEST_TS 0x04 /* Tristate test mode */ |
| #define | ESP_UID_F100A 0x00 /* ESP FAS100A */ |
| #define | ESP_UID_F236 0x02 /* ESP FAS236 */ |
| #define | ESP_UID_REV 0x07 /* ESP revision */ |
| #define | ESP_UID_FAM 0xf8 /* ESP family */ |
| #define | ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */ |
| #define | ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */ |
| #define | ESP_FF_SSTEP 0xe0 /* Sequence step */ |
| #define | ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */ |
| #define | ESP_CCF_NEVER 0x01 /* Set it to this and die */ |
| #define | ESP_CCF_F2 0x02 /* 10MHz */ |
| #define | ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */ |
| #define | ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */ |
| #define | ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */ |
| #define | ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */ |
| #define | ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */ |
| #define | ESP_BUSID_RESELID 0x10 |
| #define | ESP_BUSID_CTR32BIT 0x40 |
| #define | ESP_BUS_TIMEOUT 250 /* In milli-seconds */ |
| #define | ESP_TIMEO_CONST 8192 |
| #define | ESP_NEG_DEFP(mhz, cfact) ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) |
| #define | ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000)) |
| #define | ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) |
| #define | SYNC_DEFP_SLOW 0x32 /* 5mb/s */ |
| #define | SYNC_DEFP_FAST 0x19 /* 10mb/s */ |
| #define | ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp)) |
| #define | ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */ |
| #define | ESP_CMD_FLAG_ABORT 0x02 /* being aborted */ |
| #define | ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */ |
| #define | ESP_DEFAULT_TAGS 16 |
| #define | ESP_MAX_TARGET 16 |
| #define | ESP_MAX_LUN 8 |
| #define | ESP_MAX_TAG 256 |
| #define | ESP_TGT_WIDE 0x01 |
| #define | ESP_TGT_DISCONNECT 0x02 |
| #define | ESP_TGT_NEGO_WIDE 0x04 |
| #define | ESP_TGT_NEGO_SYNC 0x08 |
| #define | ESP_TGT_CHECK_NEGO 0x40 |
| #define | ESP_TGT_BROKEN 0x80 |
| #define | ESP_EVENT_TYPE_EVENT 0x01 |
| #define | ESP_EVENT_TYPE_CMD 0x02 |
| #define | ESP_MAX_MSG_SZ 8 |
| #define | ESP_EVENT_LOG_SZ 32 |
| #define | ESP_QUICKIRQ_LIMIT 100 |
| #define | ESP_RESELECT_TAG_LIMIT 2500 |
| #define | ESP_FLAG_DIFFERENTIAL 0x00000001 |
| #define | ESP_FLAG_RESETTING 0x00000002 |
| #define | ESP_FLAG_DOING_SLOWCMD 0x00000004 |
| #define | ESP_FLAG_WIDE_CAPABLE 0x00000008 |
| #define | ESP_FLAG_QUICKIRQ_CHECK 0x00000010 |
| #define | ESP_FLAG_DISABLE_SYNC 0x00000020 |
| #define | ESP_SELECT_NONE 0x00 /* Not selecting */ |
| #define | ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */ |
| #define | ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */ |
| #define | ESP_EVENT_NONE 0x00 |
| #define | ESP_EVENT_CMD_START 0x01 |
| #define | ESP_EVENT_CMD_DONE 0x02 |
| #define | ESP_EVENT_DATA_IN 0x03 |
| #define | ESP_EVENT_DATA_OUT 0x04 |
| #define | ESP_EVENT_DATA_DONE 0x05 |
| #define | ESP_EVENT_MSGIN 0x06 |
| #define | ESP_EVENT_MSGIN_MORE 0x07 |
| #define | ESP_EVENT_MSGIN_DONE 0x08 |
| #define | ESP_EVENT_MSGOUT 0x09 |
| #define | ESP_EVENT_MSGOUT_DONE 0x0a |
| #define | ESP_EVENT_STATUS 0x0b |
| #define | ESP_EVENT_FREE_BUS 0x0c |
| #define | ESP_EVENT_CHECK_PHASE 0x0d |
| #define | ESP_EVENT_RESET 0x10 |
Enumerations | |
| enum | esp_rev { ESP100 = 0x00, ESP100A = 0x01, ESP236 = 0x02, FAS236 = 0x03, FAS100A = 0x04, FAST = 0x05, FASHME = 0x06 } |
Functions | |
| int | scsi_esp_register (struct esp *, struct device *) |
| void | scsi_esp_unregister (struct esp *) |
| irqreturn_t | scsi_esp_intr (int, void *) |
| void | scsi_esp_cmd (struct esp *, u8) |
Variables | |
| struct scsi_host_template | scsi_esp_template |
| #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */ |
Definition at line 221 of file esp_scsi.h.
| #define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */ |
Definition at line 15 of file esp_scsi.h.
| #define ESP_BUSID_CTR32BIT 0x40 |
Definition at line 219 of file esp_scsi.h.
| #define ESP_BUSID_RESELID 0x10 |
Definition at line 218 of file esp_scsi.h.
| #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */ |
Definition at line 208 of file esp_scsi.h.
| #define ESP_CCF_F2 0x02 /* 10MHz */ |
Definition at line 210 of file esp_scsi.h.
| #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */ |
Definition at line 211 of file esp_scsi.h.
| #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */ |
Definition at line 212 of file esp_scsi.h.
| #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */ |
Definition at line 213 of file esp_scsi.h.
| #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */ |
Definition at line 214 of file esp_scsi.h.
| #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */ |
Definition at line 215 of file esp_scsi.h.
| #define ESP_CCF_NEVER 0x01 /* Set it to this and die */ |
Definition at line 209 of file esp_scsi.h.
| #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */ |
Definition at line 23 of file esp_scsi.h.
| #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */ |
Definition at line 22 of file esp_scsi.h.
| #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */ |
Definition at line 26 of file esp_scsi.h.
| #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */ |
Definition at line 27 of file esp_scsi.h.
| #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */ |
Definition at line 13 of file esp_scsi.h.
| #define ESP_CMD_DCNCT 0x27 /* Disconnect */ |
Definition at line 109 of file esp_scsi.h.
| #define ESP_CMD_DMA 0x80 /* Do DMA? */ |
Definition at line 129 of file esp_scsi.h.
| #define ESP_CMD_DSEL 0x45 /* Disable selections */ |
Definition at line 124 of file esp_scsi.h.
| #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */ |
Definition at line 106 of file esp_scsi.h.
| #define ESP_CMD_ESEL 0x44 /* Enable selection */ |
Definition at line 123 of file esp_scsi.h.
| #define ESP_CMD_FLAG_ABORT 0x02 /* being aborted */ |
Definition at line 268 of file esp_scsi.h.
| #define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */ |
Definition at line 269 of file esp_scsi.h.
| #define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */ |
Definition at line 267 of file esp_scsi.h.
| #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */ |
Definition at line 86 of file esp_scsi.h.
| #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */ |
Definition at line 94 of file esp_scsi.h.
| #define ESP_CMD_MOK 0x12 /* Message okie-dokie */ |
Definition at line 95 of file esp_scsi.h.
| #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */ |
Definition at line 85 of file esp_scsi.h.
| #define ESP_CMD_PRIV | ( | CMD | ) | ((struct esp_cmd_priv *)(&(CMD)->SCp)) |
Definition at line 245 of file esp_scsi.h.
| #define ESP_CMD_RATN 0x1b /* De-assert ATN */ |
Definition at line 98 of file esp_scsi.h.
| #define ESP_CMD_RC 0x02 /* Chip reset */ |
Definition at line 87 of file esp_scsi.h.
| #define ESP_CMD_RCMD 0x29 /* Receive Command */ |
Definition at line 111 of file esp_scsi.h.
| #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */ |
Definition at line 113 of file esp_scsi.h.
| #define ESP_CMD_RDATA 0x2a /* Receive Data */ |
Definition at line 112 of file esp_scsi.h.
| #define ESP_CMD_RMSG 0x28 /* Receive Message */ |
Definition at line 110 of file esp_scsi.h.
| #define ESP_CMD_RS 0x03 /* SCSI bus reset */ |
Definition at line 88 of file esp_scsi.h.
| #define ESP_CMD_RSEL 0x40 /* Reselect */ |
Definition at line 119 of file esp_scsi.h.
| #define ESP_CMD_RSEL3 0x47 /* Reselect3 */ |
Definition at line 126 of file esp_scsi.h.
| #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */ |
Definition at line 125 of file esp_scsi.h.
| #define ESP_CMD_SATN 0x1a /* Set ATN */ |
Definition at line 97 of file esp_scsi.h.
| #define ESP_CMD_SDATA 0x22 /* Send data */ |
Definition at line 105 of file esp_scsi.h.
| #define ESP_CMD_SEL 0x41 /* Select w/o ATN */ |
Definition at line 120 of file esp_scsi.h.
| #define ESP_CMD_SELA 0x42 /* Select w/ATN */ |
Definition at line 121 of file esp_scsi.h.
| #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */ |
Definition at line 122 of file esp_scsi.h.
| #define ESP_CMD_SMSG 0x20 /* Send message */ |
Definition at line 103 of file esp_scsi.h.
| #define ESP_CMD_SSTAT 0x21 /* Send status */ |
Definition at line 104 of file esp_scsi.h.
| #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */ |
Definition at line 108 of file esp_scsi.h.
| #define ESP_CMD_TI 0x10 /* Transfer Information */ |
Definition at line 93 of file esp_scsi.h.
| #define ESP_CMD_TPAD 0x18 /* Transfer Pad */ |
Definition at line 96 of file esp_scsi.h.
| #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */ |
Definition at line 107 of file esp_scsi.h.
| #define ESP_CMDP (ESP_STAT_PCD) /* Command */ |
Definition at line 152 of file esp_scsi.h.
| #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */ |
Definition at line 40 of file esp_scsi.h.
| #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */ |
Definition at line 39 of file esp_scsi.h.
| #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */ |
Definition at line 42 of file esp_scsi.h.
| #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */ |
Definition at line 41 of file esp_scsi.h.
| #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */ |
Definition at line 44 of file esp_scsi.h.
| #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */ |
Definition at line 43 of file esp_scsi.h.
| #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */ |
Definition at line 49 of file esp_scsi.h.
| #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */ |
Definition at line 53 of file esp_scsi.h.
| #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */ |
Definition at line 54 of file esp_scsi.h.
| #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */ |
Definition at line 47 of file esp_scsi.h.
| #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */ |
Definition at line 55 of file esp_scsi.h.
| #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */ |
Definition at line 51 of file esp_scsi.h.
| #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */ |
Definition at line 58 of file esp_scsi.h.
| #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */ |
Definition at line 52 of file esp_scsi.h.
| #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */ |
Definition at line 59 of file esp_scsi.h.
| #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */ |
Definition at line 57 of file esp_scsi.h.
| #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */ |
Definition at line 48 of file esp_scsi.h.
| #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */ |
Definition at line 50 of file esp_scsi.h.
| #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */ |
Definition at line 56 of file esp_scsi.h.
| #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */ |
Definition at line 65 of file esp_scsi.h.
| #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */ |
Definition at line 75 of file esp_scsi.h.
| #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */ |
Definition at line 64 of file esp_scsi.h.
| #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */ |
Definition at line 69 of file esp_scsi.h.
| #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */ |
Definition at line 62 of file esp_scsi.h.
| #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */ |
Definition at line 71 of file esp_scsi.h.
| #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */ |
Definition at line 72 of file esp_scsi.h.
| #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */ |
Definition at line 73 of file esp_scsi.h.
| #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */ |
Definition at line 70 of file esp_scsi.h.
| #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ |
Definition at line 76 of file esp_scsi.h.
| #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ |
Definition at line 77 of file esp_scsi.h.
| #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */ |
Definition at line 67 of file esp_scsi.h.
| #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */ |
Definition at line 74 of file esp_scsi.h.
| #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */ |
Definition at line 63 of file esp_scsi.h.
| #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */ |
Definition at line 66 of file esp_scsi.h.
| #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */ |
Definition at line 68 of file esp_scsi.h.
| #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */ |
Definition at line 25 of file esp_scsi.h.
| #define ESP_DEFAULT_TAGS 16 |
Definition at line 284 of file esp_scsi.h.
| #define ESP_DIP (ESP_STAT_PIO) /* Data In */ |
Definition at line 151 of file esp_scsi.h.
| #define ESP_DOP (0) /* Data Out */ |
Definition at line 150 of file esp_scsi.h.
| #define ESP_EVENT_CHECK_PHASE 0x0d |
Definition at line 500 of file esp_scsi.h.
| #define ESP_EVENT_CMD_DONE 0x02 |
Definition at line 489 of file esp_scsi.h.
| #define ESP_EVENT_CMD_START 0x01 |
Definition at line 488 of file esp_scsi.h.
| #define ESP_EVENT_DATA_DONE 0x05 |
Definition at line 492 of file esp_scsi.h.
| #define ESP_EVENT_DATA_IN 0x03 |
Definition at line 490 of file esp_scsi.h.
| #define ESP_EVENT_DATA_OUT 0x04 |
Definition at line 491 of file esp_scsi.h.
| #define ESP_EVENT_FREE_BUS 0x0c |
Definition at line 499 of file esp_scsi.h.
| #define ESP_EVENT_LOG_SZ 32 |
Definition at line 409 of file esp_scsi.h.
| #define ESP_EVENT_MSGIN 0x06 |
Definition at line 493 of file esp_scsi.h.
| #define ESP_EVENT_MSGIN_DONE 0x08 |
Definition at line 495 of file esp_scsi.h.
| #define ESP_EVENT_MSGIN_MORE 0x07 |
Definition at line 494 of file esp_scsi.h.
| #define ESP_EVENT_MSGOUT 0x09 |
Definition at line 496 of file esp_scsi.h.
| #define ESP_EVENT_MSGOUT_DONE 0x0a |
Definition at line 497 of file esp_scsi.h.
| #define ESP_EVENT_NONE 0x00 |
Definition at line 487 of file esp_scsi.h.
| #define ESP_EVENT_RESET 0x10 |
Definition at line 501 of file esp_scsi.h.
| #define ESP_EVENT_STATUS 0x0b |
Definition at line 498 of file esp_scsi.h.
| #define ESP_EVENT_TYPE_CMD 0x02 |
Definition at line 328 of file esp_scsi.h.
| #define ESP_EVENT_TYPE_EVENT 0x01 |
Definition at line 327 of file esp_scsi.h.
| #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */ |
Definition at line 12 of file esp_scsi.h.
| #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */ |
Definition at line 203 of file esp_scsi.h.
| #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */ |
Definition at line 204 of file esp_scsi.h.
| #define ESP_FF_SSTEP 0xe0 /* Sequence step */ |
Definition at line 205 of file esp_scsi.h.
| #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */ |
Definition at line 20 of file esp_scsi.h.
| #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */ |
Definition at line 31 of file esp_scsi.h.
| #define ESP_FLAG_DIFFERENTIAL 0x00000001 |
Definition at line 473 of file esp_scsi.h.
| #define ESP_FLAG_DISABLE_SYNC 0x00000020 |
Definition at line 478 of file esp_scsi.h.
| #define ESP_FLAG_DOING_SLOWCMD 0x00000004 |
Definition at line 475 of file esp_scsi.h.
| #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010 |
Definition at line 477 of file esp_scsi.h.
| #define ESP_FLAG_RESETTING 0x00000002 |
Definition at line 474 of file esp_scsi.h.
| #define ESP_FLAG_WIDE_CAPABLE 0x00000008 |
Definition at line 476 of file esp_scsi.h.
| #define ESP_HZ_TO_CYCLE | ( | hertz | ) | ((1000000000) / ((hertz) / 1000)) |
Definition at line 225 of file esp_scsi.h.
| #define ESP_INTR_BSERV 0x10 /* Bus service */ |
Definition at line 172 of file esp_scsi.h.
| #define ESP_INTR_DC 0x20 /* Disconnect */ |
Definition at line 173 of file esp_scsi.h.
| #define ESP_INTR_FDONE 0x08 /* Function done */ |
Definition at line 171 of file esp_scsi.h.
| #define ESP_INTR_IC 0x40 /* Illegal command given */ |
Definition at line 174 of file esp_scsi.h.
| #define ESP_INTR_RSEL 0x04 /* Reselected */ |
Definition at line 170 of file esp_scsi.h.
| #define ESP_INTR_S 0x01 /* Select w/o ATN */ |
Definition at line 168 of file esp_scsi.h.
| #define ESP_INTR_SATN 0x02 /* Select w/ATN */ |
Definition at line 169 of file esp_scsi.h.
| #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */ |
Definition at line 175 of file esp_scsi.h.
| #define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */ |
Definition at line 16 of file esp_scsi.h.
| #define ESP_MAX_LUN 8 |
Definition at line 287 of file esp_scsi.h.
| #define ESP_MAX_MSG_SZ 8 |
Definition at line 408 of file esp_scsi.h.
| #define ESP_MAX_TAG 256 |
Definition at line 288 of file esp_scsi.h.
| #define ESP_MAX_TARGET 16 |
Definition at line 286 of file esp_scsi.h.
| #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */ |
Definition at line 155 of file esp_scsi.h.
| #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */ |
Definition at line 154 of file esp_scsi.h.
| #define ESP_NEG_DEFP | ( | mhz, | |
| cfact | |||
| ) | ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) |
Definition at line 223 of file esp_scsi.h.
| #define ESP_QUICKIRQ_LIMIT 100 |
Definition at line 411 of file esp_scsi.h.
| #define ESP_RESELECT_TAG_LIMIT 2500 |
Definition at line 412 of file esp_scsi.h.
| #define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */ |
Definition at line 482 of file esp_scsi.h.
| #define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */ |
Definition at line 483 of file esp_scsi.h.
| #define ESP_SELECT_NONE 0x00 /* Not selecting */ |
Definition at line 481 of file esp_scsi.h.
| #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */ |
Definition at line 21 of file esp_scsi.h.
| #define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */ |
Definition at line 18 of file esp_scsi.h.
| #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */ |
Definition at line 161 of file esp_scsi.h.
| #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */ |
Definition at line 163 of file esp_scsi.h.
| #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */ |
Definition at line 165 of file esp_scsi.h.
| #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */ |
Definition at line 159 of file esp_scsi.h.
| #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */ |
Definition at line 164 of file esp_scsi.h.
| #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */ |
Definition at line 158 of file esp_scsi.h.
| #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */ |
Definition at line 162 of file esp_scsi.h.
| #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */ |
Definition at line 160 of file esp_scsi.h.
| #define ESP_STAT_INTR 0x80 /* Interrupt */ |
Definition at line 143 of file esp_scsi.h.
| #define ESP_STAT_PCD 0x02 /* CD phase bit */ |
Definition at line 133 of file esp_scsi.h.
| #define ESP_STAT_PERR 0x20 /* Parity error */ |
Definition at line 138 of file esp_scsi.h.
| #define ESP_STAT_PIO 0x01 /* IO phase bit */ |
Definition at line 132 of file esp_scsi.h.
| #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */ |
Definition at line 135 of file esp_scsi.h.
| #define ESP_STAT_PMSG 0x04 /* MSG phase bit */ |
Definition at line 134 of file esp_scsi.h.
| #define ESP_STAT_SPAM 0x40 /* Real bad error */ |
Definition at line 139 of file esp_scsi.h.
| #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */ |
Definition at line 137 of file esp_scsi.h.
| #define ESP_STAT_TDONE 0x08 /* Transfer Completed */ |
Definition at line 136 of file esp_scsi.h.
| #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */ |
Definition at line 153 of file esp_scsi.h.
| #define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */ |
Definition at line 14 of file esp_scsi.h.
Definition at line 24 of file esp_scsi.h.
| #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */ |
Definition at line 179 of file esp_scsi.h.
| #define ESP_STEP_FINI4 0x04 /* Command was sent ok */ |
Definition at line 183 of file esp_scsi.h.
| #define ESP_STEP_FINI5 0x05 |
Definition at line 186 of file esp_scsi.h.
| #define ESP_STEP_FINI6 0x06 |
Definition at line 187 of file esp_scsi.h.
| #define ESP_STEP_FINI7 0x07 |
Definition at line 188 of file esp_scsi.h.
| #define ESP_STEP_NCMD 0x02 /* Was not in command phase */ |
Definition at line 181 of file esp_scsi.h.
| #define ESP_STEP_PPC |
Definition at line 182 of file esp_scsi.h.
| #define ESP_STEP_SID 0x01 /* One msg byte sent */ |
Definition at line 180 of file esp_scsi.h.
| #define ESP_STEP_VBITS 0x07 /* Valid bits */ |
Definition at line 178 of file esp_scsi.h.
Definition at line 19 of file esp_scsi.h.
| #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */ |
Definition at line 28 of file esp_scsi.h.
| #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */ |
Definition at line 10 of file esp_scsi.h.
| #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */ |
Definition at line 11 of file esp_scsi.h.
| #define ESP_TEST_INI 0x02 /* Initiator test mode */ |
Definition at line 192 of file esp_scsi.h.
| #define ESP_TEST_TARG 0x01 /* Target test mode */ |
Definition at line 191 of file esp_scsi.h.
| #define ESP_TEST_TS 0x04 /* Tristate test mode */ |
Definition at line 193 of file esp_scsi.h.
| #define ESP_TGT_BROKEN 0x80 |
Definition at line 312 of file esp_scsi.h.
| #define ESP_TGT_CHECK_NEGO 0x40 |
Definition at line 311 of file esp_scsi.h.
| #define ESP_TGT_DISCONNECT 0x02 |
Definition at line 308 of file esp_scsi.h.
| #define ESP_TGT_NEGO_SYNC 0x08 |
Definition at line 310 of file esp_scsi.h.
| #define ESP_TGT_NEGO_WIDE 0x04 |
Definition at line 309 of file esp_scsi.h.
| #define ESP_TGT_WIDE 0x01 |
Definition at line 307 of file esp_scsi.h.
| #define ESP_TICK | ( | ccf, | |
| cycle | |||
| ) | ((7682 * (ccf) * (cycle) / 1000)) |
Definition at line 226 of file esp_scsi.h.
| #define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */ |
Definition at line 17 of file esp_scsi.h.
| #define ESP_TIMEO_CONST 8192 |
Definition at line 222 of file esp_scsi.h.
| #define ESP_UID_F100A 0x00 /* ESP FAS100A */ |
Definition at line 196 of file esp_scsi.h.
| #define ESP_UID_F236 0x02 /* ESP FAS236 */ |
Definition at line 197 of file esp_scsi.h.
| #define ESP_UID_FAM 0xf8 /* ESP family */ |
Definition at line 199 of file esp_scsi.h.
| #define ESP_UID_REV 0x07 /* ESP revision */ |
Definition at line 198 of file esp_scsi.h.
Definition at line 32 of file esp_scsi.h.
Definition at line 30 of file esp_scsi.h.
| #define SBUS_ESP_REG_SIZE 0x40UL |
Definition at line 34 of file esp_scsi.h.
| #define SYNC_DEFP_FAST 0x19 /* 10mb/s */ |
Definition at line 233 of file esp_scsi.h.
| #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */ |
Definition at line 232 of file esp_scsi.h.
| enum esp_rev |
Definition at line 247 of file esp_scsi.h.
| irqreturn_t scsi_esp_intr | ( | int | , |
| void * | |||
| ) |
Definition at line 2113 of file esp_scsi.c.
Definition at line 2313 of file esp_scsi.c.
Definition at line 2353 of file esp_scsi.c.
| struct scsi_host_template scsi_esp_template |
Definition at line 2613 of file esp_scsi.c.
1.8.2