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#define | FSL_DMA_MR_CS 0x00000001 |
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#define | FSL_DMA_MR_CC 0x00000002 |
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#define | FSL_DMA_MR_CA 0x00000008 |
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#define | FSL_DMA_MR_EIE 0x00000040 |
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#define | FSL_DMA_MR_XFE 0x00000020 |
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#define | FSL_DMA_MR_EOLNIE 0x00000100 |
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#define | FSL_DMA_MR_EOLSIE 0x00000080 |
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#define | FSL_DMA_MR_EOSIE 0x00000200 |
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#define | FSL_DMA_MR_CDSM 0x00000010 |
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#define | FSL_DMA_MR_CTM 0x00000004 |
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#define | FSL_DMA_MR_EMP_EN 0x00200000 |
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#define | FSL_DMA_MR_EMS_EN 0x00040000 |
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#define | FSL_DMA_MR_DAHE 0x00002000 |
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#define | FSL_DMA_MR_SAHE 0x00001000 |
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#define | FSL_DMA_MR_BWC 0x08000000 |
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#define | FSL_DMA_MR_EOTIE 0x00000080 |
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#define | FSL_DMA_MR_PRC_RM 0x00000800 |
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#define | FSL_DMA_SR_CH 0x00000020 |
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#define | FSL_DMA_SR_PE 0x00000010 |
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#define | FSL_DMA_SR_CB 0x00000004 |
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#define | FSL_DMA_SR_TE 0x00000080 |
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#define | FSL_DMA_SR_EOSI 0x00000002 |
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#define | FSL_DMA_SR_EOLSI 0x00000001 |
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#define | FSL_DMA_SR_EOCDI 0x00000001 |
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#define | FSL_DMA_SR_EOLNI 0x00000008 |
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#define | FSL_DMA_SATR_SBPATMU 0x20000000 |
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#define | FSL_DMA_SATR_STRANSINT_RIO 0x00c00000 |
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#define | FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000 |
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#define | FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000 |
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#define | FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000 |
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#define | FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000 |
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#define | FSL_DMA_DATR_DBPATMU 0x20000000 |
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#define | FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000 |
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#define | FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000 |
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#define | FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000 |
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#define | FSL_DMA_EOL ((u64)0x1) |
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#define | FSL_DMA_SNEN ((u64)0x10) |
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#define | FSL_DMA_EOSIE 0x8 |
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#define | FSL_DMA_NLDA_MASK (~(u64)0x1f) |
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#define | FSL_DMA_BCR_MAX_CNT 0x03ffffffu |
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#define | FSL_DMA_DGSR_TE 0x80 |
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#define | FSL_DMA_DGSR_CH 0x20 |
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#define | FSL_DMA_DGSR_PE 0x10 |
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#define | FSL_DMA_DGSR_EOLNI 0x08 |
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#define | FSL_DMA_DGSR_CB 0x04 |
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#define | FSL_DMA_DGSR_EOSI 0x02 |
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#define | FSL_DMA_DGSR_EOLSI 0x01 |
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#define | FSL_DMA_MAX_CHANS_PER_DEVICE 4 |
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#define | FSL_DMA_LITTLE_ENDIAN 0x00000000 |
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#define | FSL_DMA_BIG_ENDIAN 0x00000001 |
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#define | FSL_DMA_IP_MASK 0x00000ff0 |
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#define | FSL_DMA_IP_85XX 0x00000010 |
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#define | FSL_DMA_IP_83XX 0x00000020 |
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#define | FSL_DMA_CHAN_PAUSE_EXT 0x00001000 |
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#define | FSL_DMA_CHAN_START_EXT 0x00002000 |
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#define | to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common) |
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#define | to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) |
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#define | tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) |
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#define | DMA_IN(fsl_chan, addr, width) |
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#define | DMA_OUT(fsl_chan, addr, val, width) |
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#define | DMA_TO_CPU(fsl_chan, d, width) |
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#define | CPU_TO_DMA(fsl_chan, c, width) |
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