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gpio-msm-v1.c
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1 /*
2  * Copyright (C) 2007 Google, Inc.
3  * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
4  *
5  * This software is licensed under the terms of the GNU General Public
6  * License version 2, as published by the Free Software Foundation, and
7  * may be copied, distributed, and modified under those terms.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12  * GNU General Public License for more details.
13  *
14  */
15 
16 #include <linux/bitops.h>
17 #include <linux/gpio.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <mach/cpu.h>
23 #include <mach/msm_gpiomux.h>
24 #include <mach/msm_iomap.h>
25 
26 /* see 80-VA736-2 Rev C pp 695-751
27 **
28 ** These are actually the *shadow* gpio registers, since the
29 ** real ones (which allow full access) are only available to the
30 ** ARM9 side of the world.
31 **
32 ** Since the _BASE need to be page-aligned when we're mapping them
33 ** to virtual addresses, adjust for the additional offset in these
34 ** macros.
35 */
36 
37 #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
38 #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
39 #define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
40 #define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
41 
42 /*
43  * MSM7X00 registers
44  */
45 /* output value */
46 #define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
47 #define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
48 #define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
49 #define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
50 #define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
51 #define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
52 
53 /* same pin map as above, output enable */
54 #define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10)
55 #define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
56 #define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14)
57 #define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18)
58 #define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C)
59 #define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54)
60 
61 /* same pin map as above, input read */
62 #define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34)
63 #define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
64 #define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38)
65 #define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C)
66 #define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40)
67 #define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44)
68 
69 /* same pin map as above, 1=edge 0=level interrup */
70 #define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
71 #define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
72 #define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
73 #define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
74 #define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
75 #define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
76 
77 /* same pin map as above, 1=positive 0=negative */
78 #define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70)
79 #define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
80 #define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74)
81 #define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78)
82 #define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C)
83 #define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC)
84 
85 /* same pin map as above, interrupt enable */
86 #define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80)
87 #define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
88 #define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84)
89 #define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88)
90 #define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C)
91 #define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8)
92 
93 /* same pin map as above, write 1 to clear interrupt */
94 #define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90)
95 #define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
96 #define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94)
97 #define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98)
98 #define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C)
99 #define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4)
100 
101 /* same pin map as above, 1=interrupt pending */
102 #define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0)
103 #define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
104 #define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4)
105 #define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8)
106 #define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC)
107 #define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0)
108 
109 /*
110  * QSD8X50 registers
111  */
112 /* output value */
113 #define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
114 #define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
115 #define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
116 #define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
117 #define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */
118 #define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */
119 #define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */
120 #define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */
121 
122 /* same pin map as above, output enable */
123 #define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20)
124 #define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
125 #define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24)
126 #define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28)
127 #define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C)
128 #define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30)
129 #define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34)
130 #define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38)
131 
132 /* same pin map as above, input read */
133 #define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50)
134 #define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
135 #define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54)
136 #define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58)
137 #define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C)
138 #define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60)
139 #define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64)
140 #define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68)
141 
142 /* same pin map as above, 1=edge 0=level interrup */
143 #define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70)
144 #define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
145 #define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74)
146 #define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78)
147 #define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C)
148 #define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80)
149 #define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84)
150 #define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88)
151 
152 /* same pin map as above, 1=positive 0=negative */
153 #define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90)
154 #define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
155 #define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94)
156 #define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98)
157 #define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C)
158 #define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0)
159 #define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4)
160 #define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8)
161 
162 /* same pin map as above, interrupt enable */
163 #define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0)
164 #define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
165 #define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4)
166 #define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8)
167 #define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC)
168 #define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0)
169 #define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4)
170 #define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8)
171 
172 /* same pin map as above, write 1 to clear interrupt */
173 #define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0)
174 #define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
175 #define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4)
176 #define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8)
177 #define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC)
178 #define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0)
179 #define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4)
180 #define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8)
181 
182 /* same pin map as above, 1=interrupt pending */
183 #define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0)
184 #define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
185 #define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4)
186 #define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8)
187 #define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC)
188 #define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100)
189 #define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104)
190 #define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108)
191 
192 /*
193  * MSM7X30 registers
194  */
195 /* output value */
196 #define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
197 #define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
198 #define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
199 #define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
200 #define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
201 #define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
202 #define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
203 #define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
204 
205 /* same pin map as above, output enable */
206 #define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10)
207 #define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08)
208 #define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14)
209 #define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18)
210 #define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
211 #define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54)
212 #define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
213 #define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218)
214 
215 /* same pin map as above, input read */
216 #define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34)
217 #define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20)
218 #define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38)
219 #define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
220 #define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40)
221 #define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44)
222 #define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
223 #define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
224 
225 /* same pin map as above, 1=edge 0=level interrup */
226 #define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
227 #define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
228 #define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
229 #define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
230 #define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
231 #define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
232 #define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
233 #define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
234 
235 /* same pin map as above, 1=positive 0=negative */
236 #define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
237 #define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
238 #define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
239 #define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
240 #define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
241 #define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
242 #define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
243 #define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
244 
245 /* same pin map as above, interrupt enable */
246 #define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
247 #define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
248 #define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
249 #define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
250 #define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
251 #define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
252 #define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
253 #define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
254 
255 /* same pin map as above, write 1 to clear interrupt */
256 #define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
257 #define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
258 #define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
259 #define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
260 #define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
261 #define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
262 #define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
263 #define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
264 
265 /* same pin map as above, 1=interrupt pending */
266 #define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
267 #define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
268 #define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
269 #define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
270 #define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
271 #define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
272 #define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
273 #define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
274 
275 #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
276 
277 #define MSM_GPIO_BANK(soc, bank, first, last) \
278  { \
279  .regs = { \
280  .out = soc##_GPIO_OUT_##bank, \
281  .in = soc##_GPIO_IN_##bank, \
282  .int_status = soc##_GPIO_INT_STATUS_##bank, \
283  .int_clear = soc##_GPIO_INT_CLEAR_##bank, \
284  .int_en = soc##_GPIO_INT_EN_##bank, \
285  .int_edge = soc##_GPIO_INT_EDGE_##bank, \
286  .int_pos = soc##_GPIO_INT_POS_##bank, \
287  .oe = soc##_GPIO_OE_##bank, \
288  }, \
289  .chip = { \
290  .base = (first), \
291  .ngpio = (last) - (first) + 1, \
292  .get = msm_gpio_get, \
293  .set = msm_gpio_set, \
294  .direction_input = msm_gpio_direction_input, \
295  .direction_output = msm_gpio_direction_output, \
296  .to_irq = msm_gpio_to_irq, \
297  .request = msm_gpio_request, \
298  .free = msm_gpio_free, \
299  } \
300  }
301 
302 #define MSM_GPIO_BROKEN_INT_CLEAR 1
303 
304 struct msm_gpio_regs {
305  void __iomem *out;
306  void __iomem *in;
307  void __iomem *int_status;
308  void __iomem *int_clear;
309  void __iomem *int_en;
310  void __iomem *int_edge;
311  void __iomem *int_pos;
312  void __iomem *oe;
313 };
314 
315 struct msm_gpio_chip {
316  spinlock_t lock;
317  struct gpio_chip chip;
318  struct msm_gpio_regs regs;
319 #if MSM_GPIO_BROKEN_INT_CLEAR
320  unsigned int_status_copy;
321 #endif
322  unsigned int both_edge_detect;
323  unsigned int int_enable[2]; /* 0: awake, 1: sleep */
324 };
325 
326 static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
327  unsigned offset, unsigned on)
328 {
329  unsigned mask = BIT(offset);
330  unsigned val;
331 
332  val = readl(msm_chip->regs.out);
333  if (on)
334  writel(val | mask, msm_chip->regs.out);
335  else
336  writel(val & ~mask, msm_chip->regs.out);
337  return 0;
338 }
339 
340 static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
341 {
342  int loop_limit = 100;
343  unsigned pol, val, val2, intstat;
344  do {
345  val = readl(msm_chip->regs.in);
346  pol = readl(msm_chip->regs.int_pos);
347  pol = (pol & ~msm_chip->both_edge_detect) |
348  (~val & msm_chip->both_edge_detect);
349  writel(pol, msm_chip->regs.int_pos);
350  intstat = readl(msm_chip->regs.int_status);
351  val2 = readl(msm_chip->regs.in);
352  if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
353  return;
354  } while (loop_limit-- > 0);
355  printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
356  "failed to reach stable state %x != %x\n", val, val2);
357 }
358 
359 static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
360  unsigned offset)
361 {
362  unsigned bit = BIT(offset);
363 
364 #if MSM_GPIO_BROKEN_INT_CLEAR
365  /* Save interrupts that already triggered before we loose them. */
366  /* Any interrupt that triggers between the read of int_status */
367  /* and the write to int_clear will still be lost though. */
368  msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
369  msm_chip->int_status_copy &= ~bit;
370 #endif
371  writel(bit, msm_chip->regs.int_clear);
372  msm_gpio_update_both_edge_detect(msm_chip);
373  return 0;
374 }
375 
376 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
377 {
378  struct msm_gpio_chip *msm_chip;
379  unsigned long irq_flags;
380 
381  msm_chip = container_of(chip, struct msm_gpio_chip, chip);
382  spin_lock_irqsave(&msm_chip->lock, irq_flags);
383  writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
384  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
385  return 0;
386 }
387 
388 static int
389 msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
390 {
391  struct msm_gpio_chip *msm_chip;
392  unsigned long irq_flags;
393 
394  msm_chip = container_of(chip, struct msm_gpio_chip, chip);
395  spin_lock_irqsave(&msm_chip->lock, irq_flags);
396  msm_gpio_write(msm_chip, offset, value);
397  writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
398  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
399  return 0;
400 }
401 
402 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
403 {
404  struct msm_gpio_chip *msm_chip;
405 
406  msm_chip = container_of(chip, struct msm_gpio_chip, chip);
407  return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
408 }
409 
410 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
411 {
412  struct msm_gpio_chip *msm_chip;
413  unsigned long irq_flags;
414 
415  msm_chip = container_of(chip, struct msm_gpio_chip, chip);
416  spin_lock_irqsave(&msm_chip->lock, irq_flags);
417  msm_gpio_write(msm_chip, offset, value);
418  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
419 }
420 
421 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
422 {
423  return MSM_GPIO_TO_INT(chip->base + offset);
424 }
425 
426 #ifdef CONFIG_MSM_GPIOMUX
427 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
428 {
429  return msm_gpiomux_get(chip->base + offset);
430 }
431 
432 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
433 {
434  msm_gpiomux_put(chip->base + offset);
435 }
436 #else
437 #define msm_gpio_request NULL
438 #define msm_gpio_free NULL
439 #endif
440 
441 static struct msm_gpio_chip *msm_gpio_chips;
442 static int msm_gpio_count;
443 
444 static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
445  MSM_GPIO_BANK(MSM7X00, 0, 0, 15),
446  MSM_GPIO_BANK(MSM7X00, 1, 16, 42),
447  MSM_GPIO_BANK(MSM7X00, 2, 43, 67),
448  MSM_GPIO_BANK(MSM7X00, 3, 68, 94),
449  MSM_GPIO_BANK(MSM7X00, 4, 95, 106),
450  MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
451 };
452 
453 static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
454  MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
455  MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
456  MSM_GPIO_BANK(MSM7X30, 2, 44, 67),
457  MSM_GPIO_BANK(MSM7X30, 3, 68, 94),
458  MSM_GPIO_BANK(MSM7X30, 4, 95, 106),
459  MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
460  MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
461  MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
462 };
463 
464 static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
465  MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
466  MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
467  MSM_GPIO_BANK(QSD8X50, 2, 43, 67),
468  MSM_GPIO_BANK(QSD8X50, 3, 68, 94),
469  MSM_GPIO_BANK(QSD8X50, 4, 95, 103),
470  MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
471  MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
472  MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
473 };
474 
475 static void msm_gpio_irq_ack(struct irq_data *d)
476 {
477  unsigned long irq_flags;
478  struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
479  spin_lock_irqsave(&msm_chip->lock, irq_flags);
480  msm_gpio_clear_detect_status(msm_chip,
481  d->irq - gpio_to_irq(msm_chip->chip.base));
482  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
483 }
484 
485 static void msm_gpio_irq_mask(struct irq_data *d)
486 {
487  unsigned long irq_flags;
488  struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
489  unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
490 
491  spin_lock_irqsave(&msm_chip->lock, irq_flags);
492  /* level triggered interrupts are also latched */
493  if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
494  msm_gpio_clear_detect_status(msm_chip, offset);
495  msm_chip->int_enable[0] &= ~BIT(offset);
496  writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
497  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
498 }
499 
500 static void msm_gpio_irq_unmask(struct irq_data *d)
501 {
502  unsigned long irq_flags;
503  struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
504  unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
505 
506  spin_lock_irqsave(&msm_chip->lock, irq_flags);
507  /* level triggered interrupts are also latched */
508  if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
509  msm_gpio_clear_detect_status(msm_chip, offset);
510  msm_chip->int_enable[0] |= BIT(offset);
511  writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
512  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
513 }
514 
515 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
516 {
517  unsigned long irq_flags;
518  struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
519  unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
520 
521  spin_lock_irqsave(&msm_chip->lock, irq_flags);
522 
523  if (on)
524  msm_chip->int_enable[1] |= BIT(offset);
525  else
526  msm_chip->int_enable[1] &= ~BIT(offset);
527 
528  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
529  return 0;
530 }
531 
532 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
533 {
534  unsigned long irq_flags;
535  struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
536  unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
537  unsigned val, mask = BIT(offset);
538 
539  spin_lock_irqsave(&msm_chip->lock, irq_flags);
540  val = readl(msm_chip->regs.int_edge);
541  if (flow_type & IRQ_TYPE_EDGE_BOTH) {
542  writel(val | mask, msm_chip->regs.int_edge);
543  __irq_set_handler_locked(d->irq, handle_edge_irq);
544  } else {
545  writel(val & ~mask, msm_chip->regs.int_edge);
546  __irq_set_handler_locked(d->irq, handle_level_irq);
547  }
548  if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
549  msm_chip->both_edge_detect |= mask;
550  msm_gpio_update_both_edge_detect(msm_chip);
551  } else {
552  msm_chip->both_edge_detect &= ~mask;
553  val = readl(msm_chip->regs.int_pos);
554  if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
555  writel(val | mask, msm_chip->regs.int_pos);
556  else
557  writel(val & ~mask, msm_chip->regs.int_pos);
558  }
559  spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
560  return 0;
561 }
562 
563 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
564 {
565  int i, j, mask;
566  unsigned val;
567 
568  for (i = 0; i < msm_gpio_count; i++) {
569  struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
570  val = readl(msm_chip->regs.int_status);
571  val &= msm_chip->int_enable[0];
572  while (val) {
573  mask = val & -val;
574  j = fls(mask) - 1;
575  /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
576  __func__, v, m, j, msm_chip->chip.start + j,
577  FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
578  val &= ~mask;
579  generic_handle_irq(FIRST_GPIO_IRQ +
580  msm_chip->chip.base + j);
581  }
582  }
583  desc->irq_data.chip->irq_ack(&desc->irq_data);
584 }
585 
586 static struct irq_chip msm_gpio_irq_chip = {
587  .name = "msmgpio",
588  .irq_ack = msm_gpio_irq_ack,
589  .irq_mask = msm_gpio_irq_mask,
590  .irq_unmask = msm_gpio_irq_unmask,
591  .irq_set_wake = msm_gpio_irq_set_wake,
592  .irq_set_type = msm_gpio_irq_set_type,
593 };
594 
595 static int __init msm_init_gpio(void)
596 {
597  int i, j = 0;
598 
599  if (cpu_is_msm7x01()) {
600  msm_gpio_chips = msm_gpio_chips_msm7x01;
601  msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01);
602  } else if (cpu_is_msm7x30()) {
603  msm_gpio_chips = msm_gpio_chips_msm7x30;
604  msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30);
605  } else if (cpu_is_qsd8x50()) {
606  msm_gpio_chips = msm_gpio_chips_qsd8x50;
607  msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50);
608  } else {
609  return 0;
610  }
611 
612  for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
613  if (i - FIRST_GPIO_IRQ >=
614  msm_gpio_chips[j].chip.base +
615  msm_gpio_chips[j].chip.ngpio)
616  j++;
617  irq_set_chip_data(i, &msm_gpio_chips[j]);
618  irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
619  handle_edge_irq);
620  set_irq_flags(i, IRQF_VALID);
621  }
622 
623  for (i = 0; i < msm_gpio_count; i++) {
624  spin_lock_init(&msm_gpio_chips[i].lock);
625  writel(0, msm_gpio_chips[i].regs.int_en);
626  gpiochip_add(&msm_gpio_chips[i].chip);
627  }
628 
629  irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
630  irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
631  irq_set_irq_wake(INT_GPIO_GROUP1, 1);
632  irq_set_irq_wake(INT_GPIO_GROUP2, 2);
633  return 0;
634 }
635 
636 postcore_initcall(msm_init_gpio);
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