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#define | HDSPM_WR_SETTINGS 0 |
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#define | HDSPM_outputBufferAddress 32 |
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#define | HDSPM_inputBufferAddress 36 |
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#define | HDSPM_controlRegister 64 |
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#define | HDSPM_interruptConfirmation 96 |
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#define | HDSPM_control2Reg 256 /* not in specs ???????? */ |
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#define | HDSPM_freqReg 256 /* for AES32 */ |
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#define | HDSPM_midiDataOut0 352 /* just believe in old code */ |
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#define | HDSPM_midiDataOut1 356 |
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#define | HDSPM_eeprom_wr 384 /* for AES32 */ |
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#define | HDSPM_outputEnableBase 512 /* 512-767 input DMA */ |
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#define | HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ |
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#define | HDSPM_pageAddressBufferOut 8192 |
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#define | HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) |
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#define | HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ |
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#define | HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ |
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#define | HDSPM_statusRegister 0 |
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#define | HDSPM_statusRegister2 192 |
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#define | HDSPM_timecodeRegister 128 |
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#define | HDSPM_RD_STATUS_0 0 |
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#define | HDSPM_RD_STATUS_1 64 |
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#define | HDSPM_RD_STATUS_2 128 |
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#define | HDSPM_RD_STATUS_3 192 |
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#define | HDSPM_RD_TCO 256 |
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#define | HDSPM_RD_PLL_FREQ 512 |
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#define | HDSPM_WR_TCO 128 |
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#define | HDSPM_TCO1_TCO_lock 0x00000001 |
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#define | HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 |
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#define | HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 |
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#define | HDSPM_TCO1_LTC_Input_valid 0x00000008 |
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#define | HDSPM_TCO1_WCK_Input_valid 0x00000010 |
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#define | HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 |
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#define | HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 |
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#define | HDSPM_TCO1_set_TC 0x00000100 |
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#define | HDSPM_TCO1_set_drop_frame_flag 0x00000200 |
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#define | HDSPM_TCO1_LTC_Format_LSB 0x00000400 |
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#define | HDSPM_TCO1_LTC_Format_MSB 0x00000800 |
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#define | HDSPM_TCO2_TC_run 0x00010000 |
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#define | HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 |
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#define | HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 |
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#define | HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 |
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#define | HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 |
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#define | HDSPM_TCO2_set_jam_sync 0x00200000 |
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#define | HDSPM_TCO2_set_flywheel 0x00400000 |
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#define | HDSPM_TCO2_set_01_4 0x01000000 |
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#define | HDSPM_TCO2_set_pull_down 0x02000000 |
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#define | HDSPM_TCO2_set_pull_up 0x04000000 |
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#define | HDSPM_TCO2_set_freq 0x08000000 |
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#define | HDSPM_TCO2_set_term_75R 0x10000000 |
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#define | HDSPM_TCO2_set_input_LSB 0x20000000 |
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#define | HDSPM_TCO2_set_input_MSB 0x40000000 |
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#define | HDSPM_TCO2_set_freq_from_app 0x80000000 |
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#define | HDSPM_midiDataOut0 352 |
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#define | HDSPM_midiDataOut1 356 |
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#define | HDSPM_midiDataOut2 368 |
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#define | HDSPM_midiDataIn0 360 |
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#define | HDSPM_midiDataIn1 364 |
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#define | HDSPM_midiDataIn2 372 |
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#define | HDSPM_midiDataIn3 376 |
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#define | HDSPM_midiStatusOut0 384 |
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#define | HDSPM_midiStatusOut1 388 |
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#define | HDSPM_midiStatusOut2 400 |
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#define | HDSPM_midiStatusIn0 392 |
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#define | HDSPM_midiStatusIn1 396 |
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#define | HDSPM_midiStatusIn2 404 |
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#define | HDSPM_midiStatusIn3 408 |
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#define | HDSPM_MADI_INPUT_PEAK 4096 |
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#define | HDSPM_MADI_PLAYBACK_PEAK 4352 |
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#define | HDSPM_MADI_OUTPUT_PEAK 4608 |
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#define | HDSPM_MADI_INPUT_RMS_L 6144 |
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#define | HDSPM_MADI_PLAYBACK_RMS_L 6400 |
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#define | HDSPM_MADI_OUTPUT_RMS_L 6656 |
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#define | HDSPM_MADI_INPUT_RMS_H 7168 |
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#define | HDSPM_MADI_PLAYBACK_RMS_H 7424 |
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#define | HDSPM_MADI_OUTPUT_RMS_H 7680 |
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#define | HDSPM_Start (1<<0) /* start engine */ |
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#define | HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ |
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#define | HDSPM_Latency1 (1<<2) /* where n is defined */ |
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#define | HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ |
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#define | HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ |
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#define | HDSPM_c0Master |
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#define | HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ |
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#define | HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ |
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#define | HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ |
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#define | HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ |
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#define | HDSPM_QuadSpeed (1<<31) /* quad speed bit */ |
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#define | HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ |
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#define | HDSPM_TX_64ch |
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#define | HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ |
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#define | HDSPM_AutoInp |
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#define | HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ |
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#define | HDSPM_InputSelect0 |
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#define | HDSPM_InputSelect1 (1<<15) /* should be 0 */ |
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#define | HDSPM_SyncRef2 (1<<13) |
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#define | HDSPM_SyncRef3 (1<<25) |
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#define | HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ |
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#define | HDSPM_clr_tms |
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#define | HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ |
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#define | HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ |
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#define | HDSPM_Midi0InterruptEnable 0x0400000 |
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#define | HDSPM_Midi1InterruptEnable 0x0800000 |
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#define | HDSPM_Midi2InterruptEnable 0x0200000 |
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#define | HDSPM_Midi3InterruptEnable 0x4000000 |
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#define | HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ |
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#define | HDSPe_FLOAT_FORMAT 0x2000000 |
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#define | HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ |
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#define | HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ |
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#define | HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ |
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#define | HDSPM_wclk_sel (1<<30) |
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#define | HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) |
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#define | HDSPM_FrequencyMask |
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#define | HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) |
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#define | HDSPM_InputOptical 0 |
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#define | HDSPM_InputCoaxial (HDSPM_InputSelect0) |
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#define | HDSPM_SyncRefMask |
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#define | HDSPM_c0_SyncRef0 0x2 |
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#define | HDSPM_c0_SyncRef1 0x4 |
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#define | HDSPM_c0_SyncRef2 0x8 |
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#define | HDSPM_c0_SyncRef3 0x10 |
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#define | HDSPM_c0_SyncRefMask |
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#define | HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ |
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#define | HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ |
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#define | HDSPM_SYNC_FROM_TCO 2 |
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#define | HDSPM_SYNC_FROM_SYNC_IN 3 |
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#define | HDSPM_Frequency32KHz HDSPM_Frequency0 |
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#define | HDSPM_Frequency44_1KHz HDSPM_Frequency1 |
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#define | HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) |
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#define | HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) |
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#define | HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) |
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#define | HDSPM_Frequency96KHz |
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#define | HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) |
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#define | HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) |
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#define | HDSPM_Frequency192KHz |
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#define | HDSPM_SYNC_CHECK_NO_LOCK 0 |
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#define | HDSPM_SYNC_CHECK_LOCK 1 |
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#define | HDSPM_SYNC_CHECK_SYNC 2 |
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#define | HDSPM_AUTOSYNC_FROM_WORD 0 |
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#define | HDSPM_AUTOSYNC_FROM_MADI 1 |
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#define | HDSPM_AUTOSYNC_FROM_TCO 2 |
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#define | HDSPM_AUTOSYNC_FROM_SYNC_IN 3 |
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#define | HDSPM_AUTOSYNC_FROM_NONE 4 |
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#define | HDSPM_OPTICAL 0 /* optical */ |
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#define | HDSPM_COAXIAL 1 /* BNC */ |
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#define | hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) |
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#define | hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) |
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#define | hdspm_encode_in(x) (((x)&0x3)<<14) |
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#define | hdspm_decode_in(x) (((x)>>14)&0x3) |
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#define | HDSPM_TMS (1<<0) |
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#define | HDSPM_TCK (1<<1) |
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#define | HDSPM_TDI (1<<2) |
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#define | HDSPM_JTAG (1<<3) |
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#define | HDSPM_PWDN (1<<4) |
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#define | HDSPM_PROGRAM (1<<5) |
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#define | HDSPM_CONFIG_MODE_0 (1<<6) |
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#define | HDSPM_CONFIG_MODE_1 (1<<7) |
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#define | HDSPM_BIGENDIAN_MODE (1<<9) |
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#define | HDSPM_RD_MULTIPLE (1<<10) |
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#define | HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ |
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#define | HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ |
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#define | HDSPM_AB_int |
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#define | HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ |
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#define | HDSPM_madiSync (1<<18) /* MADI is in sync */ |
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#define | HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ |
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#define | HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ |
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#define | HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ |
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#define | HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ |
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#define | HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ |
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#define | HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ |
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#define | HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ |
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#define | HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ |
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#define | HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ |
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#define | HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ |
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#define | HDSPM_BufferID |
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#define | HDSPM_tco_detect 0x08000000 |
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#define | HDSPM_tco_lock 0x20000000 |
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#define | HDSPM_s2_tco_detect 0x00000040 |
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#define | HDSPM_s2_AEBO_D 0x00000080 |
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#define | HDSPM_s2_AEBI_D 0x00000100 |
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#define | HDSPM_midi0IRQPending 0x40000000 |
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#define | HDSPM_midi1IRQPending 0x80000000 |
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#define | HDSPM_midi2IRQPending 0x20000000 |
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#define | HDSPM_midi2IRQPendingAES 0x00000020 |
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#define | HDSPM_midi3IRQPending 0x00200000 |
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#define | HDSPM_madiFreqMask |
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#define | HDSPM_madiFreq32 (HDSPM_madiFreq0) |
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#define | HDSPM_madiFreq44_1 (HDSPM_madiFreq1) |
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#define | HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) |
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#define | HDSPM_madiFreq64 (HDSPM_madiFreq2) |
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#define | HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) |
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#define | HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) |
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#define | HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) |
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#define | HDSPM_madiFreq176_4 (HDSPM_madiFreq3) |
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#define | HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) |
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#define | HDSPM_version0 (1<<0) /* not really defined but I guess */ |
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#define | HDSPM_version1 (1<<1) /* in former cards it was ??? */ |
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#define | HDSPM_version2 (1<<2) |
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#define | HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ |
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#define | HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ |
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#define | HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ |
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#define | HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ |
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#define | HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ |
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#define | HDSPM_SyncRef0 0x10000 /* Sync Reference */ |
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#define | HDSPM_SyncRef1 0x20000 |
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#define | HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ |
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#define | HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ |
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#define | HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ |
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#define | HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) |
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#define | HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) |
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#define | HDSPM_wcFreq32 (HDSPM_wc_freq0) |
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#define | HDSPM_wcFreq44_1 (HDSPM_wc_freq1) |
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#define | HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) |
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#define | HDSPM_wcFreq64 (HDSPM_wc_freq2) |
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#define | HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) |
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#define | HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) |
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#define | HDSPM_status1_F_0 0x0400000 |
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#define | HDSPM_status1_F_1 0x0800000 |
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#define | HDSPM_status1_F_2 0x1000000 |
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#define | HDSPM_status1_F_3 0x2000000 |
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#define | HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) |
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#define | HDSPM_SelSyncRefMask |
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#define | HDSPM_SelSyncRef_WORD 0 |
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#define | HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) |
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#define | HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) |
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#define | HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) |
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#define | HDSPM_SelSyncRef_NVALID |
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#define | HDSPM_AES32_wcLock 0x0200000 |
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#define | HDSPM_AES32_wcFreq_bit 22 |
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#define | HDSPM_AES32_syncref_bit 16 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_WORD 0 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES1 1 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES2 2 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES3 3 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES4 4 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES5 5 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES6 6 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES7 7 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_AES8 8 |
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#define | HDSPM_AES32_AUTOSYNC_FROM_NONE 9 |
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#define | HDSPM_LockAES 0x80 |
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#define | HDSPM_LockAES1 0x80 |
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#define | HDSPM_LockAES2 0x40 |
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#define | HDSPM_LockAES3 0x20 |
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#define | HDSPM_LockAES4 0x10 |
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#define | HDSPM_LockAES5 0x8 |
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#define | HDSPM_LockAES6 0x4 |
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#define | HDSPM_LockAES7 0x2 |
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#define | HDSPM_LockAES8 0x1 |
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#define | UNITY_GAIN 32768 /* = 65536/2 */ |
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#define | MINUS_INFINITY_GAIN 0 |
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#define | MADI_SS_CHANNELS 64 |
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#define | MADI_DS_CHANNELS 32 |
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#define | MADI_QS_CHANNELS 16 |
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#define | RAYDAT_SS_CHANNELS 36 |
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#define | RAYDAT_DS_CHANNELS 20 |
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#define | RAYDAT_QS_CHANNELS 12 |
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#define | AIO_IN_SS_CHANNELS 14 |
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#define | AIO_IN_DS_CHANNELS 10 |
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#define | AIO_IN_QS_CHANNELS 8 |
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#define | AIO_OUT_SS_CHANNELS 16 |
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#define | AIO_OUT_DS_CHANNELS 12 |
|
#define | AIO_OUT_QS_CHANNELS 10 |
|
#define | AES32_CHANNELS 16 |
|
#define | HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) |
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#define | HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) |
|
#define | HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) |
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#define | HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) |
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#define | HDSPM_RAYDAT_REV 211 |
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#define | HDSPM_AIO_REV 212 |
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#define | HDSPM_MADIFACE_REV 213 |
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#define | HDSPM_SPEED_SINGLE 0 |
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#define | HDSPM_SPEED_DOUBLE 1 |
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#define | HDSPM_SPEED_QUAD 2 |
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#define | HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) |
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#define | HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) |
|
#define | HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) |
|
#define | HDSPM_INTERNAL_CLOCK(xname, xindex) |
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#define | HDSPM_PREF_SYNC_REF(xname, xindex) |
|
#define | HDSPM_AUTOSYNC_REF(xname, xindex) |
|
#define | HDSPM_LINE_OUT(xname, xindex) |
|
#define | snd_hdspm_info_line_out snd_ctl_boolean_mono_info |
|
#define | HDSPM_TX_64(xname, xindex) |
|
#define | snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info |
|
#define | HDSPM_C_TMS(xname, xindex) |
|
#define | snd_hdspm_info_c_tms snd_ctl_boolean_mono_info |
|
#define | HDSPM_SAFE_MODE(xname, xindex) |
|
#define | snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info |
|
#define | HDSPM_EMPHASIS(xname, xindex) |
|
#define | snd_hdspm_info_emphasis snd_ctl_boolean_mono_info |
|
#define | HDSPM_DOLBY(xname, xindex) |
|
#define | snd_hdspm_info_dolby snd_ctl_boolean_mono_info |
|
#define | HDSPM_PROFESSIONAL(xname, xindex) |
|
#define | snd_hdspm_info_professional snd_ctl_boolean_mono_info |
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#define | HDSPM_INPUT_SELECT(xname, xindex) |
|
#define | HDSPM_DS_WIRE(xname, xindex) |
|
#define | HDSPM_QS_WIRE(xname, xindex) |
|
#define | HDSPM_MADI_SPEEDMODE(xname, xindex) |
|
#define | HDSPM_MIXER(xname, xindex) |
|
#define | HDSPM_PLAYBACK_MIXER |
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#define | HDSPM_SYNC_CHECK(xname, xindex) |
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#define | HDSPM_TCO_SAMPLE_RATE(xname, xindex) |
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#define | HDSPM_TCO_PULL(xname, xindex) |
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#define | HDSPM_TCO_WCK_CONVERSION(xname, xindex) |
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#define | HDSPM_TCO_FRAME_RATE(xname, xindex) |
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#define | HDSPM_TCO_SYNC_SOURCE(xname, xindex) |
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#define | HDSPM_TCO_WORD_TERM(xname, xindex) |
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