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| #define | hprintk(fmt, args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args) |
| |
| #define | HPRINTK(fmt, args...) do { } while (0) |
| |
| #define | he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0) |
| |
| #define | he_readl(dev, reg) readl((dev)->membase + (reg)) |
| |
| #define | he_writel_rcm(dev, val, reg) he_writel_internal(dev, val, reg, CON_CTL_RCM) |
| |
| #define | he_writel_tcm(dev, val, reg) he_writel_internal(dev, val, reg, CON_CTL_TCM) |
| |
| #define | he_writel_mbox(dev, val, reg) he_writel_internal(dev, val, reg, CON_CTL_MBOX) |
| |
| #define | he_readl_rcm(dev, reg) he_readl_internal(dev, reg, CON_CTL_RCM) |
| |
| #define | he_readl_tcm(dev, reg) he_readl_internal(dev, reg, CON_CTL_TCM) |
| |
| #define | he_readl_mbox(dev, reg) he_readl_internal(dev, reg, CON_CTL_MBOX) |
| |
| #define | he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff) |
| |
| #define | he_writel_tsr0(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0) |
| |
| #define | he_readl_tsr0(dev, cid) he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0) |
| |
| #define | he_writel_tsr1(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1) |
| |
| #define | he_writel_tsr2(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2) |
| |
| #define | he_writel_tsr3(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3) |
| |
| #define | he_writel_tsr4(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4) |
| |
| #define | he_writel_tsr4_upper(dev, val, cid) |
| |
| #define | he_readl_tsr4(dev, cid) he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4) |
| |
| #define | he_writel_tsr5(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5) |
| |
| #define | he_writel_tsr6(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6) |
| |
| #define | he_writel_tsr7(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7) |
| |
| #define | he_writel_tsr8(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0) |
| |
| #define | he_writel_tsr9(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1) |
| |
| #define | he_writel_tsr10(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2) |
| |
| #define | he_writel_tsr11(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3) |
| |
| #define | he_writel_tsr12(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0) |
| |
| #define | he_writel_tsr13(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1) |
| |
| #define | he_writel_tsr14(dev, val, cid) he_writel_tcm(dev, val, CONFIG_TSRD | cid) |
| |
| #define | he_writel_tsr14_upper(dev, val, cid) |
| |
| #define | he_writel_rsr0(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0) |
| |
| #define | he_readl_rsr0(dev, cid) he_readl_rcm(dev, 0x00000 | (cid << 3) | 0) |
| |
| #define | he_writel_rsr1(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1) |
| |
| #define | he_writel_rsr2(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2) |
| |
| #define | he_writel_rsr3(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3) |
| |
| #define | he_writel_rsr4(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4) |
| |
| #define | he_writel_rsr5(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5) |
| |
| #define | he_writel_rsr6(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6) |
| |
| #define | he_writel_rsr7(dev, val, cid) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7) |
| |
| #define | NONZERO (1 << 14) |
| |
| #define | RTGTBL_OFFSET 0x400 |
| |
| #define | LAT_TIMER 209 |
| |
| #define | AAL5_LEN(buf, len) |
| |
| #define | TCP_CKSUM(buf, len) |
| |
| #define | MAX_RETRY 30 |
| |
| #define | HE_TPD_BUFSIZE 0xffff |
| |
|
| | MODULE_LICENSE ("GPL") |
| |
| | MODULE_AUTHOR ("chas williams <[email protected]>") |
| |
| | MODULE_DESCRIPTION ("ForeRunnerHE ATM Adapter driver") |
| |
| | module_param (disable64, bool, 0) |
| |
| | MODULE_PARM_DESC (disable64,"disable 64-bit pci bus transfers") |
| |
| | module_param (nvpibits, short, 0) |
| |
| | MODULE_PARM_DESC (nvpibits,"numbers of bits for vpi (default 0)") |
| |
| | module_param (nvcibits, short, 0) |
| |
| | MODULE_PARM_DESC (nvcibits,"numbers of bits for vci (default 12)") |
| |
| | module_param (rx_skb_reserve, short, 0) |
| |
| | MODULE_PARM_DESC (rx_skb_reserve,"padding for receive skb (default 16)") |
| |
| | module_param (irq_coalesce, bool, 0) |
| |
| | MODULE_PARM_DESC (irq_coalesce,"use interrupt coalescing (default 1)") |
| |
| | module_param (sdh, bool, 0) |
| |
| | MODULE_PARM_DESC (sdh,"use SDH framing (default 0)") |
| |
| | MODULE_DEVICE_TABLE (pci, he_pci_tbl) |
| |
| | module_init (he_init) |
| |
| | module_exit (he_cleanup) |
| |