14 #define DRV_MODULE_NAME "hlwd-pic"
15 #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
17 #include <linux/kernel.h>
25 #define HLWD_NR_IRQS 32
35 #define HW_BROADWAY_ICR 0x00
36 #define HW_BROADWAY_IMR 0x04
44 static void hlwd_pic_mask_and_ack(
struct irq_data *
d)
46 int irq = irqd_to_hwirq(d);
54 static void hlwd_pic_ack(
struct irq_data *
d)
56 int irq = irqd_to_hwirq(d);
62 static void hlwd_pic_mask(
struct irq_data *
d)
64 int irq = irqd_to_hwirq(d);
70 static void hlwd_pic_unmask(
struct irq_data *
d)
72 int irq = irqd_to_hwirq(d);
81 .irq_ack = hlwd_pic_ack,
82 .irq_mask_ack = hlwd_pic_mask_and_ack,
83 .irq_mask = hlwd_pic_mask,
84 .irq_unmask = hlwd_pic_unmask,
94 static int hlwd_pic_map(
struct irq_domain *
h,
unsigned int virq,
107 static unsigned int __hlwd_pic_get_irq(
struct irq_domain *
h)
118 irq =
__ffs(irq_status);
122 static void hlwd_pic_irq_cascade(
unsigned int cascade_virq,
133 virq = __hlwd_pic_get_irq(irq_domain);
137 pr_err(
"spurious interrupt!\n");
151 static void __hlwd_quiesce(
void __iomem *io_base)
160 struct irq_domain *irq_domain;
167 pr_err(
"no io memory range found\n");
172 pr_err(
"ioremap failed\n");
176 pr_info(
"controller at 0x%08x mapped to 0x%p\n", res.
start, io_base);
178 __hlwd_quiesce(io_base);
181 &hlwd_irq_domain_ops, io_base);
183 pr_err(
"failed to allocate irq_domain\n");
192 return __hlwd_pic_get_irq(hlwd_irq_host);
202 struct irq_domain *
host;
204 const u32 *interrupts;
207 for_each_compatible_node(np,
NULL,
"nintendo,hollywood-pic") {
214 irq_set_chained_handler(cascade_virq,
215 hlwd_pic_irq_cascade);
216 hlwd_irq_host = host;
232 __hlwd_quiesce(io_base);