Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
i2c-bfin-twi.c
Go to the documentation of this file.
1 /*
2  * Blackfin On-Chip Two Wire Interface Driver
3  *
4  * Copyright 2005-2007 Analog Devices Inc.
5  *
6  * Enter bugs at http://blackfin.uclinux.org/
7  *
8  * Licensed under the GPL-2 or later.
9  */
10 
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/mm.h>
18 #include <linux/timer.h>
19 #include <linux/spinlock.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 
25 #include <asm/blackfin.h>
26 #include <asm/portmux.h>
27 #include <asm/irq.h>
28 #include <asm/bfin_twi.h>
29 
30 /* SMBus mode*/
31 #define TWI_I2C_MODE_STANDARD 1
32 #define TWI_I2C_MODE_STANDARDSUB 2
33 #define TWI_I2C_MODE_COMBINED 3
34 #define TWI_I2C_MODE_REPEAT 4
35 
36 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
37  unsigned short twi_int_status)
38 {
39  unsigned short mast_stat = read_MASTER_STAT(iface);
40 
41  if (twi_int_status & XMTSERV) {
42  /* Transmit next data */
43  if (iface->writeNum > 0) {
44  SSYNC();
45  write_XMT_DATA8(iface, *(iface->transPtr++));
46  iface->writeNum--;
47  }
48  /* start receive immediately after complete sending in
49  * combine mode.
50  */
51  else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
52  write_MASTER_CTL(iface,
53  read_MASTER_CTL(iface) | MDIR);
54  else if (iface->manual_stop)
55  write_MASTER_CTL(iface,
56  read_MASTER_CTL(iface) | STOP);
57  else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
58  iface->cur_msg + 1 < iface->msg_num) {
59  if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
60  write_MASTER_CTL(iface,
61  read_MASTER_CTL(iface) | MDIR);
62  else
63  write_MASTER_CTL(iface,
64  read_MASTER_CTL(iface) & ~MDIR);
65  }
66  }
67  if (twi_int_status & RCVSERV) {
68  if (iface->readNum > 0) {
69  /* Receive next data */
70  *(iface->transPtr) = read_RCV_DATA8(iface);
71  if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
72  /* Change combine mode into sub mode after
73  * read first data.
74  */
75  iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
76  /* Get read number from first byte in block
77  * combine mode.
78  */
79  if (iface->readNum == 1 && iface->manual_stop)
80  iface->readNum = *iface->transPtr + 1;
81  }
82  iface->transPtr++;
83  iface->readNum--;
84  }
85 
86  if (iface->readNum == 0) {
87  if (iface->manual_stop) {
88  /* Temporary workaround to avoid possible bus stall -
89  * Flush FIFO before issuing the STOP condition
90  */
91  read_RCV_DATA16(iface);
92  write_MASTER_CTL(iface,
93  read_MASTER_CTL(iface) | STOP);
94  } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
95  iface->cur_msg + 1 < iface->msg_num) {
96  if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
97  write_MASTER_CTL(iface,
98  read_MASTER_CTL(iface) | MDIR);
99  else
100  write_MASTER_CTL(iface,
101  read_MASTER_CTL(iface) & ~MDIR);
102  }
103  }
104  }
105  if (twi_int_status & MERR) {
106  write_INT_MASK(iface, 0);
107  write_MASTER_STAT(iface, 0x3e);
108  write_MASTER_CTL(iface, 0);
109  iface->result = -EIO;
110 
111  if (mast_stat & LOSTARB)
112  dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
113  if (mast_stat & ANAK)
114  dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
115  if (mast_stat & DNAK)
116  dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
117  if (mast_stat & BUFRDERR)
118  dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
119  if (mast_stat & BUFWRERR)
120  dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
121 
122  /* Faulty slave devices, may drive SDA low after a transfer
123  * finishes. To release the bus this code generates up to 9
124  * extra clocks until SDA is released.
125  */
126 
127  if (read_MASTER_STAT(iface) & SDASEN) {
128  int cnt = 9;
129  do {
130  write_MASTER_CTL(iface, SCLOVR);
131  udelay(6);
132  write_MASTER_CTL(iface, 0);
133  udelay(6);
134  } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
135 
136  write_MASTER_CTL(iface, SDAOVR | SCLOVR);
137  udelay(6);
138  write_MASTER_CTL(iface, SDAOVR);
139  udelay(6);
140  write_MASTER_CTL(iface, 0);
141  }
142 
143  /* If it is a quick transfer, only address without data,
144  * not an err, return 1.
145  */
146  if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
147  iface->transPtr == NULL &&
148  (twi_int_status & MCOMP) && (mast_stat & DNAK))
149  iface->result = 1;
150 
151  complete(&iface->complete);
152  return;
153  }
154  if (twi_int_status & MCOMP) {
155  if (twi_int_status & (XMTSERV | RCVSERV) &&
156  (read_MASTER_CTL(iface) & MEN) == 0 &&
157  (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
158  iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
159  iface->result = -1;
160  write_INT_MASK(iface, 0);
161  write_MASTER_CTL(iface, 0);
162  } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
163  if (iface->readNum == 0) {
164  /* set the read number to 1 and ask for manual
165  * stop in block combine mode
166  */
167  iface->readNum = 1;
168  iface->manual_stop = 1;
169  write_MASTER_CTL(iface,
170  read_MASTER_CTL(iface) | (0xff << 6));
171  } else {
172  /* set the readd number in other
173  * combine mode.
174  */
175  write_MASTER_CTL(iface,
176  (read_MASTER_CTL(iface) &
177  (~(0xff << 6))) |
178  (iface->readNum << 6));
179  }
180  /* remove restart bit and enable master receive */
181  write_MASTER_CTL(iface,
182  read_MASTER_CTL(iface) & ~RSTART);
183  } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
184  iface->cur_msg + 1 < iface->msg_num) {
185  iface->cur_msg++;
186  iface->transPtr = iface->pmsg[iface->cur_msg].buf;
187  iface->writeNum = iface->readNum =
188  iface->pmsg[iface->cur_msg].len;
189  /* Set Transmit device address */
190  write_MASTER_ADDR(iface,
191  iface->pmsg[iface->cur_msg].addr);
192  if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
193  iface->read_write = I2C_SMBUS_READ;
194  else {
195  iface->read_write = I2C_SMBUS_WRITE;
196  /* Transmit first data */
197  if (iface->writeNum > 0) {
198  write_XMT_DATA8(iface,
199  *(iface->transPtr++));
200  iface->writeNum--;
201  }
202  }
203 
204  if (iface->pmsg[iface->cur_msg].len <= 255) {
205  write_MASTER_CTL(iface,
206  (read_MASTER_CTL(iface) &
207  (~(0xff << 6))) |
208  (iface->pmsg[iface->cur_msg].len << 6));
209  iface->manual_stop = 0;
210  } else {
211  write_MASTER_CTL(iface,
212  (read_MASTER_CTL(iface) |
213  (0xff << 6)));
214  iface->manual_stop = 1;
215  }
216  /* remove restart bit before last message */
217  if (iface->cur_msg + 1 == iface->msg_num)
218  write_MASTER_CTL(iface,
219  read_MASTER_CTL(iface) & ~RSTART);
220  } else {
221  iface->result = 1;
222  write_INT_MASK(iface, 0);
223  write_MASTER_CTL(iface, 0);
224  }
225  complete(&iface->complete);
226  }
227 }
228 
229 /* Interrupt handler */
230 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
231 {
232  struct bfin_twi_iface *iface = dev_id;
233  unsigned long flags;
234  unsigned short twi_int_status;
235 
236  spin_lock_irqsave(&iface->lock, flags);
237  while (1) {
238  twi_int_status = read_INT_STAT(iface);
239  if (!twi_int_status)
240  break;
241  /* Clear interrupt status */
242  write_INT_STAT(iface, twi_int_status);
243  bfin_twi_handle_interrupt(iface, twi_int_status);
244  SSYNC();
245  }
246  spin_unlock_irqrestore(&iface->lock, flags);
247  return IRQ_HANDLED;
248 }
249 
250 /*
251  * One i2c master transfer
252  */
253 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
254  struct i2c_msg *msgs, int num)
255 {
256  struct bfin_twi_iface *iface = adap->algo_data;
257  struct i2c_msg *pmsg;
258  int rc = 0;
259 
260  if (!(read_CONTROL(iface) & TWI_ENA))
261  return -ENXIO;
262 
263  if (read_MASTER_STAT(iface) & BUSBUSY)
264  return -EAGAIN;
265 
266  iface->pmsg = msgs;
267  iface->msg_num = num;
268  iface->cur_msg = 0;
269 
270  pmsg = &msgs[0];
271  if (pmsg->flags & I2C_M_TEN) {
272  dev_err(&adap->dev, "10 bits addr not supported!\n");
273  return -EINVAL;
274  }
275 
276  if (iface->msg_num > 1)
277  iface->cur_mode = TWI_I2C_MODE_REPEAT;
278  iface->manual_stop = 0;
279  iface->transPtr = pmsg->buf;
280  iface->writeNum = iface->readNum = pmsg->len;
281  iface->result = 0;
282  init_completion(&(iface->complete));
283  /* Set Transmit device address */
284  write_MASTER_ADDR(iface, pmsg->addr);
285 
286  /* FIFO Initiation. Data in FIFO should be
287  * discarded before start a new operation.
288  */
289  write_FIFO_CTL(iface, 0x3);
290  SSYNC();
291  write_FIFO_CTL(iface, 0);
292  SSYNC();
293 
294  if (pmsg->flags & I2C_M_RD)
295  iface->read_write = I2C_SMBUS_READ;
296  else {
297  iface->read_write = I2C_SMBUS_WRITE;
298  /* Transmit first data */
299  if (iface->writeNum > 0) {
300  write_XMT_DATA8(iface, *(iface->transPtr++));
301  iface->writeNum--;
302  SSYNC();
303  }
304  }
305 
306  /* clear int stat */
307  write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
308 
309  /* Interrupt mask . Enable XMT, RCV interrupt */
310  write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
311  SSYNC();
312 
313  if (pmsg->len <= 255)
314  write_MASTER_CTL(iface, pmsg->len << 6);
315  else {
316  write_MASTER_CTL(iface, 0xff << 6);
317  iface->manual_stop = 1;
318  }
319 
320  /* Master enable */
321  write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
322  (iface->msg_num > 1 ? RSTART : 0) |
323  ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
324  ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
325  SSYNC();
326 
327  while (!iface->result) {
328  if (!wait_for_completion_timeout(&iface->complete,
329  adap->timeout)) {
330  iface->result = -1;
331  dev_err(&adap->dev, "master transfer timeout\n");
332  }
333  }
334 
335  if (iface->result == 1)
336  rc = iface->cur_msg + 1;
337  else
338  rc = iface->result;
339 
340  return rc;
341 }
342 
343 /*
344  * Generic i2c master transfer entrypoint
345  */
346 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
347  struct i2c_msg *msgs, int num)
348 {
349  return bfin_twi_do_master_xfer(adap, msgs, num);
350 }
351 
352 /*
353  * One I2C SMBus transfer
354  */
355 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
356  unsigned short flags, char read_write,
357  u8 command, int size, union i2c_smbus_data *data)
358 {
359  struct bfin_twi_iface *iface = adap->algo_data;
360  int rc = 0;
361 
362  if (!(read_CONTROL(iface) & TWI_ENA))
363  return -ENXIO;
364 
365  if (read_MASTER_STAT(iface) & BUSBUSY)
366  return -EAGAIN;
367 
368  iface->writeNum = 0;
369  iface->readNum = 0;
370 
371  /* Prepare datas & select mode */
372  switch (size) {
373  case I2C_SMBUS_QUICK:
374  iface->transPtr = NULL;
375  iface->cur_mode = TWI_I2C_MODE_STANDARD;
376  break;
377  case I2C_SMBUS_BYTE:
378  if (data == NULL)
379  iface->transPtr = NULL;
380  else {
381  if (read_write == I2C_SMBUS_READ)
382  iface->readNum = 1;
383  else
384  iface->writeNum = 1;
385  iface->transPtr = &data->byte;
386  }
387  iface->cur_mode = TWI_I2C_MODE_STANDARD;
388  break;
389  case I2C_SMBUS_BYTE_DATA:
390  if (read_write == I2C_SMBUS_READ) {
391  iface->readNum = 1;
392  iface->cur_mode = TWI_I2C_MODE_COMBINED;
393  } else {
394  iface->writeNum = 1;
395  iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
396  }
397  iface->transPtr = &data->byte;
398  break;
399  case I2C_SMBUS_WORD_DATA:
400  if (read_write == I2C_SMBUS_READ) {
401  iface->readNum = 2;
402  iface->cur_mode = TWI_I2C_MODE_COMBINED;
403  } else {
404  iface->writeNum = 2;
405  iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
406  }
407  iface->transPtr = (u8 *)&data->word;
408  break;
409  case I2C_SMBUS_PROC_CALL:
410  iface->writeNum = 2;
411  iface->readNum = 2;
412  iface->cur_mode = TWI_I2C_MODE_COMBINED;
413  iface->transPtr = (u8 *)&data->word;
414  break;
415  case I2C_SMBUS_BLOCK_DATA:
416  if (read_write == I2C_SMBUS_READ) {
417  iface->readNum = 0;
418  iface->cur_mode = TWI_I2C_MODE_COMBINED;
419  } else {
420  iface->writeNum = data->block[0] + 1;
421  iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
422  }
423  iface->transPtr = data->block;
424  break;
425  case I2C_SMBUS_I2C_BLOCK_DATA:
426  if (read_write == I2C_SMBUS_READ) {
427  iface->readNum = data->block[0];
428  iface->cur_mode = TWI_I2C_MODE_COMBINED;
429  } else {
430  iface->writeNum = data->block[0];
431  iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
432  }
433  iface->transPtr = (u8 *)&data->block[1];
434  break;
435  default:
436  return -1;
437  }
438 
439  iface->result = 0;
440  iface->manual_stop = 0;
441  iface->read_write = read_write;
442  iface->command = command;
443  init_completion(&(iface->complete));
444 
445  /* FIFO Initiation. Data in FIFO should be discarded before
446  * start a new operation.
447  */
448  write_FIFO_CTL(iface, 0x3);
449  SSYNC();
450  write_FIFO_CTL(iface, 0);
451 
452  /* clear int stat */
453  write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
454 
455  /* Set Transmit device address */
456  write_MASTER_ADDR(iface, addr);
457  SSYNC();
458 
459  switch (iface->cur_mode) {
460  case TWI_I2C_MODE_STANDARDSUB:
461  write_XMT_DATA8(iface, iface->command);
462  write_INT_MASK(iface, MCOMP | MERR |
463  ((iface->read_write == I2C_SMBUS_READ) ?
464  RCVSERV : XMTSERV));
465  SSYNC();
466 
467  if (iface->writeNum + 1 <= 255)
468  write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
469  else {
470  write_MASTER_CTL(iface, 0xff << 6);
471  iface->manual_stop = 1;
472  }
473  /* Master enable */
474  write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
475  ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
476  break;
477  case TWI_I2C_MODE_COMBINED:
478  write_XMT_DATA8(iface, iface->command);
479  write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
480  SSYNC();
481 
482  if (iface->writeNum > 0)
483  write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
484  else
485  write_MASTER_CTL(iface, 0x1 << 6);
486  /* Master enable */
487  write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
488  ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
489  break;
490  default:
491  write_MASTER_CTL(iface, 0);
492  if (size != I2C_SMBUS_QUICK) {
493  /* Don't access xmit data register when this is a
494  * read operation.
495  */
496  if (iface->read_write != I2C_SMBUS_READ) {
497  if (iface->writeNum > 0) {
498  write_XMT_DATA8(iface,
499  *(iface->transPtr++));
500  if (iface->writeNum <= 255)
501  write_MASTER_CTL(iface,
502  iface->writeNum << 6);
503  else {
504  write_MASTER_CTL(iface,
505  0xff << 6);
506  iface->manual_stop = 1;
507  }
508  iface->writeNum--;
509  } else {
510  write_XMT_DATA8(iface, iface->command);
511  write_MASTER_CTL(iface, 1 << 6);
512  }
513  } else {
514  if (iface->readNum > 0 && iface->readNum <= 255)
515  write_MASTER_CTL(iface,
516  iface->readNum << 6);
517  else if (iface->readNum > 255) {
518  write_MASTER_CTL(iface, 0xff << 6);
519  iface->manual_stop = 1;
520  } else
521  break;
522  }
523  }
524  write_INT_MASK(iface, MCOMP | MERR |
525  ((iface->read_write == I2C_SMBUS_READ) ?
526  RCVSERV : XMTSERV));
527  SSYNC();
528 
529  /* Master enable */
530  write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
531  ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
532  ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
533  break;
534  }
535  SSYNC();
536 
537  while (!iface->result) {
538  if (!wait_for_completion_timeout(&iface->complete,
539  adap->timeout)) {
540  iface->result = -1;
541  dev_err(&adap->dev, "smbus transfer timeout\n");
542  }
543  }
544 
545  rc = (iface->result >= 0) ? 0 : -1;
546 
547  return rc;
548 }
549 
550 /*
551  * Generic I2C SMBus transfer entrypoint
552  */
553 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
554  unsigned short flags, char read_write,
555  u8 command, int size, union i2c_smbus_data *data)
556 {
557  return bfin_twi_do_smbus_xfer(adap, addr, flags,
558  read_write, command, size, data);
559 }
560 
561 /*
562  * Return what the adapter supports
563  */
564 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
565 {
566  return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
567  I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
568  I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
569  I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
570 }
571 
572 static struct i2c_algorithm bfin_twi_algorithm = {
573  .master_xfer = bfin_twi_master_xfer,
574  .smbus_xfer = bfin_twi_smbus_xfer,
575  .functionality = bfin_twi_functionality,
576 };
577 
578 static int i2c_bfin_twi_suspend(struct device *dev)
579 {
580  struct bfin_twi_iface *iface = dev_get_drvdata(dev);
581 
582  iface->saved_clkdiv = read_CLKDIV(iface);
583  iface->saved_control = read_CONTROL(iface);
584 
585  free_irq(iface->irq, iface);
586 
587  /* Disable TWI */
588  write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
589 
590  return 0;
591 }
592 
593 static int i2c_bfin_twi_resume(struct device *dev)
594 {
595  struct bfin_twi_iface *iface = dev_get_drvdata(dev);
596 
597  int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
598  0, to_platform_device(dev)->name, iface);
599  if (rc) {
600  dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
601  return -ENODEV;
602  }
603 
604  /* Resume TWI interface clock as specified */
605  write_CLKDIV(iface, iface->saved_clkdiv);
606 
607  /* Resume TWI */
608  write_CONTROL(iface, iface->saved_control);
609 
610  return 0;
611 }
612 
613 static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
614  i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
615 
616 static int i2c_bfin_twi_probe(struct platform_device *pdev)
617 {
618  struct bfin_twi_iface *iface;
619  struct i2c_adapter *p_adap;
620  struct resource *res;
621  int rc;
622  unsigned int clkhilow;
623 
624  iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
625  if (!iface) {
626  dev_err(&pdev->dev, "Cannot allocate memory\n");
627  rc = -ENOMEM;
628  goto out_error_nomem;
629  }
630 
631  spin_lock_init(&(iface->lock));
632 
633  /* Find and map our resources */
634  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
635  if (res == NULL) {
636  dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
637  rc = -ENOENT;
638  goto out_error_get_res;
639  }
640 
641  iface->regs_base = ioremap(res->start, resource_size(res));
642  if (iface->regs_base == NULL) {
643  dev_err(&pdev->dev, "Cannot map IO\n");
644  rc = -ENXIO;
645  goto out_error_ioremap;
646  }
647 
648  iface->irq = platform_get_irq(pdev, 0);
649  if (iface->irq < 0) {
650  dev_err(&pdev->dev, "No IRQ specified\n");
651  rc = -ENOENT;
652  goto out_error_no_irq;
653  }
654 
655  p_adap = &iface->adap;
656  p_adap->nr = pdev->id;
657  strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
658  p_adap->algo = &bfin_twi_algorithm;
659  p_adap->algo_data = iface;
660  p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
661  p_adap->dev.parent = &pdev->dev;
662  p_adap->timeout = 5 * HZ;
663  p_adap->retries = 3;
664 
665  rc = peripheral_request_list((unsigned short *)pdev->dev.platform_data,
666  "i2c-bfin-twi");
667  if (rc) {
668  dev_err(&pdev->dev, "Can't setup pin mux!\n");
669  goto out_error_pin_mux;
670  }
671 
672  rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
673  0, pdev->name, iface);
674  if (rc) {
675  dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
676  rc = -ENODEV;
677  goto out_error_req_irq;
678  }
679 
680  /* Set TWI internal clock as 10MHz */
681  write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
682 
683  /*
684  * We will not end up with a CLKDIV=0 because no one will specify
685  * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
686  */
687  clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
688 
689  /* Set Twi interface clock as specified */
690  write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
691 
692  /* Enable TWI */
693  write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
694  SSYNC();
695 
696  rc = i2c_add_numbered_adapter(p_adap);
697  if (rc < 0) {
698  dev_err(&pdev->dev, "Can't add i2c adapter!\n");
699  goto out_error_add_adapter;
700  }
701 
702  platform_set_drvdata(pdev, iface);
703 
704  dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
705  "regs_base@%p\n", iface->regs_base);
706 
707  return 0;
708 
709 out_error_add_adapter:
710  free_irq(iface->irq, iface);
711 out_error_req_irq:
712 out_error_no_irq:
713  peripheral_free_list((unsigned short *)pdev->dev.platform_data);
714 out_error_pin_mux:
715  iounmap(iface->regs_base);
716 out_error_ioremap:
717 out_error_get_res:
718  kfree(iface);
719 out_error_nomem:
720  return rc;
721 }
722 
723 static int i2c_bfin_twi_remove(struct platform_device *pdev)
724 {
725  struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
726 
727  platform_set_drvdata(pdev, NULL);
728 
729  i2c_del_adapter(&(iface->adap));
730  free_irq(iface->irq, iface);
731  peripheral_free_list((unsigned short *)pdev->dev.platform_data);
732  iounmap(iface->regs_base);
733  kfree(iface);
734 
735  return 0;
736 }
737 
738 static struct platform_driver i2c_bfin_twi_driver = {
739  .probe = i2c_bfin_twi_probe,
740  .remove = i2c_bfin_twi_remove,
741  .driver = {
742  .name = "i2c-bfin-twi",
743  .owner = THIS_MODULE,
744  .pm = &i2c_bfin_twi_pm,
745  },
746 };
747 
748 static int __init i2c_bfin_twi_init(void)
749 {
750  return platform_driver_register(&i2c_bfin_twi_driver);
751 }
752 
753 static void __exit i2c_bfin_twi_exit(void)
754 {
755  platform_driver_unregister(&i2c_bfin_twi_driver);
756 }
757 
758 subsys_initcall(i2c_bfin_twi_init);
759 module_exit(i2c_bfin_twi_exit);
760 
761 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
762 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
763 MODULE_LICENSE("GPL");
764 MODULE_ALIAS("platform:i2c-bfin-twi");
Generated on Thu Jan 10 2013 13:35:31 for Linux Kernel by   doxygen 1.8.2