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i82975x_edac.c File Reference
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_core.h"

Go to the source code of this file.

Data Structures

struct  i82975x_pvt
 
struct  i82975x_dev_info
 
struct  i82975x_error_info
 

Macros

#define I82975X_REVISION   " Ver: 1.0.0"
 
#define EDAC_MOD_STR   "i82975x_edac"
 
#define i82975x_printk(level, fmt, arg...)   edac_printk(level, "i82975x", fmt, ##arg)
 
#define i82975x_mc_printk(mci, level, fmt, arg...)   edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
 
#define PCI_DEVICE_ID_INTEL_82975_0   0x277c
 
#define I82975X_NR_DIMMS   8
 
#define I82975X_NR_CSROWS(nr_chans)   (I82975X_NR_DIMMS / (nr_chans))
 
#define I82975X_EAP
 
#define I82975X_DERRSYN
 
#define I82975X_DES
 
#define I82975X_ERRSTS
 
#define I82975X_ERRCMD
 
#define I82975X_SMICMD
 
#define I82975X_SCICMD
 
#define I82975X_XEAP
 
#define I82975X_MCHBAR
 
#define I82975X_DRB_SHIFT   25 /* fixed 32MiB grain */
 
#define I82975X_DRB
 
#define I82975X_DRB_CH0R0   0x100
 
#define I82975X_DRB_CH0R1   0x101
 
#define I82975X_DRB_CH0R2   0x102
 
#define I82975X_DRB_CH0R3   0x103
 
#define I82975X_DRB_CH1R0   0x180
 
#define I82975X_DRB_CH1R1   0x181
 
#define I82975X_DRB_CH1R2   0x182
 
#define I82975X_DRB_CH1R3   0x183
 
#define I82975X_DRA
 
#define I82975X_DRA_CH0R01   0x108
 
#define I82975X_DRA_CH0R23   0x109
 
#define I82975X_DRA_CH1R01   0x188
 
#define I82975X_DRA_CH1R23   0x189
 
#define I82975X_BNKARC
 
#define I82975X_C0BNKARC   0x10e
 
#define I82975X_C1BNKARC   0x18e
 
#define I82975X_DRC
 
#define I82975X_DRC_CH0M0   0x120
 
#define I82975X_DRC_CH1M0   0x1A0
 
#define I82975X_DRC_M1
 
#define I82975X_DRC_CH0M1   0x124
 
#define I82975X_DRC_CH1M1   0x1A4
 

Enumerations

enum  i82975x_chips { I82975X = 0 }
 

Functions

 MODULE_DEVICE_TABLE (pci, i82975x_pci_tbl)
 
 module_init (i82975x_init)
 
 module_exit (i82975x_exit)
 
 MODULE_LICENSE ("GPL")
 
 MODULE_AUTHOR ("Arvind R. <[email protected]>")
 
 MODULE_DESCRIPTION ("MC support for Intel 82975 memory hub controllers")
 
 module_param (edac_op_state, int, 0444)
 
 MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")
 

Macro Definition Documentation

#define EDAC_MOD_STR   "i82975x_edac"

Definition at line 20 of file i82975x_edac.c.

#define I82975X_BNKARC
Value:
0x10e /* Type of device in each rank - Bank Arch (16b)
*
* 15:8 reserved
* 7:6 Rank 3 architecture
* 5:4 Rank 2 architecture
* 3:2 Rank 1 architecture
* 1:0 Rank 0 architecture
*
* 00 => 4 banks
* 01 => 8 banks
*/

Definition at line 83 of file i82975x_edac.c.

#define I82975X_C0BNKARC   0x10e

Definition at line 84 of file i82975x_edac.c.

#define I82975X_C1BNKARC   0x18e

Definition at line 85 of file i82975x_edac.c.

#define I82975X_DERRSYN
Value:
0x5c /* Dram Error SYNdrome (8b)
*
* 7:0 DRAM ECC Syndrome
*/

Definition at line 38 of file i82975x_edac.c.

#define I82975X_DES
Value:
0x5d /* Dram ERRor DeSTination (8b)
* 0h: Processor Memory Reads
* 1h:7h reserved
* More - See Page 65 of Intel DocSheet.
*/

Definition at line 40 of file i82975x_edac.c.

#define I82975X_DRA
Value:
0x108 /* DRAM Row Attribute (4b x 8)
* defines the PAGE SIZE to be used
* for the rank
* 7 reserved
* 6:4 row attr of odd rank, i.e. 1
* 3 reserved
* 2:0 row attr of even rank, i.e. 0
*
* 000 = unpopulated
* 001 = reserved
* 010 = 4KiB
* 011 = 8KiB
* 100 = 16KiB
* others = reserved
*/

Definition at line 76 of file i82975x_edac.c.

#define I82975X_DRA_CH0R01   0x108

Definition at line 77 of file i82975x_edac.c.

#define I82975X_DRA_CH0R23   0x109

Definition at line 78 of file i82975x_edac.c.

#define I82975X_DRA_CH1R01   0x188

Definition at line 79 of file i82975x_edac.c.

#define I82975X_DRA_CH1R23   0x189

Definition at line 80 of file i82975x_edac.c.

#define I82975X_DRB
Value:
0x100 /* DRAM Row Boundary (8b x 8)
*
* 7 set to 1 in highest DRB of
* channel if 4GB in ch.
* 6:2 upper boundary of rank in
* 32MB grains
* 1:0 set to 0
*/

Definition at line 65 of file i82975x_edac.c.

#define I82975X_DRB_CH0R0   0x100

Definition at line 66 of file i82975x_edac.c.

#define I82975X_DRB_CH0R1   0x101

Definition at line 67 of file i82975x_edac.c.

#define I82975X_DRB_CH0R2   0x102

Definition at line 68 of file i82975x_edac.c.

#define I82975X_DRB_CH0R3   0x103

Definition at line 69 of file i82975x_edac.c.

#define I82975X_DRB_CH1R0   0x180

Definition at line 70 of file i82975x_edac.c.

#define I82975X_DRB_CH1R1   0x181

Definition at line 71 of file i82975x_edac.c.

#define I82975X_DRB_CH1R2   0x182

Definition at line 72 of file i82975x_edac.c.

#define I82975X_DRB_CH1R3   0x183

Definition at line 73 of file i82975x_edac.c.

#define I82975X_DRB_SHIFT   25 /* fixed 32MiB grain */

Definition at line 63 of file i82975x_edac.c.

#define I82975X_DRC
Value:
0x120 /* DRAM Controller Mode0 (32b)
*
* 31:30 reserved
* 29 init complete
* 28:11 reserved, according to Intel
* 22:21 number of channels
* 00=1 01=2 in 82875
* seems to be ECC mode
* bits in 82975 in Asus
* P5W
* 19:18 Data Integ Mode
* 00=none 01=ECC in 82875
* 10:8 refresh mode
* 7 reserved
* 6:4 mode select
* 3:2 reserved
* 1:0 DRAM type 10=Second Revision
* DDR2 SDRAM
* 00, 01, 11 reserved
*/

Definition at line 89 of file i82975x_edac.c.

#define I82975X_DRC_CH0M0   0x120

Definition at line 90 of file i82975x_edac.c.

#define I82975X_DRC_CH0M1   0x124

Definition at line 96 of file i82975x_edac.c.

#define I82975X_DRC_CH1M0   0x1A0

Definition at line 91 of file i82975x_edac.c.

#define I82975X_DRC_CH1M1   0x1A4

Definition at line 97 of file i82975x_edac.c.

#define I82975X_DRC_M1
Value:
0x124 /* DRAM Controller Mode1 (32b)
* 31 0=Standard Address Map
* 1=Enhanced Address Map
* 30:0 reserved
*/

Definition at line 94 of file i82975x_edac.c.

#define I82975X_EAP
Value:
0x58 /* Dram Error Address Pointer (32b)
*
* 31:7 128 byte cache-line address
* 6:1 reserved
* 0 0: CH0; 1: CH1
*/

Definition at line 36 of file i82975x_edac.c.

#define I82975X_ERRCMD
Value:
0xca /* Error Command (16b)
*
* 15:12 reserved
* 11 Thermal Sensor Event
* 10 reserved
* 9 non-DRAM lock error (ndlock)
* 8 Refresh Timeout
* 7:2 reserved
* 1 ECC UE (multibit DRAM error)
* 0 ECC CE (singlebit DRAM error)
*/

Definition at line 50 of file i82975x_edac.c.

#define I82975X_ERRSTS
Value:
0xc8 /* Error Status Register (16b)
*
* 15:12 reserved
* 11 Thermal Sensor Event
* 10 reserved
* 9 non-DRAM lock error (ndlock)
* 8 Refresh Timeout
* 7:2 reserved
* 1 ECC UE (multibit DRAM error)
* 0 ECC CE (singlebit DRAM error)
*/

Definition at line 42 of file i82975x_edac.c.

#define i82975x_mc_printk (   mci,
  level,
  fmt,
  arg... 
)    edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)

Definition at line 25 of file i82975x_edac.c.

#define I82975X_MCHBAR
Value:
0x44 /*
*
* 31:14 Base Addr of 16K memory-mapped
* configuration space
* 13:1 reserverd
* 0 mem-mapped config space enable
*/

Definition at line 58 of file i82975x_edac.c.

#define I82975X_NR_CSROWS (   nr_chans)    (I82975X_NR_DIMMS / (nr_chans))

Definition at line 33 of file i82975x_edac.c.

#define I82975X_NR_DIMMS   8

Definition at line 32 of file i82975x_edac.c.

#define i82975x_printk (   level,
  fmt,
  arg... 
)    edac_printk(level, "i82975x", fmt, ##arg)

Definition at line 22 of file i82975x_edac.c.

#define I82975X_REVISION   " Ver: 1.0.0"

Definition at line 19 of file i82975x_edac.c.

#define I82975X_SCICMD
Value:
0xce /* Error Command (16b)
*
* 15:2 reserved
* 1 ECC UE (multibit DRAM error)
* 0 ECC CE (singlebit DRAM error)
*/

Definition at line 54 of file i82975x_edac.c.

#define I82975X_SMICMD
Value:
0xcc /* Error Command (16b)
*
* 15:2 reserved
* 1 ECC UE (multibit DRAM error)
* 0 ECC CE (singlebit DRAM error)
*/

Definition at line 52 of file i82975x_edac.c.

#define I82975X_XEAP
Value:
0xfc /* Extended Dram Error Address Pointer (8b)
*
* 7:1 reserved
* 0 Bit32 of the Dram Error Address
*/

Definition at line 56 of file i82975x_edac.c.

#define PCI_DEVICE_ID_INTEL_82975_0   0x277c

Definition at line 29 of file i82975x_edac.c.

Enumeration Type Documentation

enum i82975x_chips
Enumerator:
I82975X 

Definition at line 99 of file i82975x_edac.c.

Function Documentation

MODULE_AUTHOR ( "Arvind R. <[email protected]>"  )
MODULE_DESCRIPTION ( "MC support for Intel 82975 memory hub controllers"  )
MODULE_DEVICE_TABLE ( pci  ,
i82975x_pci_tbl   
)
module_exit ( i82975x_exit  )
module_init ( i82975x_init  )
MODULE_LICENSE ( "GPL"  )
module_param ( edac_op_state  ,
int  ,
0444   
)
MODULE_PARM_DESC ( edac_op_state  ,
"EDAC Error Reporting state:  0 = Poll 
)
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