#include <linux/cpufreq.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "../../../platform/x86/intel_ips.h"
#include <linux/module.h>

Data Structures
struct	cparams

Macros
#define	FORCEWAKE_ACK_TIMEOUT_MS 2

#define	single_plane_enabled(mask) is_power_of_2(mask)

#define	ILK_LP0_PLANE_LATENCY 700

#define	ILK_LP0_CURSOR_LATENCY 1300

Functions
bool	intel_fbc_enabled (struct drm_device *dev)

void	intel_enable_fbc (struct drm_crtc *crtc, unsigned long interval)

void	intel_disable_fbc (struct drm_device *dev)

void	intel_update_fbc (struct drm_device *dev)

void	intel_update_watermarks (struct drm_device *dev)

void	intel_update_linetime_watermarks (struct drm_device dev, int pipe, struct drm_display_mode mode)

void	intel_update_sprite_watermarks (struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size)

	DEFINE_SPINLOCK (mchdev_lock)

bool	ironlake_set_drps (struct drm_device *dev, u8 val)

void	gen6_set_rps (struct drm_device *dev, u8 val)

int	intel_enable_rc6 (const struct drm_device *dev)

void	ironlake_teardown_rc6 (struct drm_device *dev)

unsigned long	i915_chipset_val (struct drm_i915_private *dev_priv)

unsigned long	i915_mch_val (struct drm_i915_private *dev_priv)

void	i915_update_gfx_val (struct drm_i915_private *dev_priv)

unsigned long	i915_gfx_val (struct drm_i915_private *dev_priv)

unsigned long	i915_read_mch_val (void)

	EXPORT_SYMBOL_GPL (i915_read_mch_val)

bool	i915_gpu_raise (void)

	EXPORT_SYMBOL_GPL (i915_gpu_raise)

bool	i915_gpu_lower (void)

	EXPORT_SYMBOL_GPL (i915_gpu_lower)

bool	i915_gpu_busy (void)

	EXPORT_SYMBOL_GPL (i915_gpu_busy)

bool	i915_gpu_turbo_disable (void)

	EXPORT_SYMBOL_GPL (i915_gpu_turbo_disable)

void	intel_gpu_ips_init (struct drm_i915_private *dev_priv)

void	intel_gpu_ips_teardown (void)

void	intel_disable_gt_powersave (struct drm_device *dev)

void	intel_enable_gt_powersave (struct drm_device *dev)

void	intel_init_clock_gating (struct drm_device *dev)

void	intel_init_power_wells (struct drm_device *dev)

void	intel_init_pm (struct drm_device *dev)

void	gen6_gt_force_wake_get (struct drm_i915_private *dev_priv)

void	gen6_gt_check_fifodbg (struct drm_i915_private *dev_priv)

void	gen6_gt_force_wake_put (struct drm_i915_private *dev_priv)

int	__gen6_gt_wait_for_fifo (struct drm_i915_private *dev_priv)

void	intel_gt_init (struct drm_device *dev)

Macro Definition Documentation

#define FORCEWAKE_ACK_TIMEOUT_MS 2

Definition at line 34 of file intel_pm.c.

#define ILK_LP0_CURSOR_LATENCY 1300

Definition at line 1585 of file intel_pm.c.

#define ILK_LP0_PLANE_LATENCY 700

Definition at line 1584 of file intel_pm.c.

#define single_plane_enabled ( mask ) is_power_of_2(mask)

Definition at line 1281 of file intel_pm.c.

Function Documentation

int __gen6_gt_wait_for_fifo ( struct drm_i915_private * dev_priv )

Definition at line 4094 of file intel_pm.c.

DEFINE_SPINLOCK ( mchdev_lock )

Lock protecting IPS related data structures

EXPORT_SYMBOL_GPL ( i915_read_mch_val )

EXPORT_SYMBOL_GPL ( i915_gpu_raise )

EXPORT_SYMBOL_GPL ( i915_gpu_lower )

EXPORT_SYMBOL_GPL ( i915_gpu_busy )

EXPORT_SYMBOL_GPL ( i915_gpu_turbo_disable )

void gen6_gt_check_fifodbg ( struct drm_i915_private * dev_priv )

Definition at line 4058 of file intel_pm.c.

void gen6_gt_force_wake_get ( struct drm_i915_private * dev_priv )

Definition at line 4048 of file intel_pm.c.

void gen6_gt_force_wake_put ( struct drm_i915_private * dev_priv )

Definition at line 4084 of file intel_pm.c.

void gen6_set_rps	(	struct drm_device *	dev,
		u8	val
	)

Definition at line 2321 of file intel_pm.c.

unsigned long i915_chipset_val ( struct drm_i915_private * dev_priv )

Definition at line 2785 of file intel_pm.c.

unsigned long i915_gfx_val ( struct drm_i915_private * dev_priv )

Definition at line 3041 of file intel_pm.c.

bool i915_gpu_busy ( void )

i915_gpu_busy - indicate GPU business to IPS

Tell the IPS driver whether or not the GPU is busy.

Definition at line 3145 of file intel_pm.c.

bool i915_gpu_lower ( void )

i915_gpu_lower - lower GPU frequency limit

IPS indicates we're close to a thermal limit, so throttle back the GPU frequency maximum.

Definition at line 3118 of file intel_pm.c.

bool i915_gpu_raise ( void )

i915_gpu_raise - raise GPU frequency limit

Raise the limit; IPS indicates we have thermal headroom.

Definition at line 3090 of file intel_pm.c.

bool i915_gpu_turbo_disable ( void )

i915_gpu_turbo_disable - disable graphics turbo

Disable graphics turbo by resetting the max frequency and setting the current frequency to the default.

Definition at line 3173 of file intel_pm.c.

unsigned long i915_mch_val ( struct drm_i915_private * dev_priv )

Definition at line 2801 of file intel_pm.c.

unsigned long i915_read_mch_val ( void )

i915_read_mch_val - return value for IPS use

Calculate and return a value for the IPS driver to use when deciding whether we have thermal and power headroom to increase CPU or GPU power budget.

Definition at line 3063 of file intel_pm.c.

void i915_update_gfx_val ( struct drm_i915_private * dev_priv )

Definition at line 2992 of file intel_pm.c.

void intel_disable_fbc ( struct drm_device * dev )

Definition at line 350 of file intel_pm.c.

void intel_disable_gt_powersave ( struct drm_device * dev )

Definition at line 3305 of file intel_pm.c.

void intel_enable_fbc	(	struct drm_crtc *	crtc,
		unsigned long	interval
	)

Definition at line 310 of file intel_pm.c.

void intel_enable_gt_powersave ( struct drm_device * dev )

Definition at line 3315 of file intel_pm.c.

int intel_enable_rc6 ( const struct drm_device * dev )

Definition at line 2370 of file intel_pm.c.

bool intel_fbc_enabled ( struct drm_device * dev )

Definition at line 248 of file intel_pm.c.

void intel_gpu_ips_init ( struct drm_i915_private * dev_priv )

Definition at line 3217 of file intel_pm.c.

void intel_gpu_ips_teardown ( void )

Definition at line 3228 of file intel_pm.c.

void intel_gt_init ( struct drm_device * dev )

Definition at line 4136 of file intel_pm.c.

void intel_init_clock_gating ( struct drm_device * dev )

Definition at line 3810 of file intel_pm.c.

void intel_init_pm ( struct drm_device * dev )

Definition at line 3852 of file intel_pm.c.

void intel_init_power_wells ( struct drm_device * dev )

Definition at line 3823 of file intel_pm.c.

void intel_update_fbc ( struct drm_device * dev )

intel_update_fbc - enable/disable FBC as needed : the drm_device

Set up the framebuffer compression hardware at mode set time. We enable it if possible:

plane A only (on pre-965)
no pixel mulitply/line duplication
no alpha buffer discard
no dual wide
framebuffer <= 2048 in width, 1536 in height

We can't assume that any compression will take place (worst case), so the compressed buffer has to be the same size as the uncompressed one. It also must reside (along with the line length buffer) in stolen memory.

We need to enable/disable FBC on a global basis.

Definition at line 382 of file intel_pm.c.

void intel_update_linetime_watermarks	(	struct drm_device *	dev,
		int	pipe,
		struct drm_display_mode *	mode
	)

Definition at line 2110 of file intel_pm.c.

void intel_update_sprite_watermarks	(	struct drm_device *	dev,
		int	pipe,
		uint32_t	sprite_width,
		int	pixel_size
	)

Definition at line 2119 of file intel_pm.c.

void intel_update_watermarks ( struct drm_device * dev )

intel_update_watermarks - update FIFO watermark values based on current modes

Calculate watermark values for the various WM regs based on current mode and plane configuration.

There are several cases to deal with here:

normal (i.e. non-self-refresh)
self-refresh (SR) mode
lines are large relative to FIFO size (buffer can hold up to 2)
lines are small relative to FIFO size (buffer can hold more than 2 lines), so need to account for TLB latency

The normal calculation is: watermark = dotclock * bytes per pixel * latency where latency is platform & configuration dependent (we assume pessimal values here).

The SR calculation is: watermark = (trunc(latency/line time)+1) * surface width * bytes per pixel where line time = htotal / dotclock surface width = hdisplay for normal plane and 64 for cursor and latency is assumed to be high, as above.

The final value programmed to the register should always be rounded up, and include an extra 2 entries to account for clock crossings.

We don't use the sprite, so we can ignore that. And on Crestline we have to set the non-SR watermarks to 8.

Definition at line 2102 of file intel_pm.c.

bool ironlake_set_drps	(	struct drm_device *	dev,
		u8	val
	)

Definition at line 2174 of file intel_pm.c.

void ironlake_teardown_rc6 ( struct drm_device * dev )

Definition at line 2592 of file intel_pm.c.

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation