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ipath_wc_x86_64.c File Reference
#include <linux/pci.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include "ipath_kernel.h"

Go to the source code of this file.


int ipath_enable_wc (struct ipath_devdata *dd)
void ipath_disable_wc (struct ipath_devdata *dd)
int ipath_unordered_wc (void)

Function Documentation

void ipath_disable_wc ( struct ipath_devdata dd)

ipath_disable_wc - disable write combining for MMIO writes to the device : infinipath device

Definition at line 155 of file ipath_wc_x86_64.c.

int ipath_enable_wc ( struct ipath_devdata dd)

ipath_enable_wc - enable write combining for MMIO writes to the device : infinipath device

This routine is x86_64-specific; it twiddles the CPU's MTRRs to enable write combining.

Definition at line 52 of file ipath_wc_x86_64.c.

int ipath_unordered_wc ( void  )

ipath_unordered_wc - indicate whether write combining is ordered

Because our performance depends on our ability to do write combining mmio writes in the most efficient way, we need to know if we are on an Intel or AMD x86_64 processor. AMD x86_64 processors flush WC buffers out in the order completed, and so no special flushing is required to get correct ordering. Intel processors, however, will flush write buffers out in "random" orders, and so explicit ordering is needed at times.

Definition at line 181 of file ipath_wc_x86_64.c.