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69 #ifndef __iwl_commands_h__
70 #define __iwl_commands_h__
73 #include <linux/types.h>
202 #define IWL_MIN_NUM_QUEUES 11
207 #define IWL_DEFAULT_CMD_QUEUE_NUM 4
208 #define IWL_IPAN_CMD_QUEUE_NUM 9
210 #define IWL_TX_FIFO_BK 0
211 #define IWL_TX_FIFO_BE 1
212 #define IWL_TX_FIFO_VI 2
213 #define IWL_TX_FIFO_VO 3
214 #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
215 #define IWL_TX_FIFO_BE_IPAN 4
216 #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
217 #define IWL_TX_FIFO_VO_IPAN 5
219 #define IWL_TX_FIFO_AUX 5
220 #define IWL_TX_FIFO_UNUSED 255
222 #define IWLAGN_CMD_FIFO_NUM 7
229 #define IWL_IPAN_MCAST_QUEUE 8
279 #define RATE_MCS_CODE_MSK 0x7
280 #define RATE_MCS_SPATIAL_POS 3
281 #define RATE_MCS_SPATIAL_MSK 0x18
282 #define RATE_MCS_HT_DUP_POS 5
283 #define RATE_MCS_HT_DUP_MSK 0x20
285 #define RATE_MCS_RATE_MSK 0xff
288 #define RATE_MCS_FLAGS_POS 8
289 #define RATE_MCS_HT_POS 8
290 #define RATE_MCS_HT_MSK 0x100
293 #define RATE_MCS_CCK_POS 9
294 #define RATE_MCS_CCK_MSK 0x200
297 #define RATE_MCS_GF_POS 10
298 #define RATE_MCS_GF_MSK 0x400
301 #define RATE_MCS_HT40_POS 11
302 #define RATE_MCS_HT40_MSK 0x800
305 #define RATE_MCS_DUP_POS 12
306 #define RATE_MCS_DUP_MSK 0x1000
309 #define RATE_MCS_SGI_POS 13
310 #define RATE_MCS_SGI_MSK 0x2000
321 #define RATE_MCS_ANT_POS 14
322 #define RATE_MCS_ANT_A_MSK 0x04000
323 #define RATE_MCS_ANT_B_MSK 0x08000
324 #define RATE_MCS_ANT_C_MSK 0x10000
325 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
326 #define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
327 #define RATE_ANT_NUM 3
329 #define POWER_TABLE_NUM_ENTRIES 33
330 #define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
331 #define POWER_TABLE_CCK_ENTRY 32
333 #define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
334 #define IWL_PWR_CCK_ENTRIES 2
351 #define IWLAGN_TX_POWER_AUTO 0x7f
352 #define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
377 #define UCODE_VALID_OK cpu_to_le32(0x1)
519 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
520 #define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
521 #define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
522 #define RXON_RX_CHAIN_VALID_POS (1)
523 #define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
524 #define RXON_RX_CHAIN_FORCE_SEL_POS (4)
525 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
526 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
527 #define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
528 #define RXON_RX_CHAIN_CNT_POS (10)
529 #define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
530 #define RXON_RX_CHAIN_MIMO_CNT_POS (12)
531 #define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
532 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
536 #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
537 #define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
539 #define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
541 #define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
543 #define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
544 #define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
546 #define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
547 #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
548 #define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
549 #define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
551 #define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
552 #define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
555 #define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
559 #define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
560 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
562 #define RXON_FLG_HT_OPERATING_MODE_POS (23)
564 #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
565 #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
567 #define RXON_FLG_CHANNEL_MODE_POS (25)
568 #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
577 #define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
578 #define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
579 #define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
582 #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
586 #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
588 #define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
590 #define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
592 #define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
594 #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
596 #define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
598 #define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
660 #define IWL_CONN_MAX_LISTEN_INTERVAL 10
661 #define IWL_MAX_UCODE_BEACON_INTERVAL 4
761 #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
762 #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
763 #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
790 #define IWL_AP_ID_PAN 1
792 #define IWLAGN_PAN_BCAST_ID 14
793 #define IWLAGN_BROADCAST_ID 15
794 #define IWLAGN_STATION_COUNT 16
796 #define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
798 #define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
799 #define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
800 #define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
801 #define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
802 #define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
803 #define STA_FLG_MAX_AGG_SIZE_POS (19)
804 #define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
805 #define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
806 #define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
807 #define STA_FLG_AGG_MPDU_DENSITY_POS (23)
808 #define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
811 #define STA_CONTROL_MODIFY_MSK 0x01
814 #define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
815 #define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
816 #define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
817 #define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
818 #define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
820 #define STA_KEY_FLG_KEYID_POS 8
821 #define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
823 #define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
826 #define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
827 #define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
828 #define STA_KEY_MAX_NUM 8
829 #define STA_KEY_MAX_NUM_PAN 16
831 #define IWLAGN_HW_KEY_DEFAULT 0xfe
834 #define STA_MODIFY_KEY_MASK 0x01
835 #define STA_MODIFY_TID_DISABLE_TX 0x02
836 #define STA_MODIFY_TX_RATE_MSK 0x04
837 #define STA_MODIFY_ADDBA_TID_MSK 0x08
838 #define STA_MODIFY_DELBA_TID_MSK 0x10
839 #define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
843 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
942 #define ADD_STA_SUCCESS_MSK 0x1
943 #define ADD_STA_NO_ROOM_IN_TABLE 0x2
944 #define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
945 #define ADD_STA_MODIFY_NON_EXIST_STA 0x8
953 #define REM_STA_SUCCESS_MSK 0x1
973 #define IWL_SCD_BK_MSK cpu_to_le32(BIT(0))
974 #define IWL_SCD_BE_MSK cpu_to_le32(BIT(1))
975 #define IWL_SCD_VI_MSK cpu_to_le32(BIT(2))
976 #define IWL_SCD_VO_MSK cpu_to_le32(BIT(3))
977 #define IWL_SCD_MGMT_MSK cpu_to_le32(BIT(3))
980 #define IWL_PAN_SCD_BK_MSK cpu_to_le32(BIT(4))
981 #define IWL_PAN_SCD_BE_MSK cpu_to_le32(BIT(5))
982 #define IWL_PAN_SCD_VI_MSK cpu_to_le32(BIT(6))
983 #define IWL_PAN_SCD_VO_MSK cpu_to_le32(BIT(7))
984 #define IWL_PAN_SCD_MGMT_MSK cpu_to_le32(BIT(7))
985 #define IWL_PAN_SCD_MULTICAST_MSK cpu_to_le32(BIT(8))
987 #define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
989 #define IWL_DROP_SINGLE 0
990 #define IWL_DROP_ALL (BIT(IWL_RXON_CTX_BSS) | BIT(IWL_RXON_CTX_PAN))
1039 #define WEP_KEY_WEP_TYPE 1
1040 #define WEP_KEYS_MAX 4
1041 #define WEP_INVALID_OFFSET 0xff
1042 #define WEP_KEY_LEN_64 5
1043 #define WEP_KEY_LEN_128 13
1051 #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1052 #define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1054 #define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1055 #define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1056 #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1057 #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1058 #define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1059 #define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1060 #define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1062 #define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1063 #define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1064 #define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1065 #define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1066 #define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1067 #define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1069 #define RX_RES_STATUS_STATION_FOUND (1<<6)
1070 #define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1072 #define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1073 #define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1074 #define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1075 #define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1076 #define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1078 #define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1079 #define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1080 #define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1081 #define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1084 #define IWLAGN_RX_RES_PHY_CNT 8
1085 #define IWLAGN_RX_RES_AGC_IDX 1
1086 #define IWLAGN_RX_RES_RSSI_AB_IDX 2
1087 #define IWLAGN_RX_RES_RSSI_C_IDX 3
1088 #define IWLAGN_OFDM_AGC_MSK 0xfe00
1089 #define IWLAGN_OFDM_AGC_BIT_POS 9
1090 #define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1091 #define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1092 #define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1093 #define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1094 #define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1095 #define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1096 #define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1097 #define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1098 #define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1161 #define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1166 #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1174 #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1178 #define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1181 #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1185 #define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1191 #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1195 #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1200 #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1208 #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1212 #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1215 #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1221 #define TX_CMD_SEC_WEP 0x01
1222 #define TX_CMD_SEC_CCM 0x02
1223 #define TX_CMD_SEC_TKIP 0x03
1224 #define TX_CMD_SEC_MSK 0x03
1225 #define TX_CMD_SEC_SHIFT 6
1226 #define TX_CMD_SEC_KEY128 0x08
1231 #define WEP_IV_LEN 4
1232 #define WEP_ICV_LEN 4
1233 #define CCMP_MIC_LEN 8
1234 #define TKIP_ICV_LEN 4
1366 #define TX_PACKET_MODE_REGULAR 0x0000
1367 #define TX_PACKET_MODE_BURST_SEQ 0x0100
1368 #define TX_PACKET_MODE_BURST_FIRST 0x0200
1405 #define AGG_TX_STATUS_MSK 0x00000fff
1406 #define AGG_TX_TRY_MSK 0x0000f000
1408 #define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1409 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1410 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1413 #define AGG_TX_STATE_TRY_CNT_POS 12
1414 #define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1417 #define AGG_TX_STATE_SEQ_NUM_POS 16
1418 #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1457 #define IWL50_TX_RES_INIT_RATE_INDEX_POS 0
1458 #define IWL50_TX_RES_INIT_RATE_INDEX_MSK 0x0f
1459 #define IWL50_TX_RES_RATE_TABLE_COLOR_POS 4
1460 #define IWL50_TX_RES_RATE_TABLE_COLOR_MSK 0x70
1461 #define IWL50_TX_RES_INV_RATE_INDEX_MSK 0x80
1464 #define IWLAGN_TX_RES_TID_POS 0
1465 #define IWLAGN_TX_RES_TID_MSK 0x0f
1466 #define IWLAGN_TX_RES_RA_POS 4
1467 #define IWLAGN_TX_RES_RA_MSK 0xf0
1537 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1540 #define LINK_QUAL_AC_NUM AC_NUM
1543 #define LINK_QUAL_MAX_RETRY_NUM 16
1546 #define LINK_QUAL_ANT_A_MSK (1 << 0)
1547 #define LINK_QUAL_ANT_B_MSK (1 << 1)
1548 #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1582 #define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1583 #define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1584 #define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1586 #define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1587 #define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1588 #define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1590 #define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1591 #define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1592 #define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1842 #define BT_COEX_DISABLE (0x0)
1843 #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1844 #define BT_ENABLE_PRIORITY BIT(1)
1845 #define BT_ENABLE_2_WIRE BIT(2)
1847 #define BT_COEX_DISABLE (0x0)
1848 #define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1850 #define BT_LEAD_TIME_MIN (0x0)
1851 #define BT_LEAD_TIME_DEF (0x1E)
1852 #define BT_LEAD_TIME_MAX (0xFF)
1854 #define BT_MAX_KILL_MIN (0x1)
1855 #define BT_MAX_KILL_DEF (0x5)
1856 #define BT_MAX_KILL_MAX (0xFF)
1858 #define BT_DURATION_LIMIT_DEF 625
1859 #define BT_DURATION_LIMIT_MAX 1250
1860 #define BT_DURATION_LIMIT_MIN 625
1862 #define BT_ON_THRESHOLD_DEF 4
1863 #define BT_ON_THRESHOLD_MAX 1000
1864 #define BT_ON_THRESHOLD_MIN 1
1866 #define BT_FRAG_THRESHOLD_DEF 0
1867 #define BT_FRAG_THRESHOLD_MAX 0
1868 #define BT_FRAG_THRESHOLD_MIN 0
1870 #define BT_AGG_THRESHOLD_DEF 1200
1871 #define BT_AGG_THRESHOLD_MAX 8000
1872 #define BT_AGG_THRESHOLD_MIN 400
1890 #define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1892 #define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1893 #define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1894 #define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1895 #define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1896 #define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1897 #define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1899 #define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1901 #define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1903 #define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1904 #define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1906 #define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1907 #define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1908 #define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1909 #define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1911 #define IWLAGN_BT_MAX_KILL_DEFAULT 5
1913 #define IWLAGN_BT3_T7_DEFAULT 1
1921 #define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1922 #define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1923 #define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1924 #define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1926 #define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1928 #define IWLAGN_BT3_T2_DEFAULT 0xc
1930 #define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1931 #define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1932 #define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1933 #define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1934 #define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1935 #define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1936 #define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1937 #define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1939 #define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1940 IWLAGN_BT_VALID_BOOST | \
1941 IWLAGN_BT_VALID_MAX_KILL | \
1942 IWLAGN_BT_VALID_3W_TIMERS | \
1943 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1944 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1945 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1946 IWLAGN_BT_VALID_3W_LUT)
1948 #define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1950 #define IWLAGN_BT_DECISION_LUT_SIZE 12
1995 #define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
2010 #define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
2011 RXON_FILTER_CTL2HOST_MSK | \
2012 RXON_FILTER_ACCEPT_GRP_MSK | \
2013 RXON_FILTER_DIS_DECRYPT_MSK | \
2014 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
2015 RXON_FILTER_ASSOC_MSK | \
2016 RXON_FILTER_BCON_AWARE_MSK)
2072 #define NUM_ELEMENTS_IN_HISTOGRAM 8
2162 #define IWL_POWER_VEC_SIZE 5
2164 #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2165 #define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2166 #define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2167 #define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2168 #define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2169 #define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2170 #define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2171 #define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2172 #define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2173 #define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2174 #define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2217 #define CARD_STATE_CMD_DISABLE 0x00
2218 #define CARD_STATE_CMD_ENABLE 0x01
2219 #define CARD_STATE_CMD_HALT 0x02
2231 #define HW_CARD_DISABLED 0x01
2232 #define SW_CARD_DISABLED 0x02
2233 #define CT_CARD_DISABLED 0x04
2234 #define RXON_CARD_DISABLED 0x10
2255 #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2256 #define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2295 #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2311 #define PROBE_OPTION_MAX 20
2312 #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2313 #define IWL_GOOD_CRC_TH_DISABLED 0
2314 #define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2315 #define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2316 #define IWL_MAX_CMD_SIZE 4096
2420 #define CAN_ABORT_STATUS cpu_to_le32(0x1)
2422 #define ABORT_STATUS 0x2
2444 #define SCAN_OWNER_STATUS 0x1
2445 #define MEASURE_OWNER_STATUS 0x2
2447 #define IWL_PROBE_STATUS_OK 0
2448 #define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2450 #define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2451 #define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2453 #define NUMBER_OF_STATISTICS 1
2520 #define IWL_TEMP_CONVERT 260
2522 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2523 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2524 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2585 #define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2747 #define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2748 #define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2749 #define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2766 #define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2767 #define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2787 #define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2788 #define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2824 #define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2825 #define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2826 #define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
3008 #define HD_TABLE_SIZE (11)
3009 #define HD_MIN_ENERGY_CCK_DET_INDEX (0)
3010 #define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
3011 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
3012 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
3013 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
3014 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
3015 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
3016 #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
3017 #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
3018 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
3019 #define HD_OFDM_ENERGY_TH_IN_INDEX (10)
3024 #define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
3025 #define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
3026 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
3027 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
3028 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
3029 #define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
3030 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
3031 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
3032 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
3033 #define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
3034 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
3035 #define HD_RESERVED (22)
3038 #define ENHANCE_HD_TABLE_SIZE (23)
3041 #define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
3043 #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3044 #define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3045 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3046 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3047 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3048 #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3049 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3050 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3051 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3052 #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3053 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3055 #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3056 #define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3057 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3058 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3059 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3060 #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3061 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3062 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3063 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3064 #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3065 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3069 #define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3070 #define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3176 #define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3177 IWL_CALIB_CFG_DC_IDX | \
3178 IWL_CALIB_CFG_LO_IDX | \
3179 IWL_CALIB_CFG_TX_IQ_IDX | \
3180 IWL_CALIB_CFG_RX_IQ_IDX | \
3181 IWL_CALIB_CFG_CRYSTAL_IDX)
3183 #define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3184 IWL_CALIB_CFG_DC_IDX | \
3185 IWL_CALIB_CFG_LO_IDX | \
3186 IWL_CALIB_CFG_TX_IQ_IDX | \
3187 IWL_CALIB_CFG_RX_IQ_IDX | \
3188 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3189 IWL_CALIB_CFG_PAPD_IDX | \
3190 IWL_CALIB_CFG_TX_PWR_IDX | \
3191 IWL_CALIB_CFG_CRYSTAL_IDX)
3193 #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3234 #define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3297 #define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3298 #define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3299 #define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3301 #define COEX_CU_UNASSOC_IDLE_RP 4
3302 #define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3303 #define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3304 #define COEX_CU_CALIBRATION_RP 4
3305 #define COEX_CU_PERIODIC_CALIBRATION_RP 4
3306 #define COEX_CU_CONNECTION_ESTAB_RP 4
3307 #define COEX_CU_ASSOCIATED_IDLE_RP 4
3308 #define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3309 #define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3310 #define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3311 #define COEX_CU_RF_ON_RP 6
3312 #define COEX_CU_RF_OFF_RP 4
3313 #define COEX_CU_STAND_ALONE_DEBUG_RP 6
3314 #define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3315 #define COEX_CU_RSRVD1_RP 4
3316 #define COEX_CU_RSRVD2_RP 4
3318 #define COEX_CU_UNASSOC_IDLE_WP 3
3319 #define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3320 #define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3321 #define COEX_CU_CALIBRATION_WP 3
3322 #define COEX_CU_PERIODIC_CALIBRATION_WP 3
3323 #define COEX_CU_CONNECTION_ESTAB_WP 3
3324 #define COEX_CU_ASSOCIATED_IDLE_WP 3
3325 #define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3326 #define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3327 #define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3328 #define COEX_CU_RF_ON_WP 3
3329 #define COEX_CU_RF_OFF_WP 3
3330 #define COEX_CU_STAND_ALONE_DEBUG_WP 6
3331 #define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3332 #define COEX_CU_RSRVD1_WP 3
3333 #define COEX_CU_RSRVD2_WP 3
3335 #define COEX_UNASSOC_IDLE_FLAGS 0
3336 #define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3337 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3338 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3339 #define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3340 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3341 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3342 #define COEX_CALIBRATION_FLAGS \
3343 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3344 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3345 #define COEX_PERIODIC_CALIBRATION_FLAGS 0
3350 #define COEX_CONNECTION_ESTAB_FLAGS \
3351 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3352 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3353 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3354 #define COEX_ASSOCIATED_IDLE_FLAGS 0
3355 #define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3356 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3357 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3358 #define COEX_ASSOC_AUTO_SCAN_FLAGS \
3359 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3360 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3361 #define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3362 #define COEX_RF_ON_FLAGS 0
3363 #define COEX_RF_OFF_FLAGS 0
3364 #define COEX_STAND_ALONE_DEBUG_FLAGS \
3365 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3366 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3367 #define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3368 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3369 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3370 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3371 #define COEX_RSRVD1_FLAGS 0
3372 #define COEX_RSRVD2_FLAGS 0
3377 #define COEX_CU_RF_ON_FLAGS \
3378 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3379 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3380 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3425 #define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3427 #define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3429 #define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3431 #define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3453 #define COEX_MEDIUM_BUSY (0x0)
3454 #define COEX_MEDIUM_ACTIVE (0x1)
3455 #define COEX_MEDIUM_PRE_RELEASE (0x2)
3456 #define COEX_MEDIUM_MSK (0x7)
3459 #define COEX_MEDIUM_CHANGED (0x8)
3460 #define COEX_MEDIUM_CHANGED_MSK (0x8)
3461 #define COEX_MEDIUM_SHIFT (3)
3475 #define COEX_EVENT_REQUEST_MSK (0x1)
3508 #define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3509 #define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3512 #define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3513 #define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3514 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3515 #define BT_UART_MSG_FRAME1SSN_POS (3)
3516 #define BT_UART_MSG_FRAME1SSN_MSK \
3517 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3518 #define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3519 #define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3520 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3521 #define BT_UART_MSG_FRAME1RESERVED_POS (6)
3522 #define BT_UART_MSG_FRAME1RESERVED_MSK \
3523 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3525 #define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3526 #define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3527 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3528 #define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3529 #define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3530 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3531 #define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3532 #define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3533 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3534 #define BT_UART_MSG_FRAME2INBAND_POS (5)
3535 #define BT_UART_MSG_FRAME2INBAND_MSK \
3536 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3537 #define BT_UART_MSG_FRAME2RESERVED_POS (6)
3538 #define BT_UART_MSG_FRAME2RESERVED_MSK \
3539 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3541 #define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3542 #define BT_UART_MSG_FRAME3SCOESCO_MSK \
3543 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3544 #define BT_UART_MSG_FRAME3SNIFF_POS (1)
3545 #define BT_UART_MSG_FRAME3SNIFF_MSK \
3546 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3547 #define BT_UART_MSG_FRAME3A2DP_POS (2)
3548 #define BT_UART_MSG_FRAME3A2DP_MSK \
3549 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3550 #define BT_UART_MSG_FRAME3ACL_POS (3)
3551 #define BT_UART_MSG_FRAME3ACL_MSK \
3552 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3553 #define BT_UART_MSG_FRAME3MASTER_POS (4)
3554 #define BT_UART_MSG_FRAME3MASTER_MSK \
3555 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3556 #define BT_UART_MSG_FRAME3OBEX_POS (5)
3557 #define BT_UART_MSG_FRAME3OBEX_MSK \
3558 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3559 #define BT_UART_MSG_FRAME3RESERVED_POS (6)
3560 #define BT_UART_MSG_FRAME3RESERVED_MSK \
3561 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3563 #define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3564 #define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3565 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3566 #define BT_UART_MSG_FRAME4RESERVED_POS (6)
3567 #define BT_UART_MSG_FRAME4RESERVED_MSK \
3568 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3570 #define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3571 #define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3572 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3573 #define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3574 #define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3575 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3576 #define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3577 #define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3578 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3579 #define BT_UART_MSG_FRAME5RESERVED_POS (6)
3580 #define BT_UART_MSG_FRAME5RESERVED_MSK \
3581 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3583 #define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3584 #define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3585 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3586 #define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3587 #define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3588 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3589 #define BT_UART_MSG_FRAME6RESERVED_POS (6)
3590 #define BT_UART_MSG_FRAME6RESERVED_MSK \
3591 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3593 #define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3594 #define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3595 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3596 #define BT_UART_MSG_FRAME7PAGE_POS (3)
3597 #define BT_UART_MSG_FRAME7PAGE_MSK \
3598 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3599 #define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3600 #define BT_UART_MSG_FRAME7INQUIRY_MSK \
3601 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3602 #define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3603 #define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3604 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3605 #define BT_UART_MSG_FRAME7RESERVED_POS (6)
3606 #define BT_UART_MSG_FRAME7RESERVED_MSK \
3607 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3610 #define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3611 #define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3612 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3613 #define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3614 #define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3615 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3617 #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3618 #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3619 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3620 #define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3621 #define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3622 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3624 #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3625 #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3626 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3627 #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3628 #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3629 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3630 #define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3631 #define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3632 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3633 #define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3634 #define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3635 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3637 #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3638 #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3639 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3640 #define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3641 #define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3642 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3643 #define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3644 #define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3645 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3647 #define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3648 #define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3649 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3650 #define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3651 #define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3652 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3653 #define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3654 #define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3655 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3656 #define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3657 #define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3658 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3660 #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3661 #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3662 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3663 #define BT_UART_MSG_2_FRAME6RFU_POS (5)
3664 #define BT_UART_MSG_2_FRAME6RFU_MSK \
3665 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3666 #define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3667 #define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3668 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3670 #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3671 #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3672 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3673 #define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3674 #define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3675 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3676 #define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3677 #define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3678 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3679 #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3680 #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3681 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3682 #define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3683 #define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3684 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3687 #define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3688 #define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3709 #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3710 #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3711 #define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3712 #define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3713 #define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3714 #define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3715 #define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3758 #define IWL_BT_COEX_ENV_CLOSE 0
3759 #define IWL_BT_COEX_ENV_OPEN 1
3786 #define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3787 #define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3797 #define IWLAGN_WOWLAN_MAX_PATTERNS 20
3829 #define IWLAGN_NUM_RSC 16
3865 #define IWLAGN_MIC_KEY_SIZE 8
3866 #define IWLAGN_P1K_SIZE 5
3877 #define IWLAGN_NUM_RX_P1K_CACHE 2
3890 #define IWLAGN_KCK_MAX_SIZE 32
3891 #define IWLAGN_KEK_MAX_SIZE 32
3908 #define IWL_MIN_SLOT_TIME 20
3923 #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3924 #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3925 #define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3926 #define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3927 #define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)