33 #define lg_printk(kern, fmt, arg...) \
34 printk(kern "%s: " fmt, __func__, ##arg)
36 #define lg_info(fmt, arg...) printk(KERN_INFO "lg2160: " fmt, ##arg)
37 #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
38 #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
39 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
40 lg_printk(KERN_DEBUG, fmt, ##arg)
41 #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
42 lg_printk(KERN_DEBUG, fmt, ##arg)
44 #define lg_fail(ret) \
49 lg_err("error %d on line %d\n", ret, __LINE__); \
70 u8 buf[] = { reg >> 8, reg & 0xff, val };
72 .addr = state->
cfg->i2c_addr, .flags = 0,
76 lg_reg(
"reg: 0x%04x, val: 0x%02x\n", reg, val);
81 lg_err(
"error (addr %02x %02x <- %02x, err = %i)\n",
94 u8 reg_buf[] = { reg >> 8, reg & 0xff };
97 .flags = 0, .buf = reg_buf, .len = 2 },
98 { .addr = state->
cfg->i2c_addr,
102 lg_reg(
"reg: 0x%04x\n", reg);
107 lg_err(
"error (addr %02x reg %04x error (ret == %i)\n",
108 state->
cfg->i2c_addr, reg, ret);
122 static int lg216x_write_regs(
struct lg216x_state *state,
127 lg_reg(
"writing %d registers...\n", len);
129 for (i = 0; i < len; i++) {
130 ret = lg216x_write_reg(state, regs[i].reg, regs[i].val);
137 static int lg216x_set_reg_bit(
struct lg216x_state *state,
143 lg_reg(
"reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
145 ret = lg216x_read_reg(state, reg, &val);
150 val |= (onoff & 1) << bit;
152 ret = lg216x_write_reg(state, reg, val);
165 if (state->
cfg->deny_i2c_rptr)
170 ret = lg216x_set_reg_bit(state, 0x0000, 0, enable ? 0 : 1);
177 static int lg216x_soft_reset(
struct lg216x_state *state)
183 ret = lg216x_write_reg(state, 0x0002, 0x00);
188 ret = lg216x_write_reg(state, 0x0002, 0x01);
197 static int lg216x_initialize(
struct lg216x_state *state)
203 { .
reg = 0x0015, .val = 0xe6 },
205 { .reg = 0x0015, .val = 0xf7 },
206 { .reg = 0x001b, .val = 0x52 },
207 { .reg = 0x0208, .val = 0x00 },
208 { .reg = 0x0209, .val = 0x82 },
209 { .reg = 0x0210, .val = 0xf9 },
210 { .reg = 0x020a, .val = 0x00 },
211 { .reg = 0x020b, .val = 0x82 },
212 { .reg = 0x020d, .val = 0x28 },
213 { .reg = 0x020f, .val = 0x14 },
218 { .
reg = 0x0000, .val = 0x41 },
219 { .reg = 0x0001, .val = 0xfb },
220 { .reg = 0x0216, .val = 0x00 },
221 { .reg = 0x0219, .val = 0x00 },
222 { .reg = 0x021b, .val = 0x55 },
223 { .reg = 0x0606, .val = 0x0a },
226 switch (state->
cfg->lg_chip) {
228 ret = lg216x_write_regs(state,
232 ret = lg216x_write_regs(state,
242 ret = lg216x_soft_reset(state);
257 ret = lg216x_read_reg(state, 0x0132, &val);
262 val |= (0 == state->
cfg->if_khz) ? 0x04 : 0x00;
264 ret = lg216x_write_reg(state, 0x0132, val);
275 int if_agc_fix,
int rf_agc_fix)
280 ret = lg216x_read_reg(state, 0x0100, &val);
285 val |= (if_agc_fix) ? 0x08 : 0x00;
286 val |= (rf_agc_fix) ? 0x04 : 0x00;
288 ret = lg216x_write_reg(state, 0x0100, val);
295 static int lg2160_agc_freeze(
struct lg216x_state *state,
296 int if_agc_freeze,
int rf_agc_freeze)
301 ret = lg216x_read_reg(state, 0x0100, &val);
306 val |= (if_agc_freeze) ? 0x20 : 0x00;
307 val |= (rf_agc_freeze) ? 0x10 : 0x00;
309 ret = lg216x_write_reg(state, 0x0100, val);
316 static int lg2160_agc_polarity(
struct lg216x_state *state,
317 int if_agc_polarity,
int rf_agc_polarity)
322 ret = lg216x_read_reg(state, 0x0100, &val);
327 val |= (if_agc_polarity) ? 0x02 : 0x00;
328 val |= (rf_agc_polarity) ? 0x01 : 0x00;
330 ret = lg216x_write_reg(state, 0x0100, val);
336 static int lg2160_tuner_pwr_save_polarity(
struct lg216x_state *state,
342 ret = lg216x_read_reg(state, 0x0008, &val);
349 ret = lg216x_write_reg(state, 0x0008, val);
355 static int lg2160_spectrum_polarity(
struct lg216x_state *state,
361 ret = lg216x_read_reg(state, 0x0132, &val);
366 val |= (inverted) ? 0x02 : 0x00;
368 ret = lg216x_write_reg(state, 0x0132, val);
371 return lg216x_soft_reset(state);
374 static int lg2160_tuner_pwr_save(
struct lg216x_state *state,
int onoff)
379 ret = lg216x_read_reg(state, 0x0007, &val);
384 val |= (
onoff) ? 0x40 : 0x00;
386 ret = lg216x_write_reg(state, 0x0007, val);
392 static int lg216x_set_parade(
struct lg216x_state *state,
int id)
396 ret = lg216x_write_reg(state, 0x013e,
id & 0x7f);
405 static int lg216x_set_ensemble(
struct lg216x_state *state,
int id)
411 switch (state->
cfg->lg_chip) {
421 ret = lg216x_read_reg(state, reg, &val);
426 val |= (
id) ? 0x01 : 0x00;
428 ret = lg216x_write_reg(state, reg, val);
434 static int lg2160_set_spi_clock(
struct lg216x_state *state)
439 ret = lg216x_read_reg(state, 0x0014, &val);
444 val |= (state->
cfg->spi_clock << 2);
446 ret = lg216x_write_reg(state, 0x0014, val);
452 static int lg2161_set_output_interface(
struct lg216x_state *state)
457 ret = lg216x_read_reg(state, 0x0014, &val);
462 val |= state->
cfg->output_if;
464 ret = lg216x_write_reg(state, 0x0014, val);
470 static int lg216x_enable_fic(
struct lg216x_state *state,
int onoff)
474 ret = lg216x_write_reg(state, 0x0017, 0x23);
478 ret = lg216x_write_reg(state, 0x0016, 0xfc);
482 switch (state->
cfg->lg_chip) {
484 ret = lg216x_write_reg(state, 0x0016,
485 0xfc | ((onoff) ? 0x02 : 0x00));
488 ret = lg216x_write_reg(state, 0x0016, (onoff) ? 0x10 : 0x00);
494 ret = lg216x_initialize(state);
499 ret = lg216x_write_reg(state, 0x0017, 0x03);
508 static int lg216x_get_fic_version(
struct lg216x_state *state,
u8 *ficver)
515 ret = lg216x_read_reg(state, 0x0128, &val);
519 *ficver = (val >> 3) & 0x1f;
525 static int lg2160_get_parade_id(
struct lg216x_state *state,
u8 *
id)
532 ret = lg216x_read_reg(state, 0x0123, &val);
549 ret = lg216x_read_reg(state, 0x0124, &val);
553 *nog = ((val >> 4) & 0x07) + 1;
565 ret = lg216x_read_reg(state, 0x0125, &val);
581 ret = lg216x_read_reg(state, 0x0124, &val);
597 ret = lg216x_read_reg(state, 0x0125, &val);
601 *prc = ((val >> 5) & 0x07) + 1;
608 static int lg216x_get_rs_frame_mode(
struct lg216x_state *state,
614 switch (state->
cfg->lg_chip) {
616 ret = lg216x_read_reg(state, 0x0410, &val);
619 ret = lg216x_read_reg(state, 0x0513, &val);
627 switch ((val >> 4) & 0x03) {
648 int lg216x_get_rs_frame_ensemble(
struct lg216x_state *state,
654 switch (state->
cfg->lg_chip) {
656 ret = lg216x_read_reg(state, 0x0400, &val);
659 ret = lg216x_read_reg(state, 0x0500, &val);
673 static int lg216x_get_rs_code_mode(
struct lg216x_state *state,
680 switch (state->
cfg->lg_chip) {
682 ret = lg216x_read_reg(state, 0x0410, &val);
685 ret = lg216x_read_reg(state, 0x0513, &val);
699 static int lg216x_get_sccc_block_mode(
struct lg216x_state *state,
705 switch (state->
cfg->lg_chip) {
707 ret = lg216x_read_reg(state, 0x0315, &val);
710 ret = lg216x_read_reg(state, 0x0511, &val);
718 switch (val & 0x03) {
733 static int lg216x_get_sccc_code_mode(
struct lg216x_state *state,
742 switch (state->
cfg->lg_chip) {
744 ret = lg216x_read_reg(state, 0x0316, &val);
747 ret = lg216x_read_reg(state, 0x0512, &val);
755 switch ((val >> 6) & 0x03) {
767 switch ((val >> 4) & 0x03) {
779 switch ((val >> 2) & 0x03) {
791 switch (val & 0x03) {
816 switch (state->
cfg->lg_chip) {
818 ret = lg216x_read_reg(state, 0x0012, &fic_err);
821 ret = lg216x_read_reg(state, 0x001e, &fic_err);
832 static int lg2160_read_crc_err_count(
struct lg216x_state *state,
u16 *err)
834 u8 crc_err1, crc_err2;
839 ret = lg216x_read_reg(state, 0x0411, &crc_err1);
843 ret = lg216x_read_reg(state, 0x0412, &crc_err2);
847 *err = (
u16)(((crc_err2 & 0x0f) << 8) | crc_err1);
852 static int lg2161_read_crc_err_count(
struct lg216x_state *state,
u16 *err)
859 ret = lg216x_read_reg(state, 0x0612, &crc_err);
868 static int lg216x_read_crc_err_count(
struct lg216x_state *state,
u16 *err)
871 switch (state->
cfg->lg_chip) {
873 ret = lg2160_read_crc_err_count(state, err);
876 ret = lg2161_read_crc_err_count(state, err);
885 static int lg2160_read_rs_err_count(
struct lg216x_state *state,
u16 *err)
892 ret = lg216x_read_reg(state, 0x0413, &rs_err1);
896 ret = lg216x_read_reg(state, 0x0414, &rs_err2);
900 *err = (
u16)(((rs_err2 & 0x0f) << 8) | rs_err1);
905 static int lg2161_read_rs_err_count(
struct lg216x_state *state,
u16 *err)
912 ret = lg216x_read_reg(state, 0x0613, &rs_err1);
916 ret = lg216x_read_reg(state, 0x0614, &rs_err2);
920 *err = (
u16)((rs_err1 << 8) | rs_err2);
925 static int lg216x_read_rs_err_count(
struct lg216x_state *state,
u16 *err)
928 switch (state->
cfg->lg_chip) {
930 ret = lg2160_read_rs_err_count(state, err);
933 ret = lg2161_read_rs_err_count(state, err);
956 ret = lg216x_get_fic_version(state,
964 ret = lg2160_get_parade_id(state,
971 ret = lg216x_get_nog(state,
975 ret = lg216x_get_tnog(state,
979 ret = lg216x_get_sgn(state,
983 ret = lg216x_get_prc(state,
988 ret = lg216x_get_rs_frame_mode(state,
993 ret = lg216x_get_rs_frame_ensemble(state,
998 ret = lg216x_get_rs_code_mode(state,
1005 ret = lg216x_get_sccc_block_mode(state,
1010 ret = lg216x_get_sccc_code_mode(state,
1023 ret = lg216x_read_fic_err_count(state,
1027 ret = lg216x_read_crc_err_count(state,
1031 ret = lg216x_read_rs_err_count(state,
1036 switch (state->
cfg->lg_chip) {
1041 ret = lg216x_soft_reset(state);
1054 static int lg216x_get_property(
struct dvb_frontend *fe,
1058 lg216x_get_frontend(fe) : 0;
1062 static int lg2160_set_frontend(
struct dvb_frontend *fe)
1069 if (fe->
ops.tuner_ops.set_params) {
1070 ret = fe->
ops.tuner_ops.set_params(fe);
1071 if (fe->
ops.i2c_gate_ctrl)
1072 fe->
ops.i2c_gate_ctrl(fe, 0);
1078 ret = lg2160_agc_fix(state, 0, 0);
1081 ret = lg2160_agc_polarity(state, 0, 0);
1084 ret = lg2160_tuner_pwr_save_polarity(state, 1);
1087 ret = lg216x_set_if(state);
1090 ret = lg2160_spectrum_polarity(state, state->
cfg->spectral_inversion);
1095 ret = lg216x_soft_reset(state);
1099 ret = lg2160_tuner_pwr_save(state, 0);
1103 switch (state->
cfg->lg_chip) {
1105 ret = lg2160_set_spi_clock(state);
1110 ret = lg2161_set_output_interface(state);
1120 ret = lg216x_set_ensemble(state,
1125 ret = lg216x_initialize(state);
1129 ret = lg216x_enable_fic(state, 1);
1132 lg216x_get_frontend(fe);
1139 static int lg2160_read_lock_status(
struct lg216x_state *state,
1140 int *acq_lock,
int *sync_lock)
1148 ret = lg216x_read_reg(state, 0x011b, &val);
1152 *sync_lock = (val & 0x20) ? 0 : 1;
1153 *acq_lock = (val & 0x40) ? 0 : 1;
1158 #ifdef USE_LG2161_LOCK_BITS
1159 static int lg2161_read_lock_status(
struct lg216x_state *state,
1160 int *acq_lock,
int *sync_lock)
1168 ret = lg216x_read_reg(state, 0x0304, &val);
1172 *sync_lock = (val & 0x80) ? 0 : 1;
1174 ret = lg216x_read_reg(state, 0x011b, &val);
1178 *acq_lock = (val & 0x40) ? 0 : 1;
1184 static int lg216x_read_lock_status(
struct lg216x_state *state,
1185 int *acq_lock,
int *sync_lock)
1187 #ifdef USE_LG2161_LOCK_BITS
1189 switch (state->
cfg->lg_chip) {
1191 ret = lg2160_read_lock_status(state, acq_lock, sync_lock);
1194 ret = lg2161_read_lock_status(state, acq_lock, sync_lock);
1202 return lg2160_read_lock_status(state, acq_lock, sync_lock);
1209 int ret, acq_lock, sync_lock;
1213 ret = lg216x_read_lock_status(state, &acq_lock, &sync_lock);
1218 acq_lock ?
"SIGNALEXIST " :
"",
1219 sync_lock ?
"SYNCLOCK" :
"");
1243 ret = lg216x_read_reg(state, 0x0202, &snr1);
1247 ret = lg216x_read_reg(state, 0x0203, &snr2);
1251 if ((snr1 == 0xba) || (snr2 == 0xdf))
1255 *snr = ((snr1 >> 4) * 100) + ((snr1 & 0x0f) * 10) + (snr2 >> 4);
1257 *snr = (snr2 | (snr1 << 8));
1271 ret = lg216x_read_reg(state, 0x0302, &snr1);
1275 ret = lg216x_read_reg(state, 0x0303, &snr2);
1279 if ((snr1 == 0xba) || (snr2 == 0xfd))
1283 *snr = ((snr1 >> 4) * 100) + ((snr1 & 0x0f) * 10) + (snr2 & 0x0f);
1288 static int lg216x_read_signal_strength(
struct dvb_frontend *fe,
1305 ret = fe->
ops.read_snr(fe, &snr);
1310 if (state->snr >= 8960 * 0x10000)
1313 *strength = state->snr / 8960;
1323 static int lg216x_read_ucblocks(
struct dvb_frontend *fe,
u32 *ucblocks)
1329 ret = lg216x_read_rs_err_count(state,
1342 static int lg216x_get_tune_settings(
struct dvb_frontend *fe,
1361 .name =
"LG Electronics LG2160 ATSC/MH Frontend",
1362 .frequency_min = 54000000,
1363 .frequency_max = 858000000,
1364 .frequency_stepsize = 62500,
1366 .i2c_gate_ctrl = lg216x_i2c_gate_ctrl,
1368 .init = lg216x_init,
1369 .sleep = lg216x_sleep,
1371 .get_property = lg216x_get_property,
1373 .set_frontend = lg2160_set_frontend,
1374 .get_frontend = lg216x_get_frontend,
1375 .get_tune_settings = lg216x_get_tune_settings,
1376 .read_status = lg216x_read_status,
1378 .read_ber = lg216x_read_ber,
1380 .read_signal_strength = lg216x_read_signal_strength,
1381 .read_snr = lg2160_read_snr,
1382 .read_ucblocks = lg216x_read_ucblocks,
1383 .release = lg216x_release,
1389 .name =
"LG Electronics LG2161 ATSC/MH Frontend",
1390 .frequency_min = 54000000,
1391 .frequency_max = 858000000,
1392 .frequency_stepsize = 62500,
1394 .i2c_gate_ctrl = lg216x_i2c_gate_ctrl,
1396 .init = lg216x_init,
1397 .sleep = lg216x_sleep,
1399 .get_property = lg216x_get_property,
1401 .set_frontend = lg2160_set_frontend,
1402 .get_frontend = lg216x_get_frontend,
1403 .get_tune_settings = lg216x_get_tune_settings,
1404 .read_status = lg216x_read_status,
1406 .read_ber = lg216x_read_ber,
1408 .read_signal_strength = lg216x_read_signal_strength,
1409 .read_snr = lg2161_read_snr,
1410 .read_ucblocks = lg216x_read_ucblocks,
1411 .release = lg216x_release,
1420 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1434 lg_warn(
"invalid chip requested, defaulting to LG2160");
1449 state->
frontend.dtv_property_cache.atscmh_parade_id = 1;