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Macros
m32r_sio_reg.h File Reference

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Macros

#define SIOCR   0x000
 
#define SIOMOD0   0x004
 
#define SIOMOD1   0x008
 
#define SIOSTS   0x00c
 
#define SIOTRCR   0x010
 
#define SIOBAUR   0x014
 
#define SIORBAUR   0x018
 
#define SIOTXB   0x01c
 
#define SIORXB   0x020
 
#define UART_RX   M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
 
#define UART_TX   M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
 
#define UART_DLL   0 /* Out: Divisor Latch Low (DLAB=1) */
 
#define UART_TRG
 
#define UART_DLM   0 /* Out: Divisor Latch High (DLAB=1) */
 
#define UART_IER   M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
 
#define UART_FCTR
 
#define UART_IIR   0 /* In: Interrupt ID Register */
 
#define UART_FCR   0 /* Out: FIFO Control Register */
 
#define UART_EFR   0 /* I/O: Extended Features Register */
 
#define UART_LCR   0 /* Out: Line Control Register */
 
#define UART_MCR   0 /* Out: Modem Control Register */
 
#define UART_LSR   M32R_SIO0_STS_PORTL /* In: Line Status Register */
 
#define UART_MSR   0 /* In: Modem Status Register */
 
#define UART_SCR   0 /* I/O: Scratch Register */
 
#define UART_EMSR
 
#define UART_EMPTY   (UART_LSR_TEMT | UART_LSR_THRE)
 
#define UART_LCR_DLAB   0x80 /* Divisor latch access bit */
 
#define UART_LCR_SBC   0x40 /* Set break control */
 
#define UART_LCR_SPAR   0x20 /* Stick parity (?) */
 
#define UART_LCR_EPAR   0x10 /* Even parity select */
 
#define UART_LCR_PARITY   0x08 /* Parity Enable */
 
#define UART_LCR_STOP   0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
 
#define UART_LCR_WLEN5   0x00 /* Wordlength: 5 bits */
 
#define UART_LCR_WLEN6   0x01 /* Wordlength: 6 bits */
 
#define UART_LCR_WLEN7   0x02 /* Wordlength: 7 bits */
 
#define UART_LCR_WLEN8   0x03 /* Wordlength: 8 bits */
 
#define UART_LSR_TEMT   0x02 /* Transmitter empty */
 
#define UART_LSR_THRE   0x01 /* Transmit-hold-register empty */
 
#define UART_LSR_BI   0x00 /* Break interrupt indicator */
 
#define UART_LSR_FE   0x80 /* Frame error indicator */
 
#define UART_LSR_PE   0x40 /* Parity error indicator */
 
#define UART_LSR_OE   0x20 /* Overrun error indicator */
 
#define UART_LSR_DR   0x04 /* Receiver data ready */
 
#define UART_IIR_NO_INT   0x01 /* No interrupts pending */
 
#define UART_IIR_ID   0x06 /* Mask for the interrupt ID */
 
#define UART_IIR_MSI   0x00 /* Modem status interrupt */
 
#define UART_IIR_THRI   0x02 /* Transmitter holding register empty */
 
#define UART_IIR_RDI   0x04 /* Receiver data interrupt */
 
#define UART_IIR_RLSI   0x06 /* Receiver line status interrupt */
 
#define UART_IER_MSI   0x00 /* Enable Modem status interrupt */
 
#define UART_IER_RLSI   0x08 /* Enable receiver line status interrupt */
 
#define UART_IER_THRI   0x03 /* Enable Transmitter holding register int. */
 
#define UART_IER_RDI   0x04 /* Enable receiver data interrupt */
 

Macro Definition Documentation

#define SIOBAUR   0x014

Definition at line 69 of file m32r_sio_reg.h.

#define SIOCR   0x000

Definition at line 64 of file m32r_sio_reg.h.

#define SIOMOD0   0x004

Definition at line 65 of file m32r_sio_reg.h.

#define SIOMOD1   0x008

Definition at line 66 of file m32r_sio_reg.h.

#define SIORBAUR   0x018

Definition at line 70 of file m32r_sio_reg.h.

#define SIORXB   0x020

Definition at line 72 of file m32r_sio_reg.h.

#define SIOSTS   0x00c

Definition at line 67 of file m32r_sio_reg.h.

#define SIOTRCR   0x010

Definition at line 68 of file m32r_sio_reg.h.

#define SIOTXB   0x01c

Definition at line 71 of file m32r_sio_reg.h.

#define UART_DLL   0 /* Out: Divisor Latch Low (DLAB=1) */

Definition at line 76 of file m32r_sio_reg.h.

#define UART_DLM   0 /* Out: Divisor Latch High (DLAB=1) */

Definition at line 79 of file m32r_sio_reg.h.

#define UART_EFR   0 /* I/O: Extended Features Register */

Definition at line 85 of file m32r_sio_reg.h.

#define UART_EMPTY   (UART_LSR_TEMT | UART_LSR_THRE)

Definition at line 97 of file m32r_sio_reg.h.

#define UART_EMSR
Value:
0 /* (LCR=BF) Extended Mode Select Register
* FCTR bit 6 selects SCR or EMSR
* XR16c85x only */

Definition at line 93 of file m32r_sio_reg.h.

#define UART_FCR   0 /* Out: FIFO Control Register */

Definition at line 84 of file m32r_sio_reg.h.

#define UART_FCTR
Value:
0 /* (LCR=BF) Feature Control Register
* XR16C85x only */

Definition at line 81 of file m32r_sio_reg.h.

#define UART_IER   M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */

Definition at line 80 of file m32r_sio_reg.h.

#define UART_IER_MSI   0x00 /* Enable Modem status interrupt */

Definition at line 141 of file m32r_sio_reg.h.

#define UART_IER_RDI   0x04 /* Enable receiver data interrupt */

Definition at line 144 of file m32r_sio_reg.h.

#define UART_IER_RLSI   0x08 /* Enable receiver line status interrupt */

Definition at line 142 of file m32r_sio_reg.h.

#define UART_IER_THRI   0x03 /* Enable Transmitter holding register int. */

Definition at line 143 of file m32r_sio_reg.h.

#define UART_IIR   0 /* In: Interrupt ID Register */

Definition at line 83 of file m32r_sio_reg.h.

#define UART_IIR_ID   0x06 /* Mask for the interrupt ID */

Definition at line 131 of file m32r_sio_reg.h.

#define UART_IIR_MSI   0x00 /* Modem status interrupt */

Definition at line 133 of file m32r_sio_reg.h.

#define UART_IIR_NO_INT   0x01 /* No interrupts pending */

Definition at line 130 of file m32r_sio_reg.h.

#define UART_IIR_RDI   0x04 /* Receiver data interrupt */

Definition at line 135 of file m32r_sio_reg.h.

#define UART_IIR_RLSI   0x06 /* Receiver line status interrupt */

Definition at line 136 of file m32r_sio_reg.h.

#define UART_IIR_THRI   0x02 /* Transmitter holding register empty */

Definition at line 134 of file m32r_sio_reg.h.

#define UART_LCR   0 /* Out: Line Control Register */

Definition at line 88 of file m32r_sio_reg.h.

#define UART_LCR_DLAB   0x80 /* Divisor latch access bit */

Definition at line 105 of file m32r_sio_reg.h.

#define UART_LCR_EPAR   0x10 /* Even parity select */

Definition at line 108 of file m32r_sio_reg.h.

#define UART_LCR_PARITY   0x08 /* Parity Enable */

Definition at line 109 of file m32r_sio_reg.h.

#define UART_LCR_SBC   0x40 /* Set break control */

Definition at line 106 of file m32r_sio_reg.h.

#define UART_LCR_SPAR   0x20 /* Stick parity (?) */

Definition at line 107 of file m32r_sio_reg.h.

#define UART_LCR_STOP   0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */

Definition at line 110 of file m32r_sio_reg.h.

#define UART_LCR_WLEN5   0x00 /* Wordlength: 5 bits */

Definition at line 111 of file m32r_sio_reg.h.

#define UART_LCR_WLEN6   0x01 /* Wordlength: 6 bits */

Definition at line 112 of file m32r_sio_reg.h.

#define UART_LCR_WLEN7   0x02 /* Wordlength: 7 bits */

Definition at line 113 of file m32r_sio_reg.h.

#define UART_LCR_WLEN8   0x03 /* Wordlength: 8 bits */

Definition at line 114 of file m32r_sio_reg.h.

#define UART_LSR   M32R_SIO0_STS_PORTL /* In: Line Status Register */

Definition at line 90 of file m32r_sio_reg.h.

#define UART_LSR_BI   0x00 /* Break interrupt indicator */

Definition at line 121 of file m32r_sio_reg.h.

#define UART_LSR_DR   0x04 /* Receiver data ready */

Definition at line 125 of file m32r_sio_reg.h.

#define UART_LSR_FE   0x80 /* Frame error indicator */

Definition at line 122 of file m32r_sio_reg.h.

#define UART_LSR_OE   0x20 /* Overrun error indicator */

Definition at line 124 of file m32r_sio_reg.h.

#define UART_LSR_PE   0x40 /* Parity error indicator */

Definition at line 123 of file m32r_sio_reg.h.

#define UART_LSR_TEMT   0x02 /* Transmitter empty */

Definition at line 119 of file m32r_sio_reg.h.

#define UART_LSR_THRE   0x01 /* Transmit-hold-register empty */

Definition at line 120 of file m32r_sio_reg.h.

#define UART_MCR   0 /* Out: Modem Control Register */

Definition at line 89 of file m32r_sio_reg.h.

#define UART_MSR   0 /* In: Modem Status Register */

Definition at line 91 of file m32r_sio_reg.h.

#define UART_RX   M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */

Definition at line 74 of file m32r_sio_reg.h.

#define UART_SCR   0 /* I/O: Scratch Register */

Definition at line 92 of file m32r_sio_reg.h.

#define UART_TRG
Value:
0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
* In: Fifo count
* Out: Fifo custom trigger levels
* XR16C85x only */

Definition at line 77 of file m32r_sio_reg.h.

#define UART_TX   M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */

Definition at line 75 of file m32r_sio_reg.h.